公开(公告)号：CA2719727A1

公开(公告)日：2009-12-17

申请号：CA2719727

申请日：2009-03-30

Applicant: IBM

Inventor： CLEVENGER LAWRENCE ,  DALTON TIMOTHY ,  HSU LOUIS ,  RADENS CARL

IPC: H02J17/00 ,  H02J7/00 ,  H04W88/02

Abstract: A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.

公开(公告)号：DE10296608T5

公开(公告)日：2004-04-22

申请号：DE10296608

申请日：2002-04-08

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DYER THOMAS W ,  KUDELKA STEPHAN ,  PRAKASH V C JAI ,  RADENS CARL

IPC: H01L27/108 ,  H01L21/8242 ,  G11C11/00

Abstract: A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.

公开(公告)号：AT551727T

公开(公告)日：2012-04-15

申请号：AT04702490

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER ,  DORIS BRUCE ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

Abstract: A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.

公开(公告)号：DE602007013472D1

公开(公告)日：2011-05-05

申请号：DE602007013472

申请日：2007-12-04

Applicant: IBM

Inventor： GAIDIS MICHAEL C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  DEBROSSE JOHN K ,  HSU LOUIS L ,  RADENS CARL ,  WONG KEITH K ,  YANG CHIH-CHAO

IPC: G11C19/08 ,  G11B5/008

公开(公告)号：DE102004060891A1

公开(公告)日：2005-08-11

申请号：DE102004060891

申请日：2004-12-17

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： RADENS CARL ,  DYER THOMAS W ,  SUNG CHUN-YUNG ,  DIVAKARUNI RAMACHANDRA ,  RAMACHANDRAN RAVIKUMAR

IPC: H01L21/8242 ,  H01L29/94 ,  H01L27/108

公开(公告)号：DE69809868T2

公开(公告)日：2003-10-09

申请号：DE69809868

申请日：1998-09-25

Applicant: SIEMENS AG ,  IBM

Inventor： GRUENING ULRIKE ,  BEINTNER JOCHEN ,  RADENS CARL

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/31 ,  H01L21/316 ,  H01L21/318 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/762

Abstract: A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.

公开(公告)号：DE69809868D1

公开(公告)日：2003-01-16

申请号：DE69809868

申请日：1998-09-25

Applicant: SIEMENS AG ,  IBM

Inventor： GRUENING ULRIKE ,  BEINTNER JOCHEN ,  RADENS CARL

IPC: H01L21/76 ,  H01L21/308 ,  H01L21/31 ,  H01L21/316 ,  H01L21/318 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/762

Abstract: A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.

公开(公告)号：DE112020002838T5

公开(公告)日：2022-02-24

申请号：DE112020002838

申请日：2020-06-15

Applicant: IBM

Inventor： XIE RUILONG ,  RADENS CARL ,  CHENG KANGGUO ,  BASKER VEERARAGHAVAN

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H10B10/00

Abstract: Ein Verfahren zum Bilden einer Halbleiterstruktur weist auf: Bilden von Fins über einem Substrat, Bilden eines die Fins umgebenden Bereichs für eine flache Grabenisolation über dem Substrat und Bilden von Nanosheet-Stapeln, die Kanäle für Nanosheet-Feldeffekttransistoren bereitstellen. Das Verfahren weist außerdem auf: Bilden eines Kanalschutzüberzugs über einem Teilbereich von Seitenwänden und einer oberen Oberfläche eines ersten Nanosheet-Stapels, der über einem ersten Fin ausgebildet ist, wobei der Kanalschutzüberzug des Weiteren über einem Teilbereich des Bereichs für eine flache Grabenisolation gebildet wird, der sich von den Seitenwänden des ersten Nanosheet-Stapels in Richtung zu einem zweiten Nanosheet-Stapel erstreckt, der über einem zweiten Fin ausgebildet ist. Das Verfahren weist des Weiteren auf: Bilden von Gate-Stapeln, die freiliegende Bereiche der Nanosheet-Stapel umgeben, Bilden einer asymmetrischen selbstausgerichteten Gate-Isolations-Struktur über dem Kanalschutzüberzug und Bilden einer symmetrischen selbstausgerichteten Gate-Isolations-Struktur über einem Teilbereich des Bereichs für eine flache Grabenisolation zwischen einem dritten Fin und einem vierten Fin.

公开(公告)号：CA2719727C

公开(公告)日：2017-01-03

申请号：CA2719727

申请日：2009-03-30

Applicant: IBM

Inventor： CLEVENGER LAWRENCE ,  DALTON TIMOTHY ,  HSU LOUIS ,  RADENS CARL

IPC: H02J50/20 ,  H02J7/00 ,  H02J50/80 ,  H04W88/02

Abstract: A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging.