公开(公告)号：GB2512783A

公开(公告)日：2014-10-08

申请号：GB201412764

申请日：2013-01-03

Applicant: IBM

Inventor： COONEY EDWARD C ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  LEE TOM C ,  LIU XIAO HU

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures (10), and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire (44, 45) in a dielectric layer (18) and annealing the first wire in an oxygen- free atmosphere. After the first wire is annealed, a second wire (60, 61) is formed in vertical alignment with the first wire. A final passivation layer (74), which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.

公开(公告)号：DE112013000373T5

公开(公告)日：2014-08-28

申请号：DE112013000373

申请日：2013-01-03

Applicant: IBM

Inventor： COONEY EDWARD C ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  LEE TOM C ,  LIU XIAO H

IPC: H01L21/00

Abstract: Verfahren zum Herstellen einer Back-End-of-Line(BEOL)-Verdrahtungsstruktur, BEOL-Verdrahtungsstrukturen (10) sowie Entwurfsstrukturen für eine BEOL-Verdrahtungsstruktur. Die BEOL-Verdrahtungsstruktur kann mittels Bilden eines ersten Drahtes (44, 45) in einer dielektrischen Schicht (18) und Wärmebehandeln des ersten Drahtes in einer sauerstofffreien Umgebung hergestellt werden. Nach der Wärmebehandlung des ersten Drahtes wird ein zweiter Draht (60, 61) in vertikaler Ausrichtung zu dem ersten Draht gebildet. Es wird eine abschließende Passivierungsschicht (74) gebildet, die aus einem organischen Material wie beispielsweise Polyimid besteht, welche eine Gesamtheit einer Seitenwand des zweiten Drahtes bedeckt.

公开(公告)号：GB2508749A

公开(公告)日：2014-06-11

申请号：GB201403444

申请日：2012-07-18

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  NOGAMI TAKESHI ,  GAMBINO JEFFREY P ,  HUANG QIANG ,  RODBELL KENNETH P

IPC: H01L21/768 ,  H01L21/288 ,  H01L23/532

Abstract: A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90nm technologies. Preferably, bamboo grains are separated at distances less than the "Blech" length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.

公开(公告)号：GB2494362A

公开(公告)日：2013-03-06

申请号：GB201300268

申请日：2011-06-23

Applicant: IBM

Inventor： GAMBINO JEFFREY P ,  MOON MATTHEW D ,  MURPHY WILLIAM J ,  NAKOS JAMES S ,  PASTEL PAUL W ,  PHILIPS BRETT A

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/78

Abstract: Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator (18) layer of a CMOS structure (10). The method further includes forming a top plate (32) and a bottom plate (28) over the barrier layer. The method further includes forming a ferro-electric material (30) between the top plate (32) and the bottom plate (28). The method further includes encapsulating the barrier layer, top plate (32), bottom plate (28) and ferro-electric material (30) with an encapsulating material (36). The method further includes forming contacts (20) to the top plate (32) and bottom plate (28), through the encapsulating material (36). At least the contact (20) to the top plate (32) and a contact (20) to a diffusion of the CMOS structure are in electrical connection through a common wire.

公开(公告)号：CA2719684A1

公开(公告)日：2009-12-10

申请号：CA2719684

申请日：2009-06-04

Applicant: IBM

Inventor： JAFFE MARK D ,  GAMBINO JEFFREY P ,  LEIDY ROBERT K ,  MUSANTE CHARLES F ,  RASSEL RICHARD J

IPC: H01L27/00

Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer (22) with respect to a planarizing layer (18) within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer (20') of different dimensions than active lens layer (20) located over a circuitry portion (Rl) of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture (A) within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion (Rl) within the particular image sensor structures.

公开(公告)号：HK1032293A1

公开(公告)日：2001-07-13

申请号：HK01102845

申请日：2001-04-23

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： RAMA DIVAKARUNI ,  GAMBINO JEFFREY P ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78 ,  H01L

Abstract: The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significantly reduced by a device structure which allows a reduced gap aspect ratio while maintaining low sheet resistance values. A reduced gap aspect ratio also relaxes the need for highly reflowable dielectric materials and also facilitates the use of angled source-drain (S-D) and halo implants. Also provided is a novel structure and process for producing a MOSFET channel, lateral doping profile which suppresses short channel effects while providing low S-D junction capacitance and leakage, as well as immunity to hot-carrier effects. This also affords the potential for reduction in the contact stud-to-gate conductor capacitance, because borderless contacts can be formed with an oxide gate sidewall spacer. As a result, the S-D junctions can be doped independently of the gate conductor doping, more easily allowing a variety of MOSFET structures.

公开(公告)号：GB2508749B

公开(公告)日：2015-12-02

申请号：GB201403444

申请日：2012-07-18

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  NOGAMI TAKESHI ,  GAMBINO JEFFREY P ,  HUANG QIANG ,  RODBELL KENNETH P

IPC: H01L21/768 ,  H01L21/288 ,  H01L23/532

Abstract: A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90 nm technologies. Preferably, bamboo grains are separated at distances less than the “Blech” length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.

公开(公告)号：DE112012002979T5

公开(公告)日：2014-04-30

申请号：DE112012002979

申请日：2012-06-29

Applicant: IBM

Inventor： DUNBAR THOMAS J ,  JAFFE MARK D ,  WOLF RANDY L ,  CANDRA PANGLIJEN ,  ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  STAMPER ANTHONY K

IPC: H03H9/64

Abstract: Hierin wird ein Oberflächen-Schallwellen(SAW)-Filter und ein Verfahren zur Herstellung desselben offenbart. Der SAW-Filter umfasst ein piezoelektrisches Substrat (110; 3); eine ebene Barriereschicht (120), welche über dem piezoelektrischen Substrat angeordnet ist, und mindestens einen Leiter (130), welcher in dem piezoelektrischen Substrat und der ebenen Barriereschicht vergraben ist.

公开(公告)号：DE102013200215A1

公开(公告)日：2013-07-25

申请号：DE102013200215

申请日：2013-01-10

Applicant: IBM

Inventor： CANDRA PANGLIJEN ,  DUNBAR THOMAS J ,  JAFFE MARK D ,  STAMPER ANTHONY K ,  WOLF RANDY L ,  GAMBINO JEFFREY P ,  ADKISSON JAMES W

IPC: H03H9/64 ,  H01L41/08 ,  H03H3/08

Abstract: Hierin werden schaltbare und/oder abstimmbare Filter, Herstellungsverfahren und Entwurfsstrukturen offenbart. Das Verfahren zum Bilden der Filter schließt das Bilden mindestens einer piezoelektrischen Filterstruktur ein, die eine Vielzahl von Elektroden aufweist, die auf einem piezoelektrischen Substrat gebildet sind. Das Verfahren schließt außerdem das Bilden einer feststehenden Elektrode mit einer Vielzahl von Fingern auf dem piezoelektrischen Substrat ein. Das Verfahren schließt zudem das Bilden einer beweglichen Elektrode mit einer Vielzahl von Fingern über dem piezoelektrischen Substrat ein. Das Verfahren schließt außerdem das Bilden von Betätigungselementen ein, die mit einem oder mehreren von der Vielzahl von Fingern der beweglichen Elektrode ausgerichtet sind.

公开(公告)号：CA2719681A1

公开(公告)日：2009-11-19

申请号：CA2719681

申请日：2009-05-05

Applicant: IBM

Inventor： ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  GAMBINO JEFFREY P ,  MUSANTE CHARLES F

IPC: H01L31/112 ,  H01L31/0236

Abstract: Protuberances (5), having vertical (h) and lateral (p) dimensions less than the wavelength range of lights detectable by a photodiode (8), are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sub lithographic features of a first polymeric block component (112) within a matrix of a second polymeric block component (111). The pattern of the polymeric block component is transferred into a first optical layer (4) to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.