中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

100 records (took 0.029 seconds)

    61.
    发明专利
    未知

    公开(公告)号：FR2790598A1

    公开(公告)日：2000-09-08

    申请号：FR9902513

    申请日：1999-03-01

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  ALIEU JEROME

    IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L29/10 ,  H01L29/772 ,  H01L29/161

    Abstract: A transistor has an indium-doped Si-Ge buried layer located in a region of a silicon channel. An indium-implanted transistor has a silicon channel region in which a buried layer of an indium-implanted alloy Si1-xGex, where 10 ≤ x ≤ 4 x 10 , preferably 10 ≤ x ≤ 10 . The amount of implanted indium is 1 x 10 -4 x 10 atoms/cm , preferably 5 x 10 -5 x 10 atoms/cm . The implanted indium has an implantation profile that is electrically active, retrograde and stable, and approaches the profile of indium chemical retrograde implantation. Independent claims are given for methods of production of the transistor. One method comprises: (a) producing, on at least one zone in the surface of a silicon substrate, the zone being intended to form a region of a transistor channel, a multilayered composite film comprising, successively from the initial surface of the substrate, at least one Si1-xGex alloy layer, as above, and an external silicon layer of at least 5 nm thickness; (b) implanting indium into the Si1-xGex alloy layer; and (c) completing the fabrication of a transistor in order to obtain a transistor whose channel region comprises a buried layer of indium-implanted Si1-xGex.

    Production of field effect transistors with reduced short channel effects and offering an elevated degree of integration for Silicon On Insulator integrated circuits
    63.
    发明专利
    Production of field effect transistors with reduced short channel effects and offering an elevated degree of integration for Silicon On Insulator integrated circuits 未知

    公开(公告)号：FR2865850A1

    公开(公告)日：2005-08-05

    申请号：FR0401018

    申请日：2004-02-03

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  CHANEMOUGAME DANIEL ,  MONFRAY STEPHANE

    IPC: H01L21/336 ,  H01L29/786 ,  H01L29/423

    Abstract: The production of a field effect transistor comprises: (A) obtaining a conductor substrate (100) supporting a portion of semiconductor material above a surface (S), with a portion of temporary material between it and the substrate; (B) forming a gate (2) comprising an upper part (C) in rigid liaison with the semiconductor material and a support part (A) resting on the substrate, the gate being obtained such that it is electrically insulated with respect to the semiconductor material and the conductor substrate; (C) removing the temporary material, the gate assuring the retention of the semiconductor material portion with respect to the substrate, in a manner to create an empty space between the semiconductor material portion and the substrate in place of the temporary material; (D) filling, at least partially, the empty space with an insulating material. Independent claims are also included for: (A) a field effect transistor produced by the method; (B) an integrated circuit incorporating this field effect transistor.

    Method for manufacturing an insulated-gate field-effect transistor with constrained channel, and integrated circuit comprising such transistor
    65.
    发明专利
    Method for manufacturing an insulated-gate field-effect transistor with constrained channel, and integrated circuit comprising such transistor 未知

    公开(公告)号：FR2838237A1

    公开(公告)日：2003-10-10

    申请号：FR0204165

    申请日：2002-04-03

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  BENSAHEL DANIEL

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/786 ,  H01L27/105

    Abstract: The transistor (T) is situated above a base layer (1) formed on a semiconductor substrate (SB) of a relaxed silicon-germanium alloy, and comprises under the insulated gate (7) a first constrained silicon layer (2) rested on the base layer (1), a buried insulator layer (10) and a second constrained silicon layer (4) extending between the regions of the source (S) and the drain (D) of the transistor. The thickness of the two constrained silicon layers (2,4) and that of the intermediate insulator layer (10) is much less than that of the base layer, and it is a few tens of nanometres, for example 20 nm. The thickness of the base layer (1) is of the order of a few micrometres, for example 2 micrometres. The manufacturing method comprises the formation of the base layer (1) on the silicon substrate (SB), the first constrained silicon layer (2), an intermediate layer of silicon-germanium, the second constrained silicon layer (4), the insulated gate (7) of the transistor flanked by insulating regions (8), an etching of the intermediate layer so to form a tunnel below the insulated gate, filling the tunnel with an insulator material (10), and the formation of the regions of the source (S) and the drain (D). The two constrained silicon layers (2,4) and the intermediate layer are formed by non-selective epitaxy, and an isolation zone (5) is formed in upper part of the base layer compatible with non-relaxation of constraints in the constrained silicon layers.

    66.
    发明专利
    未知

    公开(公告)号：FR2812764B1

    公开(公告)日：2003-01-24

    申请号：FR0010176

    申请日：2000-08-02

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  HAOND MICHEL ,  DUTARTRE DIDIER

    IPC: H01L21/762 ,  H01L21/328

    Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

    67.
    发明专利
    未知

    公开(公告)号：FR2819341A1

    公开(公告)日：2002-07-12

    申请号：FR0100295

    申请日：2001-01-11

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  MONFRAY STEPHANE ,  MALLARDEAU CATHERINE

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of N+ doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.

    69.
    发明专利
    未知

    公开(公告)号：FR2800913A1

    公开(公告)日：2001-05-11

    申请号：FR9914105

    申请日：1999-11-10

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  MALLARDEAU CATHERINE

    IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/92 ,  H01G4/33 ,  H01G4/38

    Abstract: The invention concerns a method which consists in forming on a substrate coated with a dielectric material layer provided with a window a stack of successive layers alternately of germanium or SiGe alloy and polycrystalline silicon; selective partial elimination of the germanium or SiGe alloy layers, to form an arborescent structure; forming a thin layer of dielectric material on the arborescent structure; and coating the arborescent structure with polycrystalline silicon. The invention is useful for making direct access dynamic memories.

    70.
    发明专利
    未知

    公开(公告)号：FR2799305A1

    公开(公告)日：2001-04-06

    申请号：FR9912406

    申请日：1999-10-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA

    IPC: H01L21/336 ,  H01L29/786

    Abstract: Gate-all-around (GAA) architecture semiconductor device production, by gate formation around a bridge structure formed by removing material below a silicon layer (5) having a thin single crystal central portion (5a), is new. A semiconductor device of GAA architecture is produced from a substrate (1) having a central active semiconductor region (2) surrounded by a peripheral insulating region (3) by (a) selective epitaxy of a single crystal Ge or SiGe alloy layer on the active region main surface; (b) non-selective epitaxy of a silicon layer (5) which is monocrystalline above the single crystal layer and which is polycrystalline above the insulating region surface; (c) masking and etching of the silicon layer (5) and the single crystal layer to form, on the active region main surface, a stack with two opposite side walls exposing the single crystal layer; (d) selective etching away of the single crystal layer so that the silicon layer forms a bridge structure having side walls, an external surface and an internal surface defining, with the active region main surface, a tunnel (7); (e) formation of a dielectric thin film (8, 9), which does not fill the tunnel, on the external and internal surfaces and on the side walls of the bridge structure; (f) deposition of conductive material to cover the bridge structure and to fill the tunnel; and (g) masking and etching of the conductive material to form an all-around gate region (10) of desired dimensions and geometry. An Independent claim is also included for a semiconductor device produced by the above process, the central part (5a) of the bridge structure (5) being of single crystal silicon and being 1-50 nm thick.

Patent Agency Ranking