公开(公告)号：KR1020080030201A

公开(公告)日：2008-04-04

申请号：KR1020060095964

申请日：2006-09-29

Applicant: 삼성전자주식회사

Inventor： 안종선 ,  김준 ,  김진홍 ,  남정림 ,  방석철 ,  정은국 ,  이준원 ,  전열 ,  고기형 ,  이영미

IPC: H01L21/336

Abstract: A semiconductor device and a method for forming the same are provided to reduce a short channel effect by increasing a channel length of a transistor due to a protrusive upper gate electrode. A first interlayer dielectric(108) is formed on a semiconductor substrate(100). One or more trench(114) is formed on an upper surface of the first interlayer dielectric. The trench is filled with a first gate electrode(106). A first semiconductor pattern is formed on an upper surface of the first gate electrode. A first gate insulating layer(104) is inserted between the first gate electrode and the first semiconductor pattern. The first gate electrode is extended in a cross direction. The first semiconductor pattern crosses the first gate electrode.

Abstract translation: 提供一种半导体器件及其形成方法，以通过增加由于突出的上栅电极引起的晶体管的沟道长度来减小短沟道效应。 在半导体衬底（100）上形成第一层间电介质（108）。 一个或多个沟槽（114）形成在第一层间电介质的上表面上。 沟槽填充有第一栅电极（106）。 第一半导体图案形成在第一栅电极的上表面上。 第一栅极绝缘层（104）插入在第一栅电极和第一半导体图案之间。 第一栅电极沿横向延伸。 第一半导体图案与第一栅电极交叉。

公开(公告)号：KR100757337B1

公开(公告)日：2007-09-11

申请号：KR1020060090282

申请日：2006-09-18

Applicant: 삼성전자주식회사

Inventor： 김창섭 ,  남정림 ,  김원진 ,  연국현

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/4234 ,  H01L29/792 ,  H01L27/11578

Abstract: A charge trap-type non-volatile memory device and a method for manufacturing the same are provided to decrease the malfunction due to charge spreading by preventing the free carriers from escaping from a silicon nitride layer pattern. A charge trap structure is formed on a substrate(100), and includes a tunnel oxide layer pattern(102a) and a silicon nitride layer pattern(104a) for charge trap. A gap of the charge trap structure is buried by an interlayer dielectric(112), while exposing an upper surface of the silicon nitride layer pattern. The silicon nitride layer pattern and the interlayer dielectric are covered by a dielectric layer(126). An electrode pattern is positioned on the dielectric layer at a position to opposite to the charge trap structure.

Abstract translation: 提供电荷陷阱型非易失性存储器件及其制造方法，以通过防止游离载流子从氮化硅层图案中逸出而减少由于电荷扩展引起的故障。 电荷陷阱结构形成在基板（100）上，并且包括用于电荷阱的隧道氧化物层图案（102a）和氮化硅层图案（104a）。 电荷陷阱结构的间隙通过层间电介质（112）掩埋，同时暴露氮​​化硅层图案的上表面。 氮化硅层图案和层间电介质被介电层（126）覆盖。 电极图案位于与电荷陷阱结构相反的位置处的电介质层上。

公开(公告)号：KR100752674B1

公开(公告)日：2007-08-29

申请号：KR1020060101029

申请日：2006-10-17

Applicant: 삼성전자주식회사

Inventor： 고차원 ,  조한구 ,  남정림 ,  여기성 ,  박준수 ,  이지영

IPC: H01L21/027

公开(公告)号：KR1020060133166A

公开(公告)日：2006-12-26

申请号：KR1020050052851

申请日：2005-06-20

Applicant: 삼성전자주식회사

Inventor： 김원진 ,  남정림 ,  오정민 ,  정병홍 ,  박흥식

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/823468

Abstract: A method for forming a gate in a non-volatile memory device is provided to prevent oxidation of a tungsten layer and prevent permeation of chemicals into the tungsten layer by covering a sidewall of the tungsten layer with an insulating layer spacer. A tunnel oxide layer(102), a floating gate layer, and a dielectric layer are formed on a semiconductor substrate(100). A control gate layer is formed by laminating a polysilicon layer and a tungsten layer on the dielectric layer. A first hard mask layer is formed by inserting an adhesive layer into the control gate layer. A first hard mask layer pattern(118a) is formed by patterning the first hard mask layer. The control gate layer is etched by using the first hard mask layer as an etch mask. An insulating layer spacer(128a) is formed on a sidewall of an etched part of the control gate layer. A control gate(115a) including a polysilicon layer pattern and a tungsten layer pattern is formed by etching the polysilicon layer. A dielectric layer pattern(108a) and a floating gate(104a) are formed by etching the dielectric layer and the floating gate layer.

Abstract translation: 提供了一种用于在非易失性存储器件中形成栅极的方法，以防止钨层的氧化，并且通过用绝缘层间隔物覆盖钨层的侧壁来防止化学物质渗透到钨层中。 在半导体衬底（100）上形成隧道氧化物层（102），浮栅层和电介质层。 通过在电介质层上层叠多晶硅层和钨层来形成控制栅极层。 通过将粘合剂层插入到控制栅极层中来形成第一硬掩模层。 通过图案化第一硬掩模层形成第一硬掩模层图案（118a）。 通过使用第一硬掩模层作为蚀刻掩模蚀刻控制栅极层。 绝缘层间隔物（128a）形成在控制栅极层的蚀刻部分的侧壁上。 通过蚀刻多晶硅层形成包括多晶硅层图案和钨层图案的控制栅极（115a）。 通过蚀刻介电层和浮栅，形成电介质层图案（108a）和浮栅（104a）。

公开(公告)号：KR100555484B1

公开(公告)日：2006-03-03

申请号：KR1019990037313

申请日：1999-09-03

Applicant: 삼성전자주식회사

Inventor： 이창원 ,  나영섭 ,  남정림 ,  정우인

IPC: H01L21/3205

Abstract: 반도체 장치의 텅스텐 배선 제조 방법을 개시한다. 본 발명의 일 관점은, 반도체 기판 상에 텅스텐(W)층, 티타늄 질화물(TiN)로 이루어지는 하드 마스크층(hard mask layer)을 형성한다. 하드 마스크층 상에 반사 방지층을 개재하는 사진 공정으로 딥 유비 포토레지스트 패턴(deep UV photoresist pattern)을 형성한다. 딥 유비 포토레지스트 패턴에 의해서 노출되는 하드 마스크층을 식각하여 하드 마스크 패턴을 형성한다. 하드 마스크 패턴에 의해서 노출되는 텅스텐층을 식각하여 텅스텐 패턴을 형성한 후, 하드 마스크 패턴을 제거한다.

公开(公告)号：KR100462887B1

公开(公告)日：2004-12-17

申请号：KR1020020064641

申请日：2002-10-22

Applicant: 삼성전자주식회사

Inventor： 유문현 ,  남정림 ,  김유현 ,  박철홍 ,  최수한 ,  반용찬 ,  신혜수 ,  김동현

IPC: H01L21/027

CPC classification number: G03F1/34 ,  G03F1/70

Abstract: 본 발명은 반도체 기판에 위상 변이 마스크(PHASE SHIFT MASK)와 트림 마스크(TRIM MASK)를 이용하여 두 차례 노광으로 취약해진 필드 영역에 위치한 필드 게이트 이미지의 폭 강화와, 이를 통한 반도체 장치의 전류 구동능력을 극대화하려고 상기 필드(FIELD) 게이트 이미지의 폭을 보강하는 위상 에지 위상 변이 마스크(PHASE EDGE PHASE SHIFT MASK)및 제조방법이다.

Abstract translation: 一种相位相移掩模及其制造方法，用于通过在半导体衬底上使用相移掩模和修剪掩模来强化位于通过两次曝光处理削弱的场区域上的场栅图像的宽度， 并施加栅极栅极图像的宽度以最大化半导体器件的电流驱动能力。

公开(公告)号：KR1020040035480A

公开(公告)日：2004-04-29

申请号：KR1020020064641

申请日：2002-10-22

Applicant: 삼성전자주식회사

Inventor： 유문현 ,  남정림 ,  김유현 ,  박철홍 ,  최수한 ,  반용찬 ,  신혜수 ,  김동현

IPC: H01L21/027

CPC classification number: G03F1/34 ,  G03F1/70

Abstract: PURPOSE: A phase edge phase shift mask for compensating a width of a field gate image and a fabricating method thereof are provided to reduce loss of photoresist by controlling an overlapping interval among the first to the third trim patterns within a shifter and a trim mask or removing a notch structure between the first to the third trim patterns within the trim mask. CONSTITUTION: A phase edge phase shift mask for compensating a width of a field gate image includes a phase shift mask, a trim mask(100). The phase shift mask is formed with an opaque region for defining a plurality of shifters(105). The trim mask(100) is formed with the first trim pattern(150), the second trim pattern(160), and the third trim patterns(120,140) which are overlapped on the phase shift mask. The first trim pattern(150) corresponds to the opaque region between the shifters(105). The second trim pattern(160) is connected to the first trim pattern. The third trim patterns(120,140) are close to a selected side of the first and the second trim patterns.

Abstract translation: 目的：提供用于补偿场栅图像的宽度的相位相移掩模及其制造方法，以通过控制移位器和修剪掩模之间的第一至第三修剪图案之间的重叠间隔来减少光致抗蚀剂的损耗，或 去除修剪掩模内的第一至第三修剪图案之间的切口结构。 构成：用于补偿场栅图像的宽度的相位相移掩模包括相移掩模，修剪掩模（100）。 相移掩模形成有用于限定多个移位器（105）的不透明区域。 修剪掩模（100）形成有重叠在相移掩模上的第一修剪图案（150），第二修剪图案（160）和第三修剪图案（120,140）。 第一修剪图案（150）对应于移位器（105）之间的不透明区域。 第二修剪图案（160）连接到第一修剪图案。 第三修剪图案（120,140）靠近第一和第二修剪图案的选定侧。

公开(公告)号：KR1020030081995A

公开(公告)日：2003-10-22

申请号：KR1020020020470

申请日：2002-04-15

Applicant: 삼성전자주식회사

Inventor： 여인준 ,  윤병문 ,  김경현 ,  하상록 ,  남정림 ,  조현호

IPC: H01L21/304

CPC classification number: H01L21/67051 ,  B08B3/12 ,  Y10S134/902

Abstract: PURPOSE: A wafer cleaning equipment is provided to be capable of preventing the damage of patterns formed at the upper portion of the wafer by using high frequency acoustic energy. CONSTITUTION: A wafer cleaning equipment is provided with a cleaning material supply part for forming a cleaning material layer(300) on the surface of a wafer(100), an energy condensing alleviation part(200) installed at one side of the wafer for prolonging the cleaning material layer to the outside of the wafer, a bar type probe(400) located across the energy condensing alleviation part parallel with the upper surface of the wafer for supplying high frequency acoustic vibration energy, a vibrator(500) connected to the rear portion of the probe for generating acoustic vibration. Preferably, the wafer cleaning equipment further includes a rotating shaft for rotating the wafer.

Abstract translation: 目的：提供晶片清洁设备，以便能够通过使用高频声能来防止在晶片上部形成的图案的损坏。 构成：晶片清洁设备设置有用于在晶片（100）的表面上形成清洁材料层（300）的清洁材料供应部件，安装在晶片一侧的能量冷凝减轻部件（200），用于延长 所述清洁材料层到所述晶片的外部;棒状探针（400），位于与所述晶片的上表面平行的用于提供高频声波振动能的平面上的所述能量冷凝减轻部分;振动器（500），连接到所述后部 用于产生声振动的探头部分。 优选地，晶片清洁设备还包括用于旋转晶片的旋转轴。

公开(公告)号：KR1020030027393A

公开(公告)日：2003-04-07

申请号：KR1020010060579

申请日：2001-09-28

Applicant: 삼성전자주식회사

Inventor： 김광복 ,  하상록 ,  남정림 ,  김경현 ,  조민수

IPC: H01L27/10

Abstract: PURPOSE: A method for fabricating a semiconductor device is provided to minimize a defect caused by a step in a polishing process by forming a conductive layer as a gate electrode and by partially etching the conductive layer in a high-stepped cell region so that the height of the conductive layer is reduced. CONSTITUTION: A gate oxide layer is formed on a semiconductor substrate having a cell region and a peripheral region. Structures whose side surface has a vertical profile are formed on the cell region. A conductive layer is continuously formed on the sidewall and upper surface of the structures, the surface of the cell region and the peripheral region. The first nitride layer pattern(120) is selectively formed only in the peripheral region. The conductive layer formed in the cell region is partially and anisotropically etched to lower the height of the conductive layer in the cell region by using the first nitride layer pattern as a mask. The second nitride layer is continuously formed on the conductive layer in the cell region and on the first nitride layer pattern in the peripheral region. The resultant structure is polished to eliminate the conductive layer formed on the structures in the cell region. The nitride layer left in the cell region and the peripheral region is removed. The conductive layer in the cell region and the peripheral region is patterned to form a gate electrode on both sidewalls of the structures while a gate line is formed in the peripheral region.

Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过形成导电层作为栅电极并且通过部分地蚀刻高阶阶电池区域中的导电层来最小化由抛光工艺中的步骤引起的缺陷，使得高度 的导电层减少。 构成：在具有单元区域和周边区域的半导体基板上形成栅极氧化层。 在单元区域上形成侧面具有垂直剖面的结构。 在结构的侧壁和上表面，电池区域的表面和周边区域上连续地形成导电层。 第一氮化物层图案（120）仅在周边区域中选择性地形成。 通过使用第一氮化物层图案作为掩模，在单元区域中形成的导电层被部分地和各向异性地蚀刻以降低单元区域中的导电层的高度。 第二氮化物层连续地形成在电池区域的导电层上和周边区域中的第一氮化物层图案上。 对所得到的结构进行抛光以消除在单元区域中形成的结构上的导电层。 残留在单元区域和外围区域中的氮化物层被去除。 在单元区域和外围区域中的导电层被图案化以在结构的两个侧壁上形成栅电极，同时在周边区域中形成栅极线。

公开(公告)号：KR100366633B1

公开(公告)日：2003-01-09

申请号：KR1020000061987

申请日：2000-10-20

Applicant: 삼성전자주식회사

Inventor： 이석주 ,  양희홍 ,  남정림

IPC: H01L21/28

CPC classification number: H01L21/76807 ,  H01L21/76813

Abstract: A method of forming a contact hole for a dual damascene interconnection of a semiconductor device includes forming a first photoresist layer pattern on an insulating layer of a semiconductor substrate, the first photoresist layer pattern having a first opening with a first width. A groove having the first width to a prescribed depth of the insulating layer is formed by performing an etching process using the first photoresist layer pattern as an etch mask. A second photoresist layer pattern on the insulating layer having the groove therein is formed. The second photoresist layer has a second opening with a second width, wherein the second width is substantially equal to or larger than the first width of the groove. A contact hole exposing the semiconductor substrate is formed by performing an etching process using the second photoresist layer pattern as an etch mask.

Abstract translation: 一种形成用于半导体器件的双镶嵌互连的接触孔的方法包括在半导体衬底的绝缘层上形成第一光致抗蚀剂层图案，第一光致抗蚀剂层图案具有第一宽度的第一开口。 通过使用第一光致抗蚀剂层图案作为蚀刻掩模执行蚀刻工艺来形成具有第一宽度到绝缘层的规定深度的凹槽。 在其中形成有凹槽的绝缘层上形成第二光致抗蚀剂层图案。 第二光致抗蚀剂层具有第二宽度的第二开口，其中第二宽度基本上等于或大于凹槽的第一宽度。 通过使用第二光刻胶层图案作为蚀刻掩模执行蚀刻工艺来形成暴露半导体衬底的接触孔。