公开(公告)号：EP1858308B1

公开(公告)日：2012-04-18

申请号：EP06781090.3

申请日：2006-07-07

Applicant: Ibiden Co., Ltd.

Inventor： TAKAHASHI, Michimasa, c/o IBIDEN CO., LTD. ,  MIKADO, Yukinobu, c/o IBIDEN CO., LTD. ,  NAKAMURA, Takenobu, c/o IBIDEN CO., LTD. ,  AOYAMA, Masakazu, c/o IBIDEN CO., LTD.

IPC: H05K3/46

CPC classification number: H05K3/421 ,  H05K1/115 ,  H05K3/423 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09709 ,  H05K2201/09863 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/31511

Abstract: In a multilayer printed wiring board, insulating layers and conductor layers are alternately stacked, and the conductor layers are electrically connected through via holes arranged on the insulating layers. The via hole is formed to have a swell at least on a part of it, in a substantially vertical direction to a thickness direction of the insulating layer. External stresses, such as a force of impact when dropped, are suppressed to have an insulating substrate not to easily warp, and cracks, disconnection, and the like of the conductor circuit are prevented. Thus, deterioration of reliability and drop impact resistance of a mounting substrate can be reduced.

Abstract translation: 在多层印刷线路板中，绝缘层和导体层交替堆叠，并且导体层通过设置在绝缘层上的通孔电连接。 通孔形成为在与绝缘层的厚度方向大致垂直的方向上至少在其一部分上具有隆起。 外部应力如下降时的冲击力被抑制，以使绝缘基板不易翘曲，并且防止导体电路的裂纹，断开等。 因此，可以降低安装基板的可靠性和耐跌落冲击性的劣化。

公开(公告)号：EP1484952A4

公开(公告)日：2008-04-23

申请号：EP03703355

申请日：2003-02-21

Applicant: FUJIKURA LTD

Inventor： ITO SHOUJI ,  NAKAO OSAMU ,  HIGUCHI REIJI ,  OKAMOTO MASAHIRO

IPC: H05K3/38 ,  H05K3/40 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K3/4617 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0394 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0191 ,  H05K2203/1453 ,  Y10T29/49165 ,  Y10T428/12181 ,  Y10T428/24917

Abstract: A base for multilayer wiring boards in which a conductive layer (112) forming a wiring pattern is provided on one side of an insulating base (insulating resin layer (111)), and an adhesive layer (113) for interlayer adhesion is provided on the other side, and a through hole (114) extending through the conductive layer, the insulating base, and the adhesive layer is filled with a conductive resin composition (115) for interlayer electrical connection. The diameter of the conductive layer portion (114b) of the through hole is smaller than those of the insulating base portion and the adhesive layer portion (114a). The electrical connection between the conductive resin composition and the conductive layer is ensured through the back (112a) of the conductive layer.

公开(公告)号：EP1843650A3

公开(公告)日：2007-11-07

申请号：EP07013524.9

申请日：1999-07-30

Applicant: IBIDEN CO., LTD.

Inventor： Hirose, Naohiro ,  Noda, Kouta ,  Segawa, Hiroshi ,  En, Honjin ,  Tsukada, Kiyotaka ,  Ishida, Naoto ,  Asano, Kouji ,  Shouda, Atsushi

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A multilayered printed circuit board comprising: a substrate (330) on which a conductive circuit (334) is formed; an interlayer insulating resin layer (350) formed on the conductive circuit (334); an opening (348) for forming a via hole (360) formed in the interlayer insulating resin layer (350); and another conductive circuit (358) including a via hole (360) and formed on the interlayer insulating resin layer (350), wherein
the surface of the conductive circuit (334) is subjected to a coarsening process using etching solution containing cupric complex and organic acid, and
stripe pits and projections are formed on the inner wall of the opening (348) for forming the via hole (360).

Abstract translation: 一种多层印刷电路板，包括：衬底（330），其上形成有导电电路（334）; 形成在导电电路（334）上的层间绝缘树脂层（350）; 用于形成层间绝缘树脂层（350）中形成的通路孔（360）的开口（348）; 以及形成在层间绝缘树脂层（350）上的包括通路孔（360）的另一导电电路（358），其中导电电路（334）的表面经受使用包含铜络合物和有机化合物的蚀刻溶液的粗化处理 酸，并且在用于形成通孔（360）的开口（348）的内壁上形成条纹凹凸。

公开(公告)号：EP1827065A2

公开(公告)日：2007-08-29

申请号：EP07075318.1

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： Takada, Masaru c/o Ibiden Co., Ltd. ,  Tsukada, Kiyotaka c/o Ibiden Co., Ltd. ,  Kobayashi, Hiroyuki c/o Ibiden Co., Ltd. ,  Minoura, Hisashi c/o Ibiden Co., Ltd. ,  Ukai, Yoshikazu c/o Ibiden Co., Ltd. ,  Kondo, Mitsuhiro c/o Ibiden Co., Ltd.

IPC: H05K3/00 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A method of producing a printed wiring board (3) comprising a mounting recess portion (1) for mounting an electronic part, a conductor pattern (7), and a heat-sink plate (6) arranged at the bottom of the mounting recess portion (1), characterized in that a conductor pattern (7) is formed on an insulating substrate (5);
a heat-sink plate (6) is adhered to a lower face of a portion of the insulating substrate (5) forming the mounting recess portion; and
a laser beam (2) is irradiated to an upper face of the portion (10) forming the mounting recess portion to form a mounting recess portion (1).

Abstract translation: 一种印刷电路板（3）的制造方法，其特征在于，具备安装电子部件的安装凹部（1），导体图案（7），以及配置在安装凹部的底部的散热板 （1），其特征在于，在绝缘基板（5）上形成导体图案（7）。 散热板（6）粘附到形成安装凹部的绝缘基板（5）的一部分的下表面; 并且激光束（2）照射到形成安装凹部的部分（10）的上表面以形成安装凹部（1）。

公开(公告)号：EP1121008A4

公开(公告)日：2005-02-02

申请号：EP99933214

申请日：1999-07-30

Applicant: IBIDEN CO LTD

Inventor： HIROSE NAOHIRO ,  NODA KOUTA ,  SEGAWA HIROSHI ,  EN HONJIN ,  TSUKADA KIYOTAKA ,  ISHIDA NAOTO ,  ASANO KOUJI ,  SHOUDA ATSUSHI

IPC: B23K26/38 ,  H05K1/02 ,  H05K3/00 ,  H05K3/10 ,  H05K3/28 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An opening is made in a resin (20) with a laser to form a viahole. A copper foil (22) etched into a thin film (3 νm) to lower the heat conductivity is used as a conformal mask, thereby making an opening (20a) in the resin (20) by fewer times of irradiation with a pulse laser beam. This prevents formation of any undercut in the resin (20) on which an interlayer resin-insulating layer is to be formed, enabling improvement in the connection reliability of the viahole.

公开(公告)号：EP0969707A3

公开(公告)日：2000-11-22

申请号：EP99201699.8

申请日：1999-05-28

Applicant: Matsushita Electric Works, Ltd.

Inventor： Yoshioka, Hirokazu ,  Yoshida, Norio ,  Tanaka, Kenichiro

IPC: H05K3/46 ,  H05K3/00

CPC classification number: H05K3/4652 ,  H05K1/116 ,  H05K3/0035 ,  H05K3/0044 ,  H05K3/0055 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0969 ,  H05K2201/098 ,  H05K2201/09863 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/0796 ,  H05K2203/095 ,  H05K2203/1383 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/4916 ,  Y10T29/49165

Abstract: A multilayer printed wiring board (11) is formed with a plurality of conductor layers laminated as a whole with insulating layers interposed, a non-penetrating via hole (3) provided in the insulating layer (2) as bottomed by the conductor layer (1a) exposed, a plated layer (4) provided inside the via hole (3) for electric connection between the conductor layers (1a,1b), the via hole (3) being formed to be of a concave curved surface of a radius in a range of 20 to 100 µm in axially sectioned view at continuing zone of inner periphery to bottom surface of the via hole (3), whereby the equipotential surfaces occurring upon plating the plated layer (4) are curved along the continuing zone to unify the density of current for rendering the plated layer (4) uniform in the thickness without being thinned at the continuing zone.

公开(公告)号：EP0805614A4

公开(公告)日：1998-11-25

申请号：EP96938496

申请日：1996-11-18

Applicant: TOSHIBA KK

Inventor： SASAOKA KENJI ,  ODAIRA HIROSHI ,  FUJIWARA MADOKA ,  IKEGAYA FUMITOSHI ,  MORI TAKAHIRO

IPC: H01L21/48 ,  H01L23/538 ,  H05K1/09 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H01L23/48

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/095 ,  H05K1/116 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K2201/09863 ,  H05K2203/1189 ,  H05K2203/1572 ,  Y10S428/901 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A multilayered wiring board using conductive pillars for the interconnection of wiring layers. Since through holes are bored in the via lands of the wiring layers of the multilayered wiring board, the stress applied between the conductive pillars and wiring layers can be released at the time of connecting the conductive pillars to the via lands. Since the external side face of each conductive pillar smoothly continues to the surface of the via land at the contact section between the conductive pillar and the via land, the notch effect is relieved. Therefore, the reliability of the interconnection is secured even when a stress is applied to the connections during the manufacturing of the multilayered wiring board, and the mounting of electronic parts, etc.

公开(公告)号：JP6099734B2

公开(公告)日：2017-03-22

申请号：JP2015508591

申请日：2014-03-26

Applicant: 京セラ株式会社

Inventor： 梶田 智 ,  萩原 光弘 ,  松本 有平

IPC: H01L23/12 ,  H05K3/46

CPC classification number: H05K1/0306 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/09 ,  H05K1/115 ,  H05K1/181 ,  H05K3/421 ,  H05K3/4655 ,  H05K2201/0116 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2201/2072 ,  H05K3/0038 ,  H05K3/4602

公开(公告)号：JP2014154621A

公开(公告)日：2014-08-25

申请号：JP2013021214

申请日：2013-02-06

Applicant: Ibiden Co Ltd ,  イビデン株式会社

Inventor： HIBINO TOSHIAKI

IPC: H05K3/42 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K3/429 ,  H05K1/0366 ,  H05K1/0373 ,  H05K3/0032 ,  H05K3/0055 ,  H05K3/108 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/09536 ,  H05K2201/09827 ,  H05K2201/09836 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2201/2072 ,  H05K2203/108 ,  H05K2203/1476

Abstract: PROBLEM TO BE SOLVED: To provide a printed wiring board in which the connection reliability of a through hole conductor is high.SOLUTION: A through hole 28 forming a through hole conductor consists of a first aperture 28f and a second aperture 28s tapered toward the center side. The maximum diameter of a third aperture 28c interconnecting the first aperture and second aperture is larger than the diameter d2 at a minimum diameter portion 28fc of the first aperture, and the diameter d4 at a minimum diameter portion 28sc of the second aperture.

Abstract translation: 要解决的问题：提供一种通孔导体的连接可靠性高的印刷电路板。解决方案：形成通孔导体的通孔28由朝向中心渐缩的第一孔28f和第二孔28c组成 侧。 互连第一孔和第二孔的第三孔28c的最大直径大于第一孔的最小直径部分28fc处的直径d2和第二孔的最小直径部分28sc处的直径d4。

公开(公告)号：JPWO2012046640A1

公开(公告)日：2014-02-24

申请号：JP2012501475

申请日：2011-09-30

Applicant: 日本特殊陶業株式会社

Inventor： 吉田　美隆 ,  美隆 吉田 ,  宏明 山本 ,  宏明 山本

IPC: H05K1/02 ,  B23K26/00 ,  B23K26/046 ,  B23K26/082 ,  B23K26/364 ,  H05K3/00

CPC classification number: H05K1/0306 ,  B32B3/30 ,  H05K1/09 ,  H05K3/00 ,  H05K3/0052 ,  H05K3/0097 ,  H05K2201/09036 ,  H05K2201/0909 ,  H05K2201/09154 ,  H05K2201/09863 ,  Y10T156/10 ,  Y10T428/15

Abstract: 分割時や該分割前において分割溝付近からの破損や欠けや割れが生じにくく、高い信頼性を有する多数個取り配線基板、およびその製造方法を提供する。複数のセラミック層s1,s2を積層してなり、表面2および裏面3を有し、平面視で長方形(矩形)を呈し且つキャビティ5を有する複数の配線基板部分4を縦横に配列した製品領域4aと、該製品領域4aの周囲に沿って位置する耳部6と、配線基板部分4,4間の境界および配線基板部分4と耳部6との境界に沿って表面2および裏面3の少なくとも一方に形成した分割溝8,9と、を備える多数個取り配線基板1であって、分割溝8,9は、長手方向と直交する断面において、該分割溝8,9の最深部8bが円弧形で、且つ該最深部8bと溝入口8cとの間に中間部8aを有し、最深部8bの幅w2は、溝入口8cの幅w3よりも大きく、中間部8aの幅w1は、溝入口8cの幅w3と同じかこれよりも小さい、多数個取り配線基板1。