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    Printed circuit boards for mounting a semiconductor integrated circuit die
    142.
    发明授权
    Printed circuit boards for mounting a semiconductor integrated circuit die 失效
    用于安装半导体集成电路管芯的印刷电路板

    公开(公告)号：US5965944A

    公开(公告)日：1999-10-12

    申请号：US968989

    申请日：1997-11-12

    Applicant: Edward Jay Frankoski ,  Irving Memis

    Inventor： Edward Jay Frankoski ,  Irving Memis

    IPC: H01L23/498 ,  H05K1/11 ,  H05K3/34 ,  H05K7/10 ,  H01L21/58

    CPC classification number: H01L23/49816 ,  H01L23/49811 ,  H05K1/111 ,  H05K3/3452 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K2201/09736 ,  H05K2201/09909 ,  H05K2201/10674 ,  Y02P70/611

    Abstract: The present invention provides printed circuit boards for mounting to a semiconductor integrated circuit die. In one embodiment the printed circuit boards comprise a rigid dielectric substrate having a planar face, a plurality of circuit lines affixed to the face of the substrate, and a plurality of conductive bumps affixed to the face of the substrate. Each conductive bump has an upper bonding surface that is substantially planar and a lateral surface which is essentially perpendicular to the face of the substrate. The conductive bumps and the circuit lines are formed from a single metallic layer. The conductive bumps and circuit lines constitute a unitary, integral structure, i.e., each conductive bump and connecting circuit line lack a physical interface therebetween. The upper surfaces of the conductive bumps extend to essentially the same height above the surface of the substrate, i.e., the upper surfaces of the conductive bumps are substantially coplanar relative to each other. In another embodiment, the printed circuit board further comprises a unitary solder dam or a plurality of unconnected solder dams that partially or completely surround the conductive bumps. The solder dam has an upper surface which lies below the upper bonding surface of the conductive bump. The solder dam is positioned to prevent the alloy, particularly solder, which is subsequently disposed on each conductive bump from flowing along the circuit lines that are integrally connected to the conductive bump. The present invention also relates to a microelectronic package that comprises a semiconductor integrated circuit die mounted to a printed circuit board made in accordance with the present invention.

    Abstract translation: 本发明提供了用于安装到半导体集成电路管芯的印刷电路板。 在一个实施例中，印刷电路板包括具有平面的刚性电介质基板，固定在基板表面上的多条电路线以及固定在基板表面上的多个导电凸块。 每个导电凸块具有基本平坦的上粘合表面和基本上垂直于基底的表面的侧表面。 导电凸块和电路线由单个金属层形成。 导电凸块和电路线构成一体的整体结构，即每个导电凸块和连接电路线之间缺少物理接口。 导电凸块的上表面延伸到基板表面上基本上相同的高度，即导电凸块的上表面相对于彼此基本上共面。 在另一个实施例中，印刷电路板还包括部分或完全围绕导电凸块的整体焊接坝或多个未连接的焊接坝。 焊料坝具有位于导电凸块的上粘接表面下方的上表面。 焊料坝被定位成防止随后设置在每个导电凸块上的合金，特别是焊料沿着与导电凸块一体连接的电路线流动。 本发明还涉及一种微电子封装，其包括安装到根据本发明制造的印刷电路板的半导体集成电路管芯。

    Method for controlling solderability of a conductor and conductor formed thereby
    143.
    发明授权
    Method for controlling solderability of a conductor and conductor formed thereby 失效
    用于控制由此形成的导体和导体的可焊性的方法

    公开(公告)号：US5962151A

    公开(公告)日：1999-10-05

    申请号：US985436

    申请日：1997-12-05

    Applicant: Christine Ann Paszkiet ,  Carl William Berlin ,  Stephanie Yolanda Oden

    Inventor： Christine Ann Paszkiet ,  Carl William Berlin ,  Stephanie Yolanda Oden

    IPC: H01L23/498 ,  H05K1/09 ,  H05K3/34 ,  B32B3/10 ,  B23K31/02

    CPC classification number: H01L23/49816 ,  H05K3/3452 ,  H01L2924/0002 ,  H05K1/092 ,  H05K1/095 ,  H05K2201/09909 ,  H05K3/3457 ,  Y10T428/12396 ,  Y10T428/12486 ,  Y10T428/12611

    Abstract: A conductor (112), a method for forming the conductor (112), and a method for attaching a discrete circuit device, such as a bond pad, chip capacitor, chip resistor, etc., to the conductor (112) with solder connections (16). Solder connections (16) formed by the method are characterized as being accurately located on the conductor (112) and having a shape and location that achieves an adequate and uniform stand-off height for the device, and improves thermal cycle fatigue life. Such benefits are achieved by forming a nonsolderable layer (114) on a substrate (10), and then forming a solderable conductor (112) on the substrate (10) such that a first portion of the conductor (112) overlies the nonsolderable layer (114) and a second portion of the conductor (112) does not overlie the nonsolderable layer (114). In so doing, the first and second portions of the conductor (114) define a boundary therebetween beyond which solder deposited on the second portion of the conductor (112) is inhibited from flowing onto the first portion of the conductor (112).

    Abstract translation: 一种导体（112），一种用于形成导体（112）的方法，以及一种用于将诸如接合焊盘，片状电容器，片状电阻器等的分立电路器件连接到导体（112）上的焊接连接 （16）。 通过该方法形成的焊接连接（16）的特征在于准确地位于导体（112）上并且具有能够实现装置的足够均匀的间隔高度的形状和位置，并且提高热循环疲劳寿命。 通过在衬底（10）上形成不可焊层（114），然后在衬底（10）上形成可焊接导体（112）使得导体（112）的第一部分覆盖在不可焊层 114），并且导体（112）的第二部分不覆盖不可焊层（114）。 在这样做的过程中，导体（114）的第一和第二部分限定了它们之间的边界，在该边界之间限制了沉积在导体（112）的第二部分上的焊料流入导体（112）的第一部分。

    Electronic device and semiconductor package
    145.
    发明授权
    Electronic device and semiconductor package 失效
    电子设备和半导体封装

    公开(公告)号：US5834848A

    公开(公告)日：1998-11-10

    申请号：US982417

    申请日：1997-12-02

    Applicant: Ken Iwasaki

    Inventor： Ken Iwasaki

    IPC: H01L23/32 ,  H01L21/56 ,  H05K3/30 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H05K3/303 ,  H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K2201/068 ,  H05K2201/09909 ,  H05K2201/10734 ,  H05K3/3436 ,  Y02P70/613

    Abstract: The electronic device has a structure that a semiconductor package (10) is mounted on a motherboard (21), and a buffer layer (41) for relieving a stress, which is produced due to a difference of physical properties between the semiconductor package (10) and the motherboard (21), is mounted on the electrical and mechanical interface between the semiconductor package (10) and the motherboard (21). For example, the buffer layer (41) having a thermal expansion coefficient close to that of the motherboard (21) is formed on a face of the semiconductor package 10 having an external connecting terminals (12b) mounted. A stress caused due to a difference between a thermal expansion coefficient of a wiring substrate (12) of the semiconductor package and that of the motherboard (21) can be relieved by the buffer layer (41). Therefore, a cyclic stress applied to the connection between the semiconductor package and the motherboard in the actual application environment can be relieved, and reliability of connection can be improved. Thus, a semiconductor package mountable with a high degree of reliability and an electronic device having a high degree of reliability is provided.

    Abstract translation: 电子设备具有将半导体封装（10）安装在母板（21）上的结构，以及用于缓解由于半导体封装（10）之间的物理差异而产生的应力的缓冲层（41） ）和母板（21）安装在半导体封装（10）和母板（21）之间的电气和机械接口上。 例如，具有接近主板（21）的热膨胀系数的缓冲层（41）形成在具有安装有外部连接端子（12b）的半导体封装10的表面上。 由于半导体封装的布线基板（12）的热膨胀系数与母板（21）的热膨胀系数之差导致的应力可被缓冲层（41）释放。 因此，可以减轻在实际应用环境中施加到半导体封装和母板之间的连接的循环应力，并且可以提高连接的可靠性。 因此，提供了可靠地安装的半导体封装件和具有高可靠性的电子器件。

    Mounting structure for electronic component
    148.
    发明授权
    Mounting structure for electronic component 失效
    电子元器件的安装结构

    公开(公告)号：US5532658A

    公开(公告)日：1996-07-02

    申请号：US362805

    申请日：1994-12-22

    Applicant: Ken Tonegawa ,  Harufumi Mandai ,  Teruhisa Tsuru ,  Mitsuhide Katou ,  Koji Furutani

    Inventor： Ken Tonegawa ,  Harufumi Mandai ,  Teruhisa Tsuru ,  Mitsuhide Katou ,  Koji Furutani

    IPC: H05K1/02 ,  H05K1/18 ,  H05K3/28 ,  H05K3/30 ,  H05K3/34 ,  H01P5/00 ,  H01L23/48

    CPC classification number: H05K1/0243 ,  H05K1/0239 ,  H05K1/18 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/0715 ,  H05K2201/09336 ,  H05K2201/09581 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09909 ,  H05K2201/1006 ,  H05K2201/10636 ,  H05K2201/10969 ,  H05K3/28 ,  H05K3/305 ,  H05K3/3436 ,  Y02P70/611

    Abstract: An electronic component which is employed in the frequency range in the microwave band or above is mounted on a circuit board. The circuit board comprises two linear transmission line members, a ground electrode, and an electric insulating substrate provided with the transmission line members and the ground electrode on its major surface. The electronic component comprises external electrodes which are formed on its side surfaces. Holding patches which are formed on the lower surface of the electronic component are bonded to the ground electrode by solder members, thereby fixing the electronic component to the circuit board. At this time, small clearances are defined between the electronic component and the circuit board through the solder members, whereby the external electrodes are electromagnetically coupled with the transmission line members and the ground electrode through the clearances respectively. Thus, it is possible to obtain a mounting structure for an electronic component, which can suppress development of unnecessary inductance components.

    Abstract translation: 在微波波段以上的频率范围内使用的电子部件安装在电路基板上。 电路板包括两个线性传输线构件，接地电极和在其主表面上设置有传输线构件和接地电极的电绝缘基板。 电子部件包括形成在其侧表面上的外部电极。 形成在电子部件的下表面上的保持贴片通过焊料接合到接地电极，从而将电子部件固定到电路板。 此时，通过焊料部件在电子部件和电路基板之间形成小的间隙，由此外部电极分别通过间隙与传输线部件和接地电极电磁耦合。 因此，可以获得能够抑制不必要的电感成分的发展的电子部件的安装结构。

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