公开(公告)号：US09664569B2

公开(公告)日：2017-05-30

申请号：US14714005

申请日：2015-05-15

Applicant: Google Inc.

Inventor： Adam Mittleman ,  Ian Charles Smith ,  Daniel Adam Warren ,  William Raeming Dong ,  Jeff Wheeler

IPC: G01N21/00 ,  G01J5/06 ,  H05K1/02 ,  G01J5/00 ,  G01J5/10 ,  G01J5/02 ,  G01J5/04 ,  G08B13/189

CPC classification number: G01J5/06 ,  G01J5/0014 ,  G01J5/0205 ,  G01J5/04 ,  G01J5/10 ,  G08B13/189 ,  G08B13/191 ,  H05K1/0201 ,  H05K1/0298 ,  H05K2201/09063 ,  H05K2201/093 ,  H05K2201/09363 ,  H05K2201/0969 ,  H05K2201/10106 ,  H05K2201/10151 ,  H05K2201/10522 ,  H05K2201/10575 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A multilayered circuit board having a metal-free region vertically extending through at least a portion of a conductive layer, which lies generally parallel to a horizontal plane, vertically spaced from an outer surface. Heat-emitting and heat-sensitive components are mounted on the outer surface. The heat-emitting component is vertically and laterally spaced from the metal-free region, whereas the heat-sensitive component is vertically spaced and laterally aligned within the metal-free region such that the metal-free region is a thermal barrier that shields heat-sensitive component from radial heat flowing from the heat-emitting component.

公开(公告)号：US09652103B2

公开(公告)日：2017-05-16

申请号：US14947563

申请日：2015-11-20

Applicant: Japan Display Inc.

Inventor： Hayato Kurasawa ,  Keisuke Asada ,  Tatsuya Ide ,  Koji Ishizaki

IPC: G06F3/045 ,  G06F3/044 ,  G02F1/1333 ,  G06F3/041 ,  H05K1/11 ,  H05K3/28 ,  H05K3/36

CPC classification number: G06F3/044 ,  G02F1/13338 ,  G06F3/0412 ,  G06F2203/04108 ,  G06F2203/04112 ,  H05K1/028 ,  H05K1/117 ,  H05K1/147 ,  H05K3/28 ,  H05K3/361 ,  H05K2201/09263 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/10128

Abstract: [Problem] To prevent detachment of overcoat layer which covers at least a part of a terminal formed on a substrate.[Measure to solve the problem] According to one embodiment, a detection device includes a substrate, detection electrode, terminal formed of a metal material, lead, coating layer, conductive adhesion layer, and circuit board. The lead connects the electrode and the terminal. The coating layer covers the electrode and the lead, and partly covers the terminal. The adhesion layer covers a part of the terminal exposed from the coating layer and covers a part of the coating layer. The circuit board is connected to the terminal with the adhesion layer interposed therebetween. At least in an overlapping area where the conductive adhesion layer covers the coating layer, the metal material that forms the terminal includes a shape that the metal material is partly removed.

公开(公告)号：US09648733B2

公开(公告)日：2017-05-09

申请号：US13861338

申请日：2013-04-11

Applicant: Yonggang Li ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

Inventor： Yonggang Li ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/18 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/426 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/0969 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.

公开(公告)号：US09596764B2

公开(公告)日：2017-03-14

申请号：US14577333

申请日：2014-12-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Naoki Gouchi

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/46 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/0287 ,  H05K1/0292 ,  H05K1/0293 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/0393 ,  H05K1/111 ,  H05K1/183 ,  H05K1/185 ,  H05K1/186 ,  H05K3/24 ,  H05K3/4007 ,  H05K3/4092 ,  H05K3/4632 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10007 ,  H05K2201/10159 ,  H05K2201/10984 ,  H05K2201/2072 ,  H05K2203/0271 ,  H05K2203/063 ,  H05K2203/08

Abstract: To prevent decrease of the bonding strength of an electronic component and a multilayer substrate, an electronic component-embedded module may include an electronic component having a plurality of pads and a multilayer substrate which includes a plurality of resin layers and a cavity for containing the electronic component. The multilayer substrate may include a first resin layer having a plurality of first pattern conductors and a space, and a second resin layer having a second pattern conductor and a plurality of third pattern conductors. The plurality of third pattern conductors may be in conduction with either of the first pattern conductors or the pads, with the second resin layer being placed over the first resin layer. The second pattern conductor may be arranged around a first pad with a gap, and the second resin layer is present between the second pattern conductor and at least one of the first pads.

Abstract translation: 为了防止电子部件和多层基板的接合强度的降低，电子部件嵌入式模块可以包括具有多个焊盘的电子部件和包括多个树脂层的多层基板和用于容纳电子部件的空腔 零件。 多层基板可以包括具有多个第一图案导体和空间的第一树脂层和具有第二图案导体和多个第三图案导体的第二树脂层。 多个第三图案导体可以与第一图案导体或垫中的任一个导通，其中第二树脂层被放置在第一树脂层上。 第二图案导体可以布置在具有间隙的第一衬垫周围，并且第二树脂层存在于第二图案导体和至少一个第一衬垫之间。

公开(公告)号：US09591767B2

公开(公告)日：2017-03-07

申请号：US14290173

申请日：2014-05-29

Applicant: FUJIKURA LTD.

Inventor： Kazuhisa Itoi ,  Masahiro Okamoto

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/10 ,  H01L23/538 ,  H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K3/10 ,  H01L21/4857 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/08237 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11416 ,  H01L2224/11418 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/1329 ,  H01L2224/13294 ,  H01L2224/13309 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13316 ,  H01L2224/13324 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/1336 ,  H01L2224/1339 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/2929 ,  H01L2224/32225 ,  H01L2224/73201 ,  H01L2224/73251 ,  H01L2224/73253 ,  H01L2224/80203 ,  H01L2224/80447 ,  H01L2224/80903 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/8185 ,  H01L2224/81862 ,  H01L2224/81907 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8349 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/9221 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15153 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/186 ,  H05K3/0061 ,  H05K3/4602 ,  H05K3/4614 ,  H05K2201/0969 ,  H05K2201/10674 ,  Y10T29/49126 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/0635 ,  H01L2924/069 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/16 ,  H01L2224/08 ,  H01L2224/32 ,  H01L2924/00

Abstract: A component built-in board comprises stacked therein a plurality of printed wiring bases having a wiring pattern and a via formed on/in a resin base thereof, and comprises an electronic component built in thereto, wherein at least a portion of the plurality of printed wiring bases include a thermal wiring in the wiring pattern and include a thermal via in the via, at least one of the plurality of printed wiring bases has formed therein an opening where the electronic component is built, and has formed therein a heat-conducting layer and closely attached to a surface on an opposite side to an electrode formation surface of the electronic component built in to the opening, and the electronic component is fixed in the opening by an adhesive layer stacked on the heat-conducting layer, via a hole formed in a region facing onto the opening of the heat-conducting layer.

Abstract translation: 一种组件内置板，其中堆叠有多个印刷布线基底，其具有形成在其树脂基底上的布线图案和通孔，并且包括内置于其中的电子部件，其中多个印刷的至少一部分 布线基底包括布线图案中的热布线，并且在通孔中包括热通孔，多个印刷布线基底中的至少一个在其中形成有电子部件构建的开口，并且在其中形成有导热层 并且紧贴在与内置于开口部的电子部件的电极形成面相反一侧的面上，电子部件通过形成有孔的层叠在导热层上的粘接层固定在开口部 在面向导热层的开口的区域中。

公开(公告)号：US09572254B2

公开(公告)日：2017-02-14

申请号：US13352215

申请日：2012-01-17

Applicant: Chad David Freitag ,  Tygh James Newton ,  Chad Johan Slenes

Inventor： Chad David Freitag ,  Tygh James Newton ,  Chad Johan Slenes

IPC: H05K1/00 ,  H05K1/11 ,  H05K3/36 ,  H05K3/32

CPC classification number: H05K3/4007 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/11 ,  H05K1/111 ,  H05K1/112 ,  H05K3/321 ,  H05K3/361 ,  H05K3/363 ,  H05K2201/0394 ,  H05K2201/09681 ,  H05K2201/0969

Abstract: An electrical interconnect has a circuit substrate and an electrical connection point on the circuit substrate. The electrical connection point includes a lattice of conductive material that is adjacent a gap in the circuit substrate and has anchor points that are attached to the circuit substrate. In some configurations, a conductive epoxy encapsulates at least a portion of the lattice of conductive material and may include a second electrical connection point that is bonded to the other electrical connection point through the conductive epoxy.

Abstract translation: 电互连具有电路基板和电路基板上的电连接点。 电连接点包括与电路基板中的间隙相邻并且具有附接到电路基板的锚定点的导电材料的格子。 在一些配置中，导电环氧树脂封装导电材料的晶格的至少一部分，并且可以包括通过导电环氧树脂结合到另一电连接点的第二电连接点。

公开(公告)号：US09478879B2

公开(公告)日：2016-10-25

申请号：US13935292

申请日：2013-07-03

Applicant: PANASONIC CORPORATION

Inventor： Hiroshi Iwano ,  Mitsuru Iida ,  Daisuke Sato ,  Hidetoshi Takeyama

IPC: H01R12/79 ,  H05K1/11 ,  H01R12/61 ,  H05K3/00 ,  H05K3/36 ,  H05K3/40

CPC classification number: H01R12/613 ,  H01R12/79 ,  H05K1/11 ,  H05K1/114 ,  H05K1/117 ,  H05K3/0038 ,  H05K3/365 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09409 ,  H05K2201/09427 ,  H05K2201/09445 ,  H05K2201/0949 ,  H05K2201/09509 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10189 ,  H05K2201/2009 ,  H05K2201/2072 ,  H05K2203/167

Abstract: A socket (female connector) used for a connector assembly includes a film substrate constituted by a flexible thin board made of insulation material. The film substrate is provided with connection through holes adapted to be inserted therein connection posts of a header (male connector). Connection pads are formed on a first surface of the film substrate around respective connection through holes. The connection pads include a first pad and a second pad. The film substrate is provided on the first surface with a first patterned conductor connected to the first pad and a third patterned conductor connected to the second pad. The third patterned conductor is connected to a second patterned conductor formed on a second surface of the film substrate by means of a blind via that is formed by boring the film substrate from the second surface so as to reach the third patterned conductor.

Abstract translation: 用于连接器组件的插座（母连接器）包括由绝缘材料制成的柔性薄板构成的薄膜基片。 薄膜基片设置有适于插入插头（公连接器）的连接柱中的连接通孔。 连接衬垫围绕各个连接通孔形成在薄膜基片的第一表面上。 连接焊盘包括第一焊盘和第二焊盘。 薄膜基板在第一表面上设置有连接到第一焊盘的第一图案化导体和连接到第二焊盘的第三图案化导体。 第三图案化导体通过盲孔通过第二图案导体连接到形成在膜基板的第二表面上的第二图案化导体，所述盲孔通过从第二表面镗孔而形成，以到达第三图案化导体。

公开(公告)号：US09468089B2

公开(公告)日：2016-10-11

申请号：US14460694

申请日：2014-08-15

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tadahiro Sasaki ,  Hiroshi Yamada

IPC: H04B3/28 ,  H05K1/02 ,  H01L23/00 ,  H01L23/498

CPC classification number: H05K1/0236 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2924/1531 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0225 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0242 ,  H05K1/0243 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09254 ,  H05K2201/0969 ,  H05K2201/09727

Abstract: An EBG structure of an embodiment includes an electrode plane, a first insulating layer provided on the electrode plane, a first metal patch provided on the first insulating layer, a second metal patch provided on the first insulating layer, a second insulating layer provided on the first and second metal patches, an interconnect layer provided on the second insulating layer, a third insulating layer provided on the interconnect layer, a first via connected to the electrode plane and the first metal patch, and a second via connected to the electrode plane and the second metal patch. The second metal patch is separately adjacent to the first metal patch. The interconnect layer has a first opening and a second opening. The first via penetrates through the first opening. The second via penetrates through the second opening.

Abstract translation: 实施例的EBG结构包括电极平面，设置在电极平面上的第一绝缘层，设置在第一绝缘层上的第一金属贴片，设置在第一绝缘层上的第二金属贴片，设置在第一绝缘层上的第二绝缘层 第一和第二金属贴片，设置在第二绝缘层上的互连层，设置在互连层上的第三绝缘层，连接到电极平面和第一金属贴片的第一通孔，以及连接到电极平面的第二通孔和 第二个金属贴片。 第二金属贴片与第一金属贴片分开相邻。 互连层具有第一开口和第二开口。 第一个通孔穿过第一个开口。 第二通孔穿过第二开口。

公开(公告)号：US09466891B2

公开(公告)日：2016-10-11

申请号：US14505621

申请日：2014-10-03

Applicant: TELLABS OY

Inventor： Antti Holma ,  Juha Sarapelto

IPC: H01R4/02 ,  H05K1/18 ,  H05K1/11 ,  H05K1/02

CPC classification number: H01R4/021 ,  H05K1/0201 ,  H05K1/115 ,  H05K1/116 ,  H05K1/181 ,  H05K2201/062 ,  H05K2201/0969 ,  H05K2201/09718

Abstract: A circuit board comprises one or more first electrical conductors (102-107) in a first portion of the thickness of the circuit board, one or more second electrical conductors (108, 109) in a second portion of the circuit board, at least one via-conductor (112) providing a galvanic current path between the first and second electrical conductors, a hole extending through the first and second portions of the circuit board, and an electrically conductive sleeve (114) lining the hole and having galvanic contacts with the second electrical conductors. The thermal resistance from the electrically conductive sleeve to the first electrical conductors is greater than the thermal resistance from the electrically conductive sleeve to the second electrical conductors so as to obtain a reliable solder joint between a part of the electrically conductive sleeve belonging to the first portion of the circuit board and an electrical conductor pin (119) located in the hole.

Abstract translation: 电路板包括在电路板的厚度的第一部分中的一个或多个第一电导体（102-107），在电路板的第二部分中的一个或多个第二电导体（108,109），至少一个 通孔导体（112）在第一和第二电导体之间提供电流通路，延伸穿过电路板的第一和第二部分的孔以及衬套孔的导电套筒（114），并且具有与 第二电导体。 从导电套管到第一电导体的热阻大于从导电套筒到第二电导体的热阻，以便在属于第一部分的导电套筒的一部分之间获得可靠的焊接接头 和位于孔中的电导体销（119）。

公开(公告)号：US20160270222A1

公开(公告)日：2016-09-15

申请号：US15160203

申请日：2016-05-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshihito Otsubo ,  Takayuki Tsukizawa

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0298 ,  H05K1/115 ,  H05K3/4682 ,  H05K2201/09227 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/09781

Abstract: A multilayer wiring board includes: a multilayer body including a plurality of insulating layers; a lower outer electrode provided on a lower surface of the multilayer body; a first via conductor connected at one end to the lower outer electrode; a first in-plane conductor connected to another end of the first via conductor; a second via conductor provided within the multilayer body on a surface of the first in-plane conductor on the opposite side from a surface of the first in-plane conductor in a position distanced from the first via conductor viewed in a direction orthogonal to a layering direction of the multilayer body, one end of the second via conductor being connected to the first in-plane conductor; and a second in-plane conductor connected to another end of the second via conductor. A line width of the first in-plane conductor is narrower than that of the second in-plane conductor.

Abstract translation: 多层布线基板包括：多层绝缘层，包括多个绝缘层; 设置在所述多层体的下表面上的下外电极; 第一通孔导体，其一端连接到下部外部电极; 连接到第一通孔导体的另一端的第一面内导体; 第二通孔导体，其设置在所述第一面内导体的表面上，所述第二通孔导体在所述第一面内导体的与所述第一面内导体的表面相反的一侧的表面上，在远离所述第一通孔导体的位置， 所述多层体的方向，所述第二通路导体的一端与所述第一面内导体连接; 以及连接到第二通孔导体的另一端的第二面内导体。 第一面内导体的线宽比第二面内导体窄。