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公开(公告)号：US20160150633A1
公开(公告)日：2016-05-26
申请号：US14947091
申请日：2015-11-20
Applicant: Amphenol Corporation
Inventor： Marc B. Cartier, JR.
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns comprising: dual diameter first and second signal vias forming a differential signal pair, the first and second signal vias being configured to accept contact tails of signal conductors of a connector; dual diameter ground shadow vias adjacent to each of the first and second signal vias, wherein the dual diameter shadow ground vias have a reversed diameter configuration with respect to the dual diameter first and second signal vias; and ground vias configured to accept contact tails of ground conductors of the connector.
Abstract translation: 印刷电路板包括多个层，包括附着层和布线层; 以及形成在所述多个层中的通孔图案，所述通孔图案中的每一个包括：形成差分信号对的双直径第一和第二信号通孔，所述第一和第二信号通孔被配置为接纳连接器的信号导体的接触尾部; 与第一和第二信号通孔中的每一个相邻的双直径地面阴影通孔，其中双直径阴影接地通孔相对于双直径第一和第二信号通孔具有反向直径构型; 以及配置为接受连接器的接地导体的接触尾部的接地通孔。
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62.发明授权High speed circuit assembly with integral terminal and mating bias loading electrical connector assembly 有权具有集成端子和配合偏置负载电连接器组件的高速电路组件公开(公告)号：US09350124B2
公开(公告)日：2016-05-24
申请号：US14408039
申请日：2013-03-13
Applicant: HSIO TECHNOLOGIES, LLC
Inventor： James Rathburn
IPC: H01R12/68 , H01R12/50 , H01R13/24 , H01R12/82 , H05K3/36 , H05K3/40 , H01R12/73 , H01L23/00 , H05K1/09 , H05K1/11 , H05K1/18 , H05K3/00 , H05K3/42 , H05K3/46
CPC classification number: H01R23/6813 , H01L24/16 , H01L24/48 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01R12/73 , H01R12/82 , H01R13/2457 , H01R13/2485 , H01R31/06 , H05K1/092 , H05K1/111 , H05K1/141 , H05K1/182 , H05K3/0094 , H05K3/10 , H05K3/1291 , H05K3/326 , H05K3/363 , H05K3/365 , H05K3/4007 , H05K3/4015 , H05K3/4092 , H05K3/425 , H05K3/4694 , H05K7/1076 , H05K2201/0397 , H05K2201/048 , H05K2201/09381 , H05K2201/09545 , H05K2201/09563 , H05K2201/09854 , H05K2201/10378 , H05K2201/10386 , H05K2201/2072 , H05K2201/209 , H05K2203/041 , H05K2203/1476 , Y10T29/49165 , H01L2224/45099 , H01L2924/00
Abstract: A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.
Abstract translation: 一种在电路组件上制成集成端子阵列的方法。 该方法包括以下步骤：在第一电路构件的第一表面上沉积至少第一液体电介质层，成像为包括与集成端子阵列相对应的多个第一凹部。 处理第一凹槽的选定表面以接受无电导电电镀沉积。 对所述第一凹槽的所选择的表面施加无电镀以产生电耦合到所述第一电路层并且大致垂直于所述第一电路层延伸的多个第一导电结构。 使用导电材料将电镀施加到基本上第一凹部的无电镀。 重复沉积，加工，无电镀和电镀的步骤以形成所需形状的整体端子。 去除电介质层以露出端子。
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公开(公告)号：US20160088731A1
公开(公告)日：2016-03-24
申请号：US14858759
申请日：2015-09-18
Applicant: FINISAR CORPORATION
Inventor： Henry Meyer Daghighian
CPC classification number: H05K1/115 , H05K1/0231 , H05K1/0243 , H05K1/0298 , H05K1/092 , H05K1/113 , H05K1/162 , H05K1/182 , H05K2201/0187 , H05K2201/0257 , H05K2201/09545 , H05K2201/09809 , H05K2201/10734
Abstract: A capacitor in a multilayer printed circuit board is described. The capacitor may include a via of a via-in-pad type and a dielectric mixture filled in the via of the via-in-pad type. The via may be disposed under an integrated circuit contact pad of the multilayer printed circuit board. The dielectric mixture may include a nanoparticle-sized dielectric powder mixed with an adhesive material.
Abstract translation: 描述了多层印刷电路板中的电容器。 电容器可以包括衬垫型通孔和填充在通孔式通孔型的通孔中的电介质混合物。 通孔可以设置在多层印刷电路板的集成电路接触焊盘的下方。 介电混合物可以包括与粘合剂材料混合的纳米颗粒尺寸的介电粉末。
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公开(公告)号：US20160078998A1
公开(公告)日：2016-03-17
申请号：US14856542
申请日：2015-09-16
Applicant: INNOCHIPS TECHNOLOGY CO., LTD.
Inventor： In Kil PARK , Tae Hyung NOH , Jun Ho JUNG , Gyeong Tae KIM , Seung Hun CHO , Young Tak KIM , Jong Pil PARK
CPC classification number: H05K3/0094 , H01F17/0013 , H01F41/041 , H01F2027/2809 , H01L23/5227 , H01L2924/0002 , H05K1/0298 , H05K1/115 , H05K2201/09545 , H05K2201/09781 , H01L2924/00
Abstract: Provided is a circuit protection device and a method of manufacturing the same including forming a plating lead line and a first coil pattern connected to the plating lead line on a substrate, forming an insulating layer on the first coil pattern and then forming a via hole exposing a portion of the first coil pattern, applying power through a plating lead line to form a via plug filling the via hole from the first coil pattern, and forming a second coil pattern connected to the via plug at an upper portion of the insulating layer.
Abstract translation: 提供了一种电路保护装置及其制造方法，包括在基板上形成连接到电镀引线的电镀引线和第一线圈图案，在第一线圈图案上形成绝缘层，然后形成通孔露出 第一线圈图案的一部分，通过电镀引线施加电力，以形成从第一线圈图案填充通孔的通孔，并且在绝缘层的上部形成连接到通孔塞的第二线圈图案。
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公开(公告)号：US20150373848A1
公开(公告)日：2015-12-24
申请号：US14625983
申请日：2015-02-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-hyun SEOK
IPC: H05K1/11 , H05K1/18 , G11C11/401 , H01C13/02
CPC classification number: H01C13/02 , G11C5/04 , G11C7/10 , G11C11/401 , H05K1/117 , H05K3/3415 , H05K2201/0385 , H05K2201/09545 , H05K2201/10159
Abstract: A semiconductor module includes a printed circuit board including an integrated circuit chip, connecting terminals at an edge of the printed circuit board, and signal lines respectively connecting electrical connection pads of the integrated circuit chip to the connecting terminals. The connecting terminals are plated using via-holes of the printed circuit board respectively connected to the signal lines.
Abstract translation: 半导体模块包括印刷电路板，其包括集成电路芯片，印刷电路板的边缘处的连接端子以及分别将集成电路芯片的电连接焊盘连接到连接端子的信号线。 使用分别连接到信号线的印刷电路板的通孔来对连接端子进行电镀。
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Patent Agency Ranking
公开(公告)号：US09107314B2
公开(公告)日：2015-08-11
申请号：US13799221
申请日：2013-03-13
Applicant: FUJITSU LIMITED
Inventor： Hideaki Yoshimura
CPC classification number: H05K1/115 , G01R31/2889 , H05K1/0298 , H05K1/0366 , H05K3/4038 , H05K3/425 , H05K3/445 , H05K3/4608 , H05K2201/0323 , H05K2201/09545 , H05K2201/09554 , H05K2201/0959 , Y10T29/49165
Abstract: A method of manufacturing a wiring board includes: forming an outer through hole in a core substrate; filling the outer through hole with an insulation resin; forming a first conductive layer on a surface of the insulation resin at a portion where a core connecting via is formed; forming a land around the first conductive layer; laminating the wiring layer on the core substrate after the forming of the first conductive layer and the forming of the land; forming an inner through hole having a smaller diameter than that of the outer through hole and penetrating through the core substrate and the wiring layer so as to penetrate through the insulation resin; and coating a first conductive film on an inner wall surface of the inner through hole, in which the core substrate and the first conductive film are electrically connected through the first conductive layer and the land.
Abstract translation: 制造布线板的方法包括：在芯基板中形成外通孔; 用绝缘树脂填充外部通孔; 在形成芯连接通孔的部分上在绝缘树脂的表面上形成第一导电层; 形成围绕所述第一导电层的区域; 在形成第一导电层并形成焊盘之后，在芯基板上层叠布线层; 形成直径小于所述外通孔直径的内通孔，穿过所述芯基板和所述布线层以贯穿所述绝缘树脂; 并且在内部通孔的内壁表面上涂覆第一导电膜，其中芯基板和第一导电膜通过第一导电层和焊盘电连接。
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67.发明申请HIGH SPEED CIRCUIT ASSEMBLY WITH INTEGRAL TERMINAL AND MATING BIAS LOADING ELECTRICAL CONNECTOR ASSEMBLY 有权具有整体端子和负极偏置电气连接器总成的高速电路组件公开(公告)号：US20150136467A1
公开(公告)日：2015-05-21
申请号：US14408039
申请日：2013-03-13
Applicant: HSIO TECHNOLOGIES, LLC
Inventor： James Rathburn
CPC classification number: H01R23/6813 , H01L24/16 , H01L24/48 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01R12/73 , H01R12/82 , H01R13/2457 , H01R13/2485 , H01R31/06 , H05K1/092 , H05K1/111 , H05K1/141 , H05K1/182 , H05K3/0094 , H05K3/10 , H05K3/1291 , H05K3/326 , H05K3/363 , H05K3/365 , H05K3/4007 , H05K3/4015 , H05K3/4092 , H05K3/425 , H05K3/4694 , H05K7/1076 , H05K2201/0397 , H05K2201/048 , H05K2201/09381 , H05K2201/09545 , H05K2201/09563 , H05K2201/09854 , H05K2201/10378 , H05K2201/10386 , H05K2201/2072 , H05K2201/209 , H05K2203/041 , H05K2203/1476 , Y10T29/49165 , H01L2224/45099 , H01L2924/00
Abstract: A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.
Abstract translation: 一种在电路组件上制成集成端子阵列的方法。 该方法包括以下步骤：在第一电路构件的第一表面上沉积至少第一液体电介质层，成像为包括与集成端子阵列相对应的多个第一凹部。 处理第一凹槽的选定表面以接受无电导电电镀沉积。 对所述第一凹槽的所选择的表面施加无电镀以产生电耦合到所述第一电路层并且大致垂直于所述第一电路层延伸的多个第一导电结构。 使用导电材料将电镀施加到基本上第一凹部的无电镀。 重复沉积，加工，无电镀和电镀的步骤以形成所需形状的整体端子。 去除电介质层以露出端子。
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公开(公告)号：US20150101852A1
公开(公告)日：2015-04-16
申请号：US14499184
申请日：2014-09-28
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Jong Tae PARK , Ho Shik Kang
CPC classification number: H05K1/115 , H05K3/0097 , H05K3/108 , H05K3/426 , H05K3/428 , H05K3/465 , H05K2201/0347 , H05K2201/09472 , H05K2201/09545 , H05K2201/09563 , H05K2203/1536 , Y10T29/49165
Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same.The printed circuit board according to a preferred embodiment of the present invention may include: an insulating layer; a first via depressed from one surface of the insulating layer; a second via depressed from the other surface of the insulating layer; and a circuit pattern formed in the insulating layer and bonded to the first and second vias.
Abstract translation: 这里公开了一种印刷电路板及其制造方法。 根据本发明的优选实施例的印刷电路板可以包括：绝缘层; 从所述绝缘层的一个表面凹陷的第一通孔; 从所述绝缘层的另一表面压下的第二通孔; 以及形成在绝缘层中并结合到第一和第二通孔的电路图案。
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公开(公告)号：US20150092381A1
公开(公告)日：2015-04-02
申请号：US14565383
申请日：2014-12-09
Applicant: Broadcom Corporation
Inventor： Tonglong ZHANG
CPC classification number: H05K1/115 , H05K1/09 , H05K1/181 , H05K3/423 , H05K3/427 , H05K2201/09545 , Y10T29/49165
Abstract: One disclosed embodiment comprises formation of a padless via in a substrate. The padless via includes a hole through a metal layer blanketing the substrate, as well as the underlying substrate. An inner wall of the padless via hole receives a seed layer of a conductive material. Electrolytic differential plating is then performed, resulting in a preferential accumulation of a conductive plating material on the via inner wall, relative to that deposited on a surface of the substrate. In one embodiment, the differential plating is performed by addition of an organic suppressant to a plating bath.
Abstract translation: 一个公开的实施例包括在衬底中形成无衬垫通孔。 无衬垫通孔包括通过覆盖衬底的金属层以及下面的衬底的孔。 无衬垫通孔的内壁容纳导电材料的籽晶层。 然后进行电解差动电镀，导致相对于沉积在基板的表面上的导电镀层材料在通孔内壁上的优先堆积。 在一个实施方案中，通过向电镀浴中加入有机抑制剂来进行差动电镀。
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70.发明申请METHOD TO MAKE A MULTILAYER CIRCUIT BOARD WITH INTERMETALLIC COMPOUND AND RELATED CIRCUIT BOARDS 有权制造具有互联化合物和相关电路板的多层电路板的方法公开(公告)号：US20150053468A1
公开(公告)日：2015-02-26
申请号：US14532224
申请日：2014-11-04
Applicant: HARRIS CORPORATION
Inventor： MICHAEL RAYMOND WEATHERSPOON , LOUIS JOSEPH RENDEK, JR. , LAWRENCE WAYNE SHACKLETTE , CASEY PHILIP RODRIGUEZ
CPC classification number: H05K1/0298 , H05K1/09 , H05K1/116 , H05K3/429 , H05K3/4614 , H05K2201/0141 , H05K2201/09545 , H05K2203/061 , Y10T29/49117 , Y10T29/49124 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
Abstract: A method for making a multilayer circuit board from circuit board layers, each including a dielectric layer and conductive traces thereon including a first metal. The method includes forming a through-via in a first circuit board layer, plating the through-via with the first metal, and coating a second metal onto the first metal of the first circuit board layer, the plated through-via, and the first metal. The method also includes aligning the first and second circuit board layers together so that the plated through-via of the first circuit board layer is adjacent a feature on the second circuit board layer, and heating and pressing the aligned first and second circuit board layers so as to laminate the dielectric layers together and form an intermetallic compound of the first and second metals bonding adjacent metal portions.
Abstract translation: 一种从电路板层制造多层电路板的方法，每个电路板包括电介质层和其上包括第一金属的导电迹线。 该方法包括在第一电路板层中形成通孔，将通孔与第一金属电镀，并将第二金属涂覆在第一电路板层的第一金属上，镀通孔和第一金属 金属。 该方法还包括将第一和第二电路板层对准在一起，使得第一电路板层的电镀通孔与第二电路板层上的特征相邻，并且加热并压紧对准的第一和第二电路板层 以将电介质层层合在一起并形成接合相邻金属部分的第一和第二金属的金属间化合物。
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