公开(公告)号：EP1974372A4

公开(公告)日：2009-12-09

申请号：EP07716303

申请日：2007-01-03

Applicant: IBM

Inventor： CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WANG YUN Y ,  KWONG HON WONG KEITH

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1825521A4

公开(公告)日：2008-10-01

申请号：EP05820881

申请日：2005-11-01

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor structure is provided that includes a V t stabilization layer between a gate dielectric and a gate electrode. The V t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the provision that when the V t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

公开(公告)号：EP2396812A4

公开(公告)日：2012-08-01

申请号：EP10767544

申请日：2010-04-15

Applicant: IBM

Inventor： CHANG JOSEPHINE B ,  CHANG LELAND ,  MO RENEE T ,  NARAYANAN VIJAY ,  SLEIGHT JEFFREY W

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7856 ,  H01L29/66795

公开(公告)号：EP1766691A4

公开(公告)日：2011-06-29

申请号：EP05732384

申请日：2005-03-30

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L31/113 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/119

CPC classification number: H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

公开(公告)号：EP2519976A4

公开(公告)日：2014-02-19

申请号：EP11735025

申请日：2011-01-14

Applicant: IBM

Inventor： ADUSUMILLI PRANEET ,  CALLEGARI ALESSANDRO ,  CHANG JOSEPHINE B ,  CHOI CHANGHWAN ,  FRANK MARTIN MICHAEL ,  GUILLOM MICHAEL ,  NARAYANAN VIJAY

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/513

公开(公告)号：EP1949447A4

公开(公告)日：2009-11-11

申请号：EP06825854

申请日：2006-10-12

Applicant: IBM

Inventor： CARTER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  LINDER BARRY P ,  NARAYANAN VIJAY

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

公开(公告)号：EP1872407A4

公开(公告)日：2011-09-14

申请号：EP06750529

申请日：2006-04-18

Applicant: IBM

Inventor： CARTIER EDUARD A ,  COPEL MATTHEW W ,  DORIS BRUCE B ,  JAMMY RAJARAO ,  KIM YOUNG-HEE ,  LINDER BARRY P ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WONG KEITH KWONG HON

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823842

公开(公告)号：EP1668706A4

公开(公告)日：2008-11-05

申请号：EP04786558

申请日：2004-08-20

Applicant: IBM

Inventor： STEEGEN AN L ,  KU VICTOR ,  WONG KWONG HON ,  LI YING ,  NARAYANAN VIJAY ,  CABRAL CYRIL JR ,  JAMISON PAUL

IPC: H01L29/94 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L29/4958

Abstract: A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure (260) is first formed on an etch stop layer (250) provided on a semiconductor substrate (240). A pair of spacers (400) is provided on sidewalls of the sacrificial gate structure (300). The sacrificial gate structure (300) is then removed, forming an opening (600). Subsequently, a metal gate (1000) including an first layer (700) of metal such as tungsten, a diffusion barrier (800) such as titanium nitride, and a second layer (900) of metal such as tungsten is formed in the opening (600) between the spacers (400).

公开(公告)号：JP2011003899A

公开(公告)日：2011-01-06

申请号：JP2010136861

申请日：2010-06-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ANDO TAKASHI ,  CHOI CHANGHWAN ,  NARAYANAN VIJAY ,  FRANK MARTIN M

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: PROBLEM TO BE SOLVED: To provide a high-k gate dielectric which maintains a constant threshold voltage even after a high temperature process in a CMOS integration step.SOLUTION: A stack of a high-k gate dielectric 30 and a metal gate structure including a lower metal layer 40, a capture metal layer 50, and an upper metal layer 60 is provided. The capture metal layer satisfies the following two standards: (1) to be a metal (M) which indicates a positive change in Gibbs free energy caused by a reaction of Si+2/yMO→2x/yM+SiO; and (2) to be a metal the Gibbs free energy of which is a larger negative value than a metal of the lower metal layer and a metal of the upper metal layer per oxygen atom to form an oxide. The capture metal layer satisfying these standards captures oxide atoms when the oxide atoms pass through a gate electrode, to be diffused toward the high-k gate dielectric. Furthermore, the capture metal layer reduces a thickness of a silicon oxide interface layer under the high-k gate dielectric remotely. As a result, a change in equivalent oxide thickness (EOT) of the whole gate dielectric is controlled.

Abstract translation: 要解决的问题：提供即使在CMOS集成步骤中的高温处理之后仍保持恒定的阈值电压的高k栅极电介质。解决方案：高k栅极电介质30和金属栅极结构的堆叠包括 提供下金属层40，捕获金属层50和上金属层60。 捕获金属层满足以下两个标准：（1）作为表示由Si + 2 / yMO→2x / yM + SiO的反应引起的吉布斯自由能的正变化的金属（M） 和（2）作为金属，其吉布斯自由能比下金属层的金属和每个氧原子的上金属层的金属具有更大的负值，以形成氧化物。 当氧化物原子通过栅电极时，满足这些标准的捕获金属层捕获氧化物原子，以朝向高k栅极电介质扩散。 此外，捕获金属层远离了高k栅极电介质下的氧化硅界面层的厚度。 结果，控制了整个栅极电介质的等效氧化物厚度（EOT）的变化。

公开(公告)号：JP2012054555A

公开(公告)日：2012-03-15

申请号：JP2011187435

申请日：2011-08-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RICKY S AMOS ,  BOYD DIANE C ,  CYRIL CABRAL JR ,  RICHARD D KAPLAN ,  JAKUB T KEDZIERSKI ,  VICTOR KU ,  LEE WOO-HYEONG ,  LI YING ,  MOCUTA ANDA C ,  NARAYANAN VIJAY ,  ANNE L ZEUGEN ,  SERENDRA MAHESWARAN

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/336 ,  H01L21/339 ,  H01L21/60 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

Abstract: PROBLEM TO BE SOLVED: To provide a complementary metal oxide semiconductor integration process that allows a plurality of silicide metal gates to be prepared on a gate dielectric.SOLUTION: There is provided a CMOS silicide metal gate integration method capable of eliminating a demerit of generation of variations in the height of poly Si gate stock which varies a silicide metal gate phase. The integration method minimizes the complexity of the process, thereby restraining the manufacturing cost of a CMOS transistor from increasing.

Abstract translation: 要解决的问题：提供允许在栅极电介质上制备多个硅化物金属栅极的互补金属氧化物半导体集成工艺。 解决方案：提供了一种CMOS硅化物金属栅极集成方法，其能够消除改变硅化物金属栅极相的多晶硅栅极原料的高度变化的缺点。 该集成方法最小化了工艺的复杂性，从而抑制了CMOS晶体管的制造成本增加。 版权所有（C）2012，JPO＆INPIT