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公开(公告)号：KR100807234B1
公开(公告)日：2008-02-28
申请号：KR1020060113093
申请日：2006-11-16
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: H01L21/31133 , G03F7/422 , G03F7/425 , H01L21/28061 , H01L29/4941 , H01L29/517 , H01L29/6659 , H01L29/7833 , G03F7/42
Abstract: A method for removing photoresist is provided to completely remove pretreated photoresist in a cleaning process using a photoresist cleaning solution by making the photoresist modified by being exposed to an ion implantation process have a state of being easily removed in a photoresist cleaning process. Supercritical carbon dioxide is penetrated into photoresist existing on a substrate having a conductive structure including metal to perform a pretreatment process on the photoresist so that the photoresist has a state of being easily removed in a subsequent cleaning process(S130). The pretreated photoresist is removed from the substrate by using a photoresist cleaning solution including an alkanolamine of 8-20 weight percent for avoiding corrosion of the metal, a polar organic solvent of 25-40 weight percent, a reducing agent of 0.5-3 weight percent and excess water(S150). The photoresist can include a photoresist pattern used as an ion implantation mask, a photoresist pattern used as an etch mask, and residual photoresist.
Abstract translation: 提供了一种去除光致抗蚀剂的方法，通过使光致抗蚀剂通过暴露于离子注入工艺而被修饰的光刻胶在光致抗蚀剂清洁过程中具有容易除去的状态，在使用光致抗蚀剂清洁溶液的清洁过程中完全去除预处理的光致抗蚀剂。 超临界二氧化碳渗透到具有包括金属的导电结构的基板上的光致抗蚀剂中，以在光致抗蚀剂上进行预处理工艺，使得光致抗蚀剂在随后的清洗过程中具有容易去除的状态（S130）。 通过使用包含8-20重量％的链烷醇胺的光致抗蚀剂清洁溶液从基材上除去预处理的光致抗蚀剂，以避免金属的腐蚀，25-40重量％的极性有机溶剂，0.5-3重量％的还原剂 和过量水（S150）。 光致抗蚀剂可以包括用作离子注入掩模的光致抗蚀剂图案，用作蚀刻掩模的光致抗蚀剂图案和残留光致抗蚀剂。
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公开(公告)号：KR100806351B1
公开(公告)日：2008-02-27
申请号：KR1020070016450
申请日：2007-02-16
Applicant: 삼성전자주식회사
IPC: H01L21/76
CPC classification number: H01L21/76229 , H01L21/3212
Abstract: A method for fabricating a semiconductor device is provided to minimize a dishing phenomenon at a planarization process for a crystalline semiconductor layer formed in a peripheral region and/or a test device group region. A pattern having trenches(203a,203b) is formed on a semiconductor substrate(200) to expose the substrate, and then a semiconductor layer is formed to bury the trenches. The semiconductor layer is primarily planarized when the pattern is not exposed. A crystalline semiconductor layer is formed on the primarily planarized semiconductor layer by performing an epitaxial growth process. The crystalline semiconductor layer is secondarily planarized to form a crystalline semiconductor pattern. The substrate has a first region and a second region wider than the first region.
Abstract translation: 提供了一种用于制造半导体器件的方法，以便在形成在周边区域和/或测试器件组区域中的结晶半导体层的平坦化处理期间最小化凹陷现象。 在半导体衬底（200）上形成具有沟槽（203a，203b）以露出衬底的图案，然后形成半导体层以埋设沟槽。 当图案不暴露时，半导体层主要是平面化的。 通过进行外延生长工艺，在主要平坦化的半导体层上形成晶体半导体层。 晶体半导体层被二次平坦化以形成晶体半导体图案。 衬底具有比第一区域宽的第一区域和第二区域。
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公开(公告)号：KR1020080008547A
公开(公告)日：2008-01-24
申请号：KR1020060067941
申请日：2006-07-20
Applicant: 삼성전자주식회사
IPC: B24B37/00 , B24B49/02 , H01L21/304
CPC classification number: B24B37/042 , B24B37/005
Abstract: A chemical mechanical polishing apparatus and a method of using the same are provided to prevent asymmetric deformation of patterns and rotation alignment errors by rotating a wafer and a grinding pad to one direction and rotating the wafer and the grinding pad to an opposed direction. A wafer(100) and a grinding pad(104) are contacted each other in the initial grinding process and are rotated to one direction(108) to obtain the first predetermined abrasive volume. The wafer and the grinding pad are accelerated to the opposite direction of the initial rotary direction, and then continue to rotate to the normal direction for a predetermined time to obtain the second predetermined abrasive volume. The rotary speed of the wafer and the pad are reduced with the same change volume, contacted for a predetermined time, and stopped abruptly when the speed reaches 0.
Abstract translation: 提供一种化学机械抛光装置及其使用方法，以通过将晶片和研磨垫旋转到一个方向并将晶片和研磨垫旋转到相对的方向来防止图案的不对称变形和旋转对准误差。 晶片（100）和研磨垫（104）在初始研磨过程中彼此接触并且旋转到一个方向（108）以获得第一预定磨料体积。 将晶片和研磨垫加速到初始旋转方向的相反方向，然后继续向正常方向旋转预定时间以获得第二预定研磨体积。 晶片和焊盘的旋转速度以相同的变化量减小，接触预定时间，并且当速度达到0时突然停止。
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公开(公告)号：KR1020070094682A
公开(公告)日：2007-09-21
申请号：KR1020060025088
申请日：2006-03-18
Applicant: 삼성전자주식회사
IPC: H01L21/306 , H01L21/8242
CPC classification number: H01L21/02068 , H01L21/31111 , H01L27/10808
Abstract: A method for fabricating a semiconductor device is provided to minimize formation of bridges between fine patterns by eliminating water remaining on a substrate using a drying agent containing fluorinated organic compound. A fine pattern is formed on a substrate(100) by using set etching solution, and then the substrate with the fine pattern is dried by using a drying agent containing a fluorinated organic compound. The fluorinated organic compound contains at least one selected from the group consisting of hydrofluoroether(HFE), hydroflurocarbon(HFC), and perflurocarbon(PFC). The substrate with the fine pattern is rinsed by deionized water.
Abstract translation: 提供一种制造半导体器件的方法，以通过使用含有氟化有机化合物的干燥剂除去残留在基底上的水来最小化细纹图案之间的桥的形成。 通过使用设定的蚀刻溶液在基板（100）上形成精细图案，然后使用含有氟化有机化合物的干燥剂干燥具有精细图案的基板。 含氟有机化合物含有选自氢氟醚（HFE），氢氟烃（HFC）和全氟烃（PFC）中的至少一种。 具有精细图案的基底用去离子水冲洗。
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公开(公告)号：KR100745992B1
公开(公告)日：2007-08-06
申请号：KR1020060078381
申请日：2006-08-18
Applicant: 삼성전자주식회사
IPC: H01L21/336
Abstract: A method for manufacturing a semiconductor device is provided to improve the reliability by embodying a complete isolation between adjacent active patterns in spite of mis-alignment of a photomask. A plurality of active patterns are formed on a semiconductor substrate(110). The active patterns are isolated from each other by using isolation layers. The active pattern is covered with a first insulating layer(120). A first groove is formed on the isolation layer between first predetermined active patterns adjacent to each other in a first direction by using first etching. A protection layer is filled in the first groove. A second groove is formed on the isolation layer between active patterns adjacent to each other in a second direction by using second etching. The protection layer is removed from the first groove. A gate line is filled in at least a portion of the second groove along the second direction.
Abstract translation: 提供了一种用于制造半导体器件的方法，以通过在相邻的有源图案之间实现完全隔离而提高可靠性，尽管光掩模未对准。 多个有源图案形成在半导体衬底（110）上。 有源图案通过使用隔离层彼此隔离。 有源图案被第一绝缘层（120）覆盖。 通过使用第一蚀刻在第一方向上彼此相邻的第一预定有源图案之间的隔离层上形成第一凹槽。 保护层填充在第一凹槽中。 通过使用第二蚀刻在第二方向上彼此相邻的有源图案之间的隔离层上形成第二凹槽。 保护层从第一凹槽移除。 栅极线沿着第二方向填充在第二凹槽的至少一部分中。
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Patent Agency Ranking
公开(公告)号：KR100699865B1
公开(公告)日：2007-03-28
申请号：KR1020050090761
申请日：2005-09-28
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76897 , H01L21/7684 , H01L27/10873 , H01L27/10885
Abstract: A method for forming a self-aligned contact pad is provided to restrain the loss of a capping layer due to a hole forming process by introducing an etch mask on the capping layer using a damascene CMP(Chemical Mechanical Polishing) process. Stacked structures composed of a conductive line(300) and an insulating capping layer, a spacer(370) at both sidewalls of each stacked structure and an insulating structure for filling a predetermined gap between adjacent stacked structures are formed on a semiconductor substrate(100). Damascene grooves are formed on the resultant structure by using wet etching or dry etching. A first etch mask is filled in each damascene groove. A second etch mask is then formed thereon. A plurality of opening holes are formed on the resultant structure by etching selectively the insulating structure using the first and second etch masks.
Abstract translation: 提供一种用于形成自对准接触焊盘的方法，以通过使用大马士革CMP（化学机械抛光）工艺在封盖层上引入蚀刻掩模来限制由于孔形成工艺而导致的封盖层的损失。 在半导体衬底（100）上形成由导体线（300）和绝缘覆盖层构成的叠层结构，在每个层叠结构的两个侧壁处的间隔物（370）和用于填充相邻层叠结构之间的预定间隙的绝缘结构， 。 通过使用湿蚀刻或干蚀刻在所得结构上形成镶嵌凹槽。 在每个镶嵌槽中填充第一蚀刻掩模。 然后在其上形成第二蚀刻掩模。 通过使用第一和第二蚀刻掩模选择性地蚀刻绝缘结构，在所得结构上形成多个开孔。
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公开(公告)号：KR100674971B1
公开(公告)日：2007-01-26
申请号：KR1020050034914
申请日：2005-04-27
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11526 , H01L27/105 , H01L27/11543
Abstract: U자형 부유 게이트를 가지는 플래시 메모리 제조방법을 제공한다. 본 발명에서는, 상면과 양 측면 일부가 기판 표면으로부터 돌출된 소자분리막들을 형성한 다음, 소자분리막들 사이의 기판 상에 터널 산화막을 형성한다. 터널 산화막 상에 소자분리막들 사이를 채우지 않는 두께로 도전막을 형성한 다음, 도전막 상에 연마 희생막을 형성한다. 소자분리막 상의 연마 희생막 및 도전막을 제거하여 소자분리막들 사이에 자기 정렬된 U자형 부유 게이트를 형성함과 동시에 부유 게이트 상에 연마 희생막 패턴을 남긴다. 연마 희생막 패턴을 마스크로 이용하여 소자분리막들을 리세스시켜 부유 게이트의 양 측벽을 노출시킨다. 부유 게이트에 대해 연마 희생막 패턴을 선택적으로 제거하여 부유 게이트의 상면을 노출시킨다.
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公开(公告)号：KR1020060119042A
公开(公告)日：2006-11-24
申请号：KR1020050041568
申请日：2005-05-18
Applicant: 삼성전자주식회사
IPC: H01L27/105 , H01L21/304
CPC classification number: H01L27/11507 , G11C11/22 , H01L27/11502 , H01L28/55 , H01L28/75
Abstract: A method for fabricating a ferroelectric layer and a method for manufacturing a semiconductor device using the same are provided to realize a thin ferroelectric layer and to improve degradation thereof by employing a CMP process for polishing a surface of a preliminary ferroelectric layer. A preliminary ferroelectric layer is formed on a substrate(100). The preliminary ferroelectric layer has a thickness of 500 to 1500Š. The preliminary ferroelectric layer is selected from a group consisting of PZT[Pb(Zr,Ti)O3], SBT(SrBi2Ta2O9), BLT[Bi(La,Ti)O3], PLZT[Pb(La,Zr)TiO3], and BST[Bi(Sr,Ti)O 3]. A surface of the preliminary ferroelectric layer is polished to form a ferroelectric layer(115) on the substrate. The ferroelectric layer is cured. The ferroelectric layer has a thickness of 200 to 1000 Š.
Abstract translation: 提供一种制造铁电体层的方法以及使用该方法制造半导体器件的方法，以实现薄铁电体层并通过采用用于抛光预备铁电层的表面的CMP工艺来改善其劣化。 在基板（100）上形成初步铁电层。 初步铁电层的厚度为500〜1500μs。 初步铁电层选自PZT [Pb（Zr，Ti）O3]，SBT（SrBi2Ta2O9），BLT [Bi（La，Ti）O3]，PLZT [Pb（La，Zr）TiO3]和 BST [Bi（Sr，Ti）O 3]。 对初级强电介质层的表面进行研磨，在基板上形成铁电体层（115）。 铁电层被固化。 铁电层的厚度为200〜1000Š。
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公开(公告)号：KR100640628B1
公开(公告)日：2006-10-31
申请号：KR1020050002051
申请日：2005-01-10
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76897
Abstract: 반도체 기판상의 자기정렬 콘택 형성 예정 영역에 보호막 패턴을 형성하고, 자기정렬 콘택 플러그를 형성하지 않는 나머지 영역에만 층간절연막을 형성함으로써 콘택 플러그 형성 예정 영역에서의 층간절연막 에칭 공정이 생략된 반도체 소자의 자기정렬 콘택 플러그 형성 방법에 관하여 개시한다. 본 발명에 따른 반도체 소자의 자기정렬 콘택 플러그 형성 방법에서는 콘택 플러그 형성 예정 영역인 제1 영역과 상기 제1 영역을 제외한 나머지 영역인 제2 영역을 포함하는 반도체 기판을 준비한다. 상기 반도체 기판상에 에칭 장벽층에 의하여 그 상면 및 측벽이 덮인 제1 도전층을 형성한다. 상기 반도체 기판상의 상기 제1 영역 위에만 상기 에칭 장벽층 및 상기 반도체 기판의 표면을 덮는 보호막 패턴을 형성한다. 상기 반도체 기판의 제2 영역 위에만 선택적으로 평탄화된 층간절연막을 형성한다. 상기 보호막 패턴을 제거하여 상기 제1 영역에서 상기 제1 도전층 및 에칭 장벽층 사이로 반도체 기판의 표면을 노출시킨다. 상기 제1 영역에서 노출된 반도체 기판의 표면 위에 상기 제1 도전층 및 에칭 장벽층에 의하여 자기정렬되는 콘택 플러그를 형성한다.
자기정렬 콘택, 희생막, PAE, CMP-
公开(公告)号：KR100634401B1
公开(公告)日：2006-10-16
申请号：KR1020040061232
申请日：2004-08-03
Applicant: 삼성전자주식회사
IPC: H01L21/304
CPC classification number: B08B3/08 , H01L21/02063 , H01L21/02071 , H01L21/02074 , H01L21/3212
Abstract: 반도체 제조공정의 기판 처리 방법을 제공한다. 이 방법은 유기계 첨가물(organic additive)이 함유된 무기계 세정액(inorganic cleaning solution)을 사용하여 기판을 세정하는 단계와, 유기 알코올(organic alcohole)을 사용하여 기판을 린스하는 단계와, 탈이온수(deionized water)를 사용하여 기판을 린스하는 단계를 포함한다.
Abstract translation: 提供了一种半导体制造工艺的衬底处理方法。 该方法包括使用含有机添加剂的无机清洁溶液清洁基板，用有机醇冲洗基板，并用去离子水冲洗基板 ）冲洗基材。
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