公开(公告)号：DE69012395T2

公开(公告)日：1995-03-30

申请号：DE69012395

申请日：1990-03-13

Applicant: IBM

Inventor： FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO

IPC: G11C11/401 ,  G11C7/18 ,  G11C11/4097 ,  G11C7/00 ,  G11C11/409

Abstract: This invention relates to semiconductor memories and includes a sense amplifier architecture in which sensed data bit lines (e.g. BL2, BL2 min ) are electrically isolated and shielded from their immediately adjacent active neighbors by utilization of non-selected bit lines (e.g. BL1, BL1 min and/or BL3, BL3 min ) as an AC ground bus. In its simplest embodiment, shielded bit line (SBL) architecture includes two pairs of opposed bit lines (BL1, BL2; BL1 min , BL2 min )associated with a common sense amplifier (10). One of each of the bit line pairs is multiplexed into the sense amplifier and the other unselected bit line pair is clamped to AC ground to shield the selected bit line pair from all dynamic line-to-line coupling.

公开(公告)号：AU4939390A

公开(公告)日：1990-09-13

申请号：AU4939390

申请日：1990-02-09

Applicant: IBM

Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  LO TIN-CHEE

IPC: G06F12/16 ,  G06F11/10 ,  G06F12/00 ,  G06F11/00

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：DE3377690D1

公开(公告)日：1988-09-15

申请号：DE3377690

申请日：1983-05-06

Applicant: IBM

Inventor： KALTER HOWARD LEO ,  WIEDMAN FRANCIS WALTER

IPC: G06F7/00 ,  G06F7/50 ,  G06F7/505 ,  H03K19/096 ,  H03K19/177

公开(公告)号：MY123248A

公开(公告)日：2006-05-31

申请号：MYPI9904527

申请日：1999-10-20

Applicant: IBM

Inventor： BARTH JOHN E JR ,  BERTIN CLAUDE L ,  DREIBELBIS JEFFREY H ,  ELLIS WAYNE F ,  HOWELL WAYNE J ,  HEDBERG ERIK L ,  KALTER HOWARD LEO ,  TONTI WILLIAM R ,  WHEATER DONALD L

IPC: G11C29/00 ,  H01L21/66 ,  G01R31/28 ,  G01R31/319

Abstract: WAFER TEST AND BURN-IN IS ACCOMPLISHED WITH STATE MACHINE OR PROGRAMMABLE TEST ENGINES (29) LOCATED ON THE WAFER (26) BEING TESTED. EACH TEST ENGINE REQUIRE LESS THAN 10 CONNECTIONS AND EACH TEST ENGINE CAN BE CONNECTED TO A PLURALITY OF CHIPS (28-28", 28A-28E), SUCH AS A ROW OR A COLUMN OF CHIPS ON THE WAFER. THUS, THE NUMBER OF PADS (1-8) OF THE WAFER THAT MUST BE CONNECTED FOR TEST IS SUBSTANTIALLY REDUCED WHILE A LARGE DEGREE OF PARALLEL TESTING IS STILL PROVIDED. THE TEST ENGINES ALSO PERMIT ON-WAFER ALLOCATION OF REDUNDANCY IN PARALLEL SO THAT FAILING CHIPS CAN BE REPAIRED AFTER BURN-IN COMPLETE. IN ADDITION, THE PROGRAMMABLE TEST ENGINES CAN HAVE THEIR CODE ALTERED SO TEST PROGRAMS CAN BE MODIFIED TO ACCOUNT FOR NEW INFORMATION AFTER THE WAFER HAS BEEN FABRICATED. THE TEST ENGINES ARE USED DURING BURN-IN TO PROVIDE HIGH FREQUENCY WRITE SIGNALS TO DRAM ARRAYS THAT PROVIDE A HIGHER EFFECTIVE VOLTAGE TO THE ARRAYS, LOWERING THE TIME REQUIRED FOR BURN-IN. CONNECTIONS TO THE WAFER AND BETWEEN TEST ENGINES AND CHIPS ARE PROVIDED ALONG A MEMBERANE (20-20') ATTACHED TO THE WAFER. MEMBRANE CONNECTORS (31-31") CAN BE FORMED OR OPENED AFTER THE MEMBRANE IS CONNECTED TO THE WAFER SO SHORTED CHIPS CAN BE DISCONNECTED.PREFERABLY THE MEMBRANE REMAINS ON THE WAFER AFTER TEST, BURN-IN AND DICING TO PROVIDE A CHIP SCALE PACKAGE. THUS, THE VERY HIGH COST OF TCE MATCHED MATERIALS, SUCH AS GALSS CERAMIC CONTATCTORS, FOR WAFER BURN-IN IS AVOIDED WHILE PROVIDING BENEFIT BEYOND TEST AND BURN-IN FOR PACKAGING. (FIG. 2)

公开(公告)号：MY118306A

公开(公告)日：2004-09-30

申请号：MYPI9706162

申请日：1997-12-18

Applicant: IBM

Inventor： BURNS STUART MCALLISTER JR ,  HANAFI HUSSEIN IBRAHIM ,  KALTER HOWARD LEO ,  KOCON WALDEMAR WALTER ,  WELSER JEFFREY J

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792

Abstract: A DENSELY PACKED ARRAY (200, 420, 500, 510, 540, 850) OF VERTICAL SEMICONDUCTOR DEVICES, HAVING PILLARS (230) WITH STACK CAPACITORS (520, 520'') THEREON, AND METHODS OF MAKING THEREOF ARE DISCLOSED. THE PILLARS ACT AS TRANSISTOR CHANNELS, AND ARE FORMED BETWEEN UPPER AND LOWER DOPED REGIONS (240, 405). THE LOWER DOPED REGIONS ARE SELF-ALIGNED AND ARE LOCATED BELOW THE PILLARS. THE ARRAY HAS COLUMNS OF BITLINES (220,700, 705) AND ROWS OF WORD LINES (225, 225''). THE LOWER DOPED REGIONS OF ADJACENT BITLINES MAY BE ISOLATED FROM EACH OTHER WITHOUT INCREASING THE CELL SIZE AND ALLOWING A MINIMUM AREA OF APPROXIMATELY 4F2 TO BE MAINTAINED. THE ARRAY IS SUITABLE FOR GBIT DRAM APPLICATIONS BECAUSE THE STACK CAPACITORS DO NOT INCREASE ARRAY AREA. THE ARRAY MAY HAVE AN OPEN BITLINE, A FOLDED, OR AN OPEN/FOLDED ARCHITECTURE WITH DUAL WORDLINES, WHERE TWO TRANSISTORS ARE FORMED ON TOP OF EACH OTHER IN EACH TRENCH. THE LOWER REGIONS MAY BE INITIALLY IMPLANTED. ALTERNATIVE1Y, THE LOWER REGIONS MAY BE DIFFUSED BELOW THE PILLARS AFTER FORMING THEREOF. IN THIS CASE, THE LOWER REGION DIFFUSION MAY BE CONTROLLED EITHER TO FORM FLOATING PILLARS ISOLATED FROM THE UNDERLYING SUBSTRATE, OR TO MAINTAIN CONTACT BETWEEN THE PILLARS AND THE SUBSTRATE. (FIG.8)

公开(公告)号：SG44390A1

公开(公告)日：1997-12-19

申请号：SG1996000087

申请日：1990-02-02

Applicant: IBM

Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  LO TIN-CHEE

IPC: G06F11/10 ,  G06F12/16 ,  G06F11/00

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：DE69123372D1

公开(公告)日：1997-01-16

申请号：DE69123372

申请日：1991-01-24

Applicant: IBM

Inventor： BARTH JOHN EDWARD ,  DRAKE CHARLES EDWARD ,  FIFIELD JOHN ATKINSON ,  HOVIS WILLIAM PAUL ,  KALTER HOWARD LEO ,  LEWIS SCOTT CLARENCE ,  NICKEL DANIEL JOHN ,  STAPPER CHARLES HENRI ,  YANKOSKY JAMES ANDREW

IPC: G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42 ,  G06F11/20

Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：DE69026743T2

公开(公告)日：1996-11-07

申请号：DE69026743

申请日：1990-02-02

Applicant: IBM

Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  LO TIN-CHEE

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/00

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：BR9001125A

公开(公告)日：1991-03-05

申请号：BR9001125

申请日：1990-03-09

Applicant: IBM

Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  LO TIN-CHEE

IPC: G06F12/16 ,  G06F11/10 ,  G11C29/00

Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：DE3377557D1

公开(公告)日：1988-09-01

申请号：DE3377557

申请日：1983-12-21

Applicant: IBM

Inventor： KALTER HOWARD LEO ,  KILEY DONALD BURNS

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/112 ,  H01L27/118 ,  H01L27/10 ,  H01L27/02

Abstract: A transistor array arrangement for providing high-density semiconductor logic circuits in double polysilicon technology is described. Semiconductor, for example, FET, logic circuits have four independent but simultaneously accessible FET devices which are formed by intersecting sets of polysilicon gate lines. The four FET devices share a common first diffusion, for example a source, surrounded by four logically independent second diffusions, for example drains. A three-bit decode device is made which includes this array design.