公开(公告)号：DE102015100771A1

公开(公告)日：2016-07-21

申请号：DE102015100771

申请日：2015-01-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NIESSNER MARTIN RICHARD ,  PAHLKE SEBASTIAN ,  HAUBNER GERHARD ,  HARTNER WALTER

IPC: H01L23/14 ,  H01L21/58 ,  H01L23/64 ,  H05K1/02

Abstract: Ein Chipträger (100) zum Tragen eines gekapselten elektronischen Chips (102), wobei der Chipträger (100) eine Laminatstruktur, die als ein Stapel einer Mehrzahl von elektrisch isolierenden Strukturen (104) und einer Mehrzahl von elektrisch leitfähigen Strukturen (106) ausgebildet ist, und einen Chipkopplungsbereich (108) auf einer freiliegenden Oberfläche der Laminatstruktur umfasst, der zum elektrischen und mechanischen Koppeln des gekapselten elektronischen Chips (102) konfiguriert ist, wobei eine der elektrisch isolierenden Strukturen (104) als ein Hochfrequenzdielektrikum (110) konfiguriert ist, das aus einem Material hergestellt ist, das mit einer verlustarmen Übertragung eines Hochfrequenzsignals kompatibel ist, wobei mindestens eines von einer weiteren der elektrisch isolierenden Strukturen (104) und einer der elektrisch leitfähigen Strukturen (106) als ein thermomechanischer Dämpfer (112) zum Dämpfen von thermisch eingebrachter mechanischer Belastung konfiguriert ist.

公开(公告)号：DE102006029682A1

公开(公告)日：2007-01-11

申请号：DE102006029682

申请日：2006-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  MEISER ANDREAS ,  GRUBER HERMANN ,  BONART DIETRICH ,  GROSS THOMAS

IPC: H01L21/71 ,  H01L21/76 ,  H01L21/768 ,  H01L23/52

Abstract: A production process for a semiconductor structure with deep trench isolation and a buried layer contact comprises forming a stack on a doped semiconductor substrate (1) comprising a highly and oppositely doped buried layer (2) and single crystal semiconductor layer (3), producing a vertical isolation (62) between lateral regions by trench (6) etching and forming a low resistance contact to the buried layer by etching a hole (3) that is narrower and less deep than the trench. Independent claims are also included for: (a) an additional production process as above; and (b) two semiconductor structures formed by the claimed processes.

公开(公告)号：DE10131491B4

公开(公告)日：2006-06-29

申请号：DE10131491

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL ,  WEINRICH VOLKER

IPC: H01L21/8239 ,  H01L21/02 ,  H01L21/8242

Abstract: A method of fabricating semiconductor memory devices is simplified by providing at least some plug regions, which are provided for contacting storage capacitor devices of a capacitor configuration, such that the plug regions have in each case a region that is elevated above the surface region of a passivation region.

公开(公告)号：DE59905479D1

公开(公告)日：2003-06-12

申请号：DE59905479

申请日：1999-07-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HINTERMAIER FRANK ,  SCHINDLER GUENTHER ,  HARTNER WALTER

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502

Abstract: The invention relates to a ferroelectric RAM configuration, including a number of storage cells, each of which has a selection transistor and a capacitor device with a ferroelectric dielectric. The capacitor device includes at least two capacitors whose coercive voltages are different from each other.

公开(公告)号：DE10147929C1

公开(公告)日：2003-04-17

申请号：DE10147929

申请日：2001-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  KROENKE MATTHIAS

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/311

Abstract: A method for producing a semiconductor structure includes applying at least one first layer, etching the first layer using a masking layer such that fences are produced, and, after removal of the masking layer and application of an auxiliary layer, the auxiliary layer and the fences are removed jointly except for a predetermined extent of the auxiliary layer. The present invention also relates to use of the method for producing spacers in a semiconductor structure.

公开(公告)号：DE10131491A1

公开(公告)日：2003-01-16

申请号：DE10131491

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL ,  WEINRICH VOLKER

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/8239

Abstract: Production of a semiconductor storage device comprises: forming a semiconductor substrate (20), a passivating region (21) and/or a surface region (20a, 21a) with a complementary metal oxide semiconductor (CMOS) structure; forming capacitor arrangements (10-1,..., 10-4); and contacting the capacitor arrangements with the CMOS structure using contact regions or plug regions (P1, P2). At least one part of the contact regions or plug regions are formed with a region raised above the surface region of the passivating region. Preferred Features: The contact regions or plug regions are formed in a common process step, preferably after forming the passivating region.

公开(公告)号：DE10105686A1

公开(公告)日：2002-09-05

申请号：DE10105686

申请日：2001-02-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  WEINRICH VOLKER ,  SCHINDLER GUENTHER

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/115 ,  H01L27/11502 ,  H01L21/8239

Abstract: The aim of the invention is to provide protection against the oxidation of plug regions (22) in a semiconductor memory device with high integration densities. To achieve this, during a method for producing memory capacitors (10), the thickness of a sub-layer (14) in a sequence of layers (12, 14, 16, 18) is reduced in the vicinity of the plug regions (22) by an intermediate etching process, to obtain a 3D structure during the conventional 2D deposition of the subsequent layers (16, 18).

公开(公告)号：DE10105673A1

公开(公告)日：2002-09-05

申请号：DE10105673

申请日：2001-02-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KASKO IGOR ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/8239

Abstract: Production of a stacked integrated ferroelectric semiconductor storage device or a DRAM cell comprises depositing an oxygen barrier (3) between a capacitor electrode (4) and an electrically conducting plug (1) which connects the electrode to a semiconductor electrode; and carrying out a rapid thermal processing step at 700-1000 deg C, preferably 800-900 deg C, after depositing the ferroelectric or high iota -material dielectric but before tempering. An Independent claim is also included for an integrated DRAM cell produced. Preferred Features: The temperature of the tempering step is below the temperature of the rapid thermal processing step. The oxygen barrier is made from Ir/IrOx.

公开(公告)号：DE10022656A1

公开(公告)日：2001-11-08

申请号：DE10022656

申请日：2000-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTNER WALTER ,  AHLSTEDT MATTIAS ,  SCHINDLER GUENTHER ,  KASTNER MARCUS ,  BEITEL GERHARD ,  WEINRICH VOLKER

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/8246 ,  H01L27/108 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/8242

Abstract: Removing structures from a substrate comprises preparing a substrate with the structures to be removed; applying a sacrificial layer; and removing the structures and the sacrificial layer by polishing. An Independent claim is also included for a process for removing one or more structured layers from a substrate. Preferred Features: The structures are made from a precious metal, especially Pt or Ir, an oxide of a precious metal, a dielectric material or a ferroelectric material. The sacrificial layer is a silicon oxide or silicon nitride layer.

公开(公告)号：DE10009146A1

公开(公告)日：2001-09-06

申请号：DE10009146

申请日：2000-02-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHINDLER GUENTHER ,  HARTNER WALTER

IPC: C23C26/00 ,  C23C28/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01G4/12 ,  H01L21/8242 ,  H01L27/108 ,  H01L41/16

Abstract: A polycrystalline metal-oxide-containing layer is produced by applying a filling solution to the polycrystalline metal-oxide-containing layer (2) to form a filling layer (3). The filling layer covers the polycrystalline metal-oxide-containing layer and filling cavities formed during crystallization of polycrystalline metal-oxide-containing layer. Production of polycrystalline metal-oxide containing layer comprises: (i) providing a substrate (1); (ii) forming an amorphous metal-oxide-containing layer on the substrate; (iii) carrying out a first thermal treatment so that the amorphous metal-oxide-containing layer crystallizes during first thermal treatment and polycrystalline metal-oxide-containing layer is produced; (iv) applying a filling solution to the polycrystalline metal-oxide-containing layer to form a filling layer; and (v) carrying out a second thermal treatment so that the filling layer crystallizes. The filling layer covers the polycrystalline metal-oxide-containing layer and filling cavities formed during crystallization of the polycrystalline metal-oxide-containing layer. An independent claim is also included for a microelectronic structure comprising a substrate; a polycrystalline metal-oxide-containing layer disposed on the substrate.