公开(公告)号：DE102004010352A1

公开(公告)日：2004-09-23

申请号：DE102004010352

申请日：2004-03-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： COWLEY ANDY ,  HOINKIS MARK ,  KALTALIOGLU ERDEM ,  STETTER MICHAEL

IPC: H01L21/768

Abstract: Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.

公开(公告)号：DE112006000840B4

公开(公告)日：2012-04-26

申请号：DE112006000840

申请日：2006-04-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEROLD KLAUS ,  KALTALIOGLU ERDEM

IPC: H01L21/768 ,  H01L23/528

Abstract: Verfahren zur Herstellung einer Halbleiteranordnung (200), mit den Schritten: Bereitstellen eines Werkstücks (202); Ausbilden einer Vielzahl von Schaltungselementen (206) innerhalb oder über dem Werkstück (202), wobei die Vielzahl von Schaltungselementen (206) ein erstes Kontaktgebiet (208) und ein zweites Kontaktgebiet (216a, 208) umfasst; und Kategorisieren eines ersten leitenden Merkmals (212a) einer Zwischenverbindungsstruktur in eine von zumindest drei Kategorien abhängig von dem Platz von einem Ende des ersten leitenden Merkmals (212a) zu einem ersten benachbarten leitenden Merkmal (212a); Kategorisieren eines zweiten leitenden Merkmals (212a) der Zwischenverbindungsstruktur in eine der zumindest drei Kategorien abhängig von dem Platz von einem Ende des zweiten leitenden Merkmals (212a) zu einem zweiten benachbarten leitenden Merkmal (212a); Ausbilden der Zwischenverbindungsstruktur über der Vielzahl von Schaltungselementen (206), wobei die Zwischenverbindungsstruktur eine Metallisierungsschicht (M1) mit dem ersten leitenden Merkmal (212a) und dem zweiten leitenden Merkmal (212a) umfasst, wobei das erste leitende Merkmal (212a) angeordnet ist...

公开(公告)号：DE102008054320A1

公开(公告)日：2009-06-04

申请号：DE102008054320

申请日：2008-11-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  BAUMGARTNER PETER ,  BENETIK THOMAS ,  KALTALIOGLU ERDEM ,  RIESS PHILIPP ,  RUDERER ERWIN ,  TEWS HELMUT ,  GLASOW ALEXANDER VON

IPC: H01L27/08 ,  H01L21/822

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

公开(公告)号：DE102004005697B4

公开(公告)日：2007-03-29

申请号：DE102004005697

申请日：2004-02-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： COWLEY ANDY ,  STETTER MICHAEL ,  KALTALIOGLU ERDEM

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A conductive line is formed in a first insulating layer. A second insulating layer is formed over the conductive line and the first insulating layer. A via extends through the second insulating layer to contact at least the top surface of the conductive line. The via also extends through the first insulating layer to contact at least a top portion of at least one sidewall of the conductive line. The conductive line sidewall may include an outwardly extending hook region, so that a portion of the via is disposed beneath the conductive line hook region, forming a locking region within the via proximate the conductive line hook region.

公开(公告)号：DE602004003476D1

公开(公告)日：2007-01-11

申请号：DE602004003476

申请日：2004-02-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  FELSNER PETRA ,  KALTALIOGLU ERDEM ,  KERST UWE ,  SCHAFBAUER THOMAS

IPC: H01G4/06 ,  H01G4/228 ,  H01G4/33 ,  H01G4/40 ,  H01L21/768 ,  H01L21/77 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

Abstract: In a method of fabricating a semiconductor device, a level of metal is formed within an interval dielectric. The level of metal includes a first metal line separated from a second metal line by a region of the interlevel dielectric. The region of interlevel dielectric is removed between the first metal line and the second metal line. A high-k dielectric is formed between the first metal line and the second metal line in the region where the interlevel dielectric was removed such that a capacitor is formed by the first metal line, the second metal line and the high-k dielectric.

公开(公告)号：DE102004010352B4

公开(公告)日：2006-10-19

申请号：DE102004010352

申请日：2004-03-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： COWLEY ANDY ,  HOINKIS MARK ,  KALTALIOGLU ERDEM ,  STETTER MICHAEL

IPC: H01L21/768

Abstract: Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.

公开(公告)号：DE102004005697A1

公开(公告)日：2004-08-26

申请号：DE102004005697

申请日：2004-02-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： COWLEY ANDY ,  STETTER MICHAEL ,  KALTALIOGLU ERDEM

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A conductive line is formed in a first insulating layer. A second insulating layer is formed over the conductive line and the first insulating layer. A via extends through the second insulating layer to contact at least the top surface of the conductive line. The via also extends through the first insulating layer to contact at least a top portion of at least one sidewall of the conductive line. The conductive line sidewall may include an outwardly extending hook region, so that a portion of the via is disposed beneath the conductive line hook region, forming a locking region within the via proximate the conductive line hook region.

公开(公告)号：AU2002250505A1

公开(公告)日：2003-10-20

申请号：AU2002250505

申请日：2002-04-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  FELSNER PETRA ,  FRIESE GERALD ,  KALTALIOGLU ERDEM

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/82 ,  H01L23/485 ,  H01L23/525 ,  H01L23/532

公开(公告)号：EP1470580A4

公开(公告)日：2005-07-20

申请号：EP02784578

申请日：2002-11-22

Applicant: INFINEON TECHNOLOGIES AG ,  INFINEON TECHNOLOGIES CORP

Inventor： CHEN TZE-CHIANG ,  ENGEL BRETT H ,  FITZSIMMONS JOHN A ,  KANE TERENCE ,  LUSTIG NAFTALI E ,  MCDONALD ANN ,  MCGAHAY VINCENT ,  SEO SOON-CHEON ,  STAMPER ANTHONY K ,  WANG YUN YU ,  KALTALIOGLU ERDEM

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer (116, 123) is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and the second cap layer (117, 124) is formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. A method for forming the BEOL metallization structure is also disclosed. The invention is particularly useful in interconnect structures comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.

Abstract translation: 公开了一种先进的后端（BEOL）金属化结构。 该结构包括双层扩散阻挡层或盖，其中第一覆盖层由优选通过高密度等离子体化学气相沉积（HDP CVD）工艺沉积的电介质材料形成，并且第二覆盖层由优选沉积的介电材料形成 通过等离子体增强化学气相沉积（PE CVD）工艺。 还公开了一种用于形成BEOL金属化结构的方法。 本发明在包括用于层间电介质（ILD）的低k电介质材料和用于导体的铜的互连结构中是特别有用的。

公开(公告)号：JP2004006852A

公开(公告)日：2004-01-08

申请号：JP2003124691

申请日：2003-04-30

Applicant: IBM

Inventor： RESTAINO DARRYL D ,  SIDDIQUI SHAHAB ,  KALTALIOGLU ERDEM ,  BENNETT DELORES ,  LIU C C ,  CHEN HSUEH-CHUNG ,  CHEN TONG-YU ,  YANG GWO-SHII ,  HSIUNG CHIUNG-SHENG

IPC: H01L21/3205 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To reduce via resistance which often occurs at an interface between a liner and the underside of a copper (Cu) layer in a submicron semiconductor integrated circuit using low dielectric constant (low-k) organic ILD materials. SOLUTION: An adhesive catalyst is applied to an upper layer 30, and a silicon dioxide thin film 50 is formed on it by oxidizing the thin film adhesive catalyst before bonding the organic inter-level dielectric substance. In this way, problem is reduced on via resistance in heat cycle of a semiconductor wafer which materializes multilevel metal and organic inter-level dielectric substance. COPYRIGHT: (C)2004,JPO