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    VIA TRANSMISSION LINES FOR MULTILAYER PRINTED CIRCUIT BOARDS
    214.
    发明申请
    VIA TRANSMISSION LINES FOR MULTILAYER PRINTED CIRCUIT BOARDS 审中-公开
    通过多层印刷电路板的传输线

    公开(公告)号：WO2005086554A1

    公开(公告)日：2005-09-15

    申请号：PCT/JP2005/004595

    申请日：2005-03-09

    Applicant: NEC CORPORATION ,  NEC ELECTRONICS CORPORATION ,  KUSHTA, Taras ,  NARITA, Kaoru ,  TOHYA, Hirokazu ,  SAEKI, Takanori ,  KANEKO, Tomoyuki

    Inventor： KUSHTA, Taras ,  NARITA, Kaoru ,  TOHYA, Hirokazu ,  SAEKI, Takanori ,  KANEKO, Tomoyuki

    IPC: H05K3/46

    CPC classification number: H05K1/0222 ,  H05K1/0269 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

    Abstract: A via transmission line for a multilayer printed circuit board (PCB) in which a wave guiding channel is formed by a signal via or a number of signal vias, an assembly of ground vias surrounding the signal via or corresponding number of coupled signal vias, a set of ground plates from conductor layers of the multilayer PCB, and a clearance hole. In this via transmission line, the signal via, or the number of signal vias forms an inner conductive boundary, ground vias and ground plates from conductor layers of the multilayer PCB form an outer conductive boundary, and the clearance hole provides both isolation of the inner conductive boundary from the outer conductive boundary and high-performance broadband operation of the via transmission line by means of the predeterminded clearance hole cross-sectional shape and dimensions where the cross-sectional shape of the clearance hole is defined by the arrangement of ground vias in the outer conductive boundary and dimensions of the clearance hole are determined according to a method to minimize frequency-dependent return losses caused by specific corrugations of the outer conductive boundary formed by ground plates in the wave guiding channel of the via transmission line.

    Abstract translation: 一种用于多层印刷电路板（PCB）的通孔传输线，其中通过信号通道或多个信号通路形成波导通道，围绕信号通孔或相应数量的耦合信号通孔的接地通孔的组件， 多层PCB的导体层的接地板组以及间隙孔。 在这个通过传输线路中，信号通孔或信号通道的数量形成内部导电边界，从多层PCB的导体层形成的接地孔和接地板形成外部导电边界，并且间隙孔提供内部 通过外部导电边界的导电边界和通孔传输线的高性能宽带操作，借助于预先指定的间隙孔横截面形状和尺寸，其中间隙孔的横截面形状由接地通孔的布置 根据通过在通孔传输线的波导通道中由接地板形成的外导电边界的特定波纹引起的频率相关的返回损耗的方法来确定间隙孔的外导电边界和尺寸。

    PASSIVE TRANSMISSION LINE EQUALIZATION USING CIRCUIT-BOARD THRU-HOLES
    215.
    发明申请
    PASSIVE TRANSMISSION LINE EQUALIZATION USING CIRCUIT-BOARD THRU-HOLES 审中-公开
    使用电路板THRH-HOLES的被动传输线均衡

    公开(公告)号：WO03073808A8

    公开(公告)日：2005-04-07

    申请号：PCT/US0227987

    申请日：2002-09-03

    Applicant: FORCE10 NETWORKS INC

    Inventor： GOERGEN JOEL R

    IPC: H05K1/02 ,  H05K1/11 ,  H05K1/16 ,  H05K3/42 ,  H05K3/46 ,  H05K7/14

    CPC classification number: H05K1/0245 ,  H05K1/0248 ,  H05K1/116 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4641 ,  H05K7/1459 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09718

    Abstract: A high-speed router backplane, and method for its fabrication, are disclosed. The backplane uses differential signaling trace pairs on multiple high-speed signaling layers, the high-speed signaling layers separated by ground planes. Plated signaling thru-holes connect the trace pairs to the board surface for connection to external components. The signaling thru-holes pass through clearances in each ground plane. At selected ground planes, a conductive pad is patterned within each high-speed signaling thru-hole clearance, the pad slightly larger than the thru-hole diameter. The pads affect the impedance characteristics of the thru-holes, thus providing a better impedance match to the differential trace pairs, reducing signal reflections, and improving the ability to signal across the backplane at high speeds.

    Abstract translation: 公开了一种高速路由器背板及其制造方法。 背板在多个高速信号层上使用差分信令跟踪对，高速信号层由接地层分开。 电镀信号通孔将走线对连接到电路板表面，以连接到外部组件。 信号通孔穿过每个接地平面内的间隙。 在选定的接地平面，每个高速信号通孔间隙内的导电焊盘都被图案化，焊盘略大于通孔直径。 这些焊盘影响通孔的阻抗特性，从而为差分走线对提供更好的阻抗匹配，减少信号反射，并提高高速信号跨背板的能力。

    PRINTED WIRING BOARDS HAVING LOW INDUCTANCE EMBEDDED CAPACITORS AND METHODS OF MAKING SAME
    216.
    发明申请
    PRINTED WIRING BOARDS HAVING LOW INDUCTANCE EMBEDDED CAPACITORS AND METHODS OF MAKING SAME 审中-公开
    具有低电感嵌入式电容器的印刷线路板及其制造方法

    公开(公告)号：WO2004056160A1

    公开(公告)日：2004-07-01

    申请号：PCT/US2003/040326

    申请日：2003-12-12

    Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

    Inventor： BORLAND, William, J. ,  FERGUSON, Saul ,  MCGREGOR, David, R.

    IPC: H05K1/16

    CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09763

    Abstract: A printed wiring board (PWB) has stacked innerlayer panels (1001, 1002, 1003, ...) comprised of passive circuit elements (105). The passive elements (105) can include capacitors with electrode terminations located within the footprints of the capacitor electrodes (170, 180). The capacitor terminations are therefore closely spaced, reducing the capacitors' contributions to loop inductance in the innerlayer. Capacitor terminations within the electrode footprints also reduce the PWB board surface area used in forming the capacitors. The capacitor terminations are connected by circuit conductors (1021, 1022).

    Abstract translation: 印刷电路板（PWB）具有由无源电路元件（105）组成的层叠的内层面板（1001,1002,1003，...）。 无源元件（105）可以包括具有位于电容器电极（170,180）的覆盖区内的电极端子的电容器。 因此，电容器端子紧密地间隔开，减小了电容器对内层中的环路电感的贡献。 电极脚印中的电容终端也可以减少用于形成电容器的PWB板表面积。 电容器端子由电路导体（1021,1022）连接。

    PRINTED CIRCUIT BOARD AND METHOD FOR FABRICATING SUCH BOARD
    218.
    发明申请
    PRINTED CIRCUIT BOARD AND METHOD FOR FABRICATING SUCH BOARD 审中-公开
    印刷电路板及其制造方法

    公开(公告)号：WO00033624A1

    公开(公告)日：2000-06-08

    申请号：PCT/US1999/028488

    申请日：1999-12-02

    IPC: H05K1/02 ,  H05K1/11 ,  H05K3/30 ,  H05K3/34 ,  H05K3/42 ,  H05K1/14 ,  H05K7/14

    CPC classification number: H05K1/115 ,  H05K1/024 ,  H05K3/308 ,  H05K3/3421 ,  H05K3/429 ,  H05K2201/09472 ,  H05K2201/09718 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2201/1059 ,  H05K2203/0455

    Abstract: A printed circuit board assembly (10) having a pair of printed circuit boards (12, 14). Each one of the boards (12, 14) has a conductive via (22) passing from a surface of a dielectric (16) into an interior region (17) of the dielectric (16). Each one of the printed circuit boards (12, 14) has a reference potential layer (20) and a signal conductor (18) disposed in the dielectric (16) thereof parallel to, the reference potential layer (20) thereof to provide a transmission line (25) having a predetermined impedance. The signal conductor (18) of each one of the boards is connected to the conductive via (22) thereof. The conductive via (22) in each one of the boards is configured to provide an impedance to the transmission line (25) thereof substantially matched to the impedance of the transmission line (25) thereof. A first electrical connector (32) is provided having a signal contact (36) connected to the conductive via (22) of one (12) of the boards and a second electrical connector (34) having a signal contact (38) connected to the conductive via (22) of the other one (14) of the boards. The first signal contact (36) of the first electrical conductor (32) is adapted for electrical connection to the second contact (38) of the second electrical connector (34).

    Abstract translation: 一种具有一对印刷电路板（12,14）的印刷电路板组件（10）。 每个板（12,14）具有从电介质（16）的表面通过到电介质（16）的内部区域（17）的导电通孔（22）。 每个印刷电路板（12,14）具有参考电位层（20）和布置在其电介质（16）中的信号导体（18），其平行于其参考电位层（20），以提供传输 线（25）具有预定的阻抗。 每个板的信号导体（18）连接到其导电通孔（22）。 每个板中的导电通孔（22）被配置为向其传输线（25）提供与其传输线（25）的阻抗基本匹配的阻抗。 提供第一电连接器（32），其具有连接到一个（12）板的导电通孔（22）的信号触头（36）和具有连接到所述板的信号触头（38）的第二电连接器（34） 另一个（14）板的导电通孔（22）。 第一电导体（32）的第一信号触点（36）适于与第二电连接器（34）的第二触点（38）电连接。

    IMPROVED ISOLATION IN MULTI-LAYER STRUCTURES
    219.
    发明申请
    IMPROVED ISOLATION IN MULTI-LAYER STRUCTURES 审中-公开
    改善多层结构的分离

    公开(公告)号：WO1998009341A1

    公开(公告)日：1998-03-05

    申请号：PCT/US1997014919

    申请日：1997-08-25

    Applicant: THE WHITAKER CORPORATION

    Inventor： THE WHITAKER CORPORATION ,  ATHERTON, John, S. ,  JAIN, Nitin

    IPC: H01P03/08

    CPC classification number: H01P3/088 ,  H05K1/0219 ,  H05K1/0251 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09854

    Abstract: A multi-layer circuit structure with selectively disposed ground planes, selectively disposed signal lines for transmitting signals of a given wavelength at a first level and a second level, dielectric material disposed between each of said ground planes and said signal lines, selectively disposed transition regions for electrically connecting one of the signal lines at said first level to one of said signal lines at said second level, said transition regions having selectively located vias for interconnecting said ground planes, has said vias of a first transmission line being spaced at a distance of other than multiple half wavelengths of said signal relative to said vias of a second transmission line.

    Abstract translation: 一种多层电路结构，具有选择性地设置的接地层，选择性地设置信号线，用于传输给定波长的信号处于第一电平和第二电平，设置在每个所述接地层与所述信号线之间的电介质材料，选择性地设置过渡区域 用于将所述第一电平的信号线之一电连接到所述第二电平的所述信号线之一，所述具有选择性定位的通孔用于互连所述接地平面的所述过渡区具有第一传输线的通孔， 除了所述信号的相对于第二传输线的所述通孔的多个半波长之外。

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