公开(公告)号：CA2719681A1

公开(公告)日：2009-11-19

申请号：CA2719681

申请日：2009-05-05

Applicant: IBM

Inventor： ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  GAMBINO JEFFREY P ,  MUSANTE CHARLES F

IPC: H01L31/112 ,  H01L31/0236

Abstract: Protuberances (5), having vertical (h) and lateral (p) dimensions less than the wavelength range of lights detectable by a photodiode (8), are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sub lithographic features of a first polymeric block component (112) within a matrix of a second polymeric block component (111). The pattern of the polymeric block component is transferred into a first optical layer (4) to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.

公开(公告)号：MY117189A

公开(公告)日：2004-05-31

申请号：MYPI9903633

申请日：1999-08-25

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  ELLIS-MONAGHAN JOHN J ,  MACIEJEWSKI EDWARD P ,  NOWAK EDWARD J ,  PRICER WILBUR DAVID ,  TONG MINH H

IPC: H01L27/06 ,  H01L29/76 ,  H01L21/00 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

Abstract: A DEVICE DESIGN FOR AN FET IN SOL CMOS WHICH IS DESIGNED FOR ENHANCED AVALANCHE MULTIPLICATION OF CURRENT THROUGH THE DEVICE WHEN THE FET IS ON, AND TO REMOVE THE BODY CHARGE WHEN THE FET IS OFF. THE FET HAS AN ELECTRICALLY FLOATING BODY AND IS SUBSTATIALLY ELECTRICALLY ISOLATED FROM THE SUBSTRATE. THE PRESENT INVENTION PROVIDES A HIGH RESISTANCE PATH COUPLING THE FLOATING BODY OF THE FET TO THE SOURCE OF THE FET, SUCH THAT THE RESISTOR ENABLES THE DEVICE TO ACT AS A FLOATING BODY FOR ACTIVE SWITCHING PURPOSES AND AS A GROUNDED BODY IN A STANDBY MODE TO REDUCE LEAKAGE CURRENT. THE HIGH RESISTANCE PATH HAS A RESISTANCE OF AT LEAST 1 M-OHM, AND COMPRISES A POLYSILICON RESISTOR WHICH IS FABRICATED BY USING A SPLIT POLYSILICON PROCESS IN WHICH A BURIED CONTACT MASK OPENS A HOLE IN A FIRST POLYSILICON LAYER TO ALLOW A SECOND POLYSILICON LAYER TO CONTACT THE SUBSTRATE. (FIGURE 1)

公开(公告)号：DE112010004612B4

公开(公告)日：2014-02-13

申请号：DE112010004612

申请日：2010-09-30

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  LEVY MAX G ,  PHELPS RICHARD A ,  BOTULA ALAN B ,  JOSEPH ALVIN J ,  SLINKMAN JAMES A

IPC: H01L27/12 ,  G06F17/50 ,  H01L21/265 ,  H01L21/84

Abstract: Halbleiterstruktur (100), aufweisend: ein Halbleitersubstrat (110) eines bestimmten Leitungstyps mit einer ersten Fläche (114) und einer zweiten Fläche (115) oberhalb der ersten Fläche (114), wobei das Halbleitersubstrat (110) Folgendes aufweist: einen der ersten Fläche (114) benachbarten ersten Teil (101), der einen Dotanden (111) des bestimmten Leitungstyps in einer ersten Konzentration aufweist; und einen zweiten Teil (102), der sich von dem ersten Teil (101) bis zu der zweiten Fläche (115) erstreckt und Folgendes aufweist: eine Vielzahl Mikrokavitäten (122); und in einer zweiten Konzentration, die größer als die erste Konzentration ist, irgendeines des Folgenden: einen gleichen Dotanden (111) wie in dem ersten Teil (101), einen von dem ersten Teil (101) verschiedenen Dotanden (112), wobei der verschiedene Dotand (112) den bestimmten Leitungstyp aufweist, und eine Kombination des gleichen Dotanden (111) und des verschiedenen Dotanden (112); und eine der zweiten Fläche (115) benachbarte Isolatorschicht (120).

公开(公告)号：MY117703A

公开(公告)日：2004-07-31

申请号：MYPI20010672

申请日：2001-02-14

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  FEENEY PAUL M ,  GEFFKEN ROBERT M ,  LANDIS HOWARD S ,  PREVITI-KELLY ROSEMARY A ,  REUTER BETTE BERGMAN L ,  RUTTEN MATTHEW J ,  STAMPER ANTHONY K ,  YANKEE SALLY J

IPC: H01L23/52 ,  H01L23/58 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/532

Abstract: A METHOD AND STRUCTURE FOR A SEMICONDUCTOR CHIP INCLUDES A PLURALITY OF LAYERS OF INTERCONNECT METALLURGY, AT LEAST ONE LAYER OF DEFORMABLE DIELECTRIC MATERIAL OVER THE INTERCONNECT METALLURGY, AT LEAST ONE INPUT/OUTPUT BONDING PAD, AND A SUPPORT STRUCTURE THAT INCLUDES A SUBSTANTIALLY RIGID DIELECTRIC IN A SUPPORTING RELATIONSHIP TO THE PAD THAT AVOIDS CRUSHING THE DEFORMABLE DIELECTRIC MATERIAL.

公开(公告)号：DE10110566A1

公开(公告)日：2001-09-27

申请号：DE10110566

申请日：2001-03-06

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  FEENEY PAUL M ,  GEFFKEN ROBERT M ,  LANDIS HOWARD S ,  PREVITI-KELLY ROSEMARY A ,  BERGMAN-REUTER BETTE L ,  RUTTEN MATTHEW J ,  STAMPER ANTHONY K ,  YANKEE SALLY J

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/532 ,  H01L23/50 ,  H01L21/314

Abstract: Over the coupling metallising is deposited at least one film of deformable dielectric material. A support structure, contg. rigid dielectric, is connected to the deformable dielectric and to an input-output bond island.The support structure also supports the bond island to prevent the fracture of the deformable dielectric material. Typically the support structure contains a cap over the deformable dielectric material, coplanar with the structured last metallising layer. Independent claims are included for integrated circuit chip and for mfr. of semiconductor chip.

公开(公告)号：HK1026064A1

公开(公告)日：2000-12-01

申请号：HK00105169

申请日：2000-08-17

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  ELLIS-MONAGHAN JOHN J ,  MACIEJEWSKI EDWARD P ,  NOWAK EDWARD J ,  PRICER WILBUR D ,  TONG MINH H

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L

Abstract: A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.