公开(公告)号：GB2512783A

公开(公告)日：2014-10-08

申请号：GB201412764

申请日：2013-01-03

Applicant: IBM

Inventor： COONEY EDWARD C ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  LEE TOM C ,  LIU XIAO HU

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures (10), and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire (44, 45) in a dielectric layer (18) and annealing the first wire in an oxygen- free atmosphere. After the first wire is annealed, a second wire (60, 61) is formed in vertical alignment with the first wire. A final passivation layer (74), which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.

公开(公告)号：DE112013000373T5

公开(公告)日：2014-08-28

申请号：DE112013000373

申请日：2013-01-03

Applicant: IBM

Inventor： COONEY EDWARD C ,  GAMBINO JEFFREY P ,  HE ZHONG-XIANG ,  LEE TOM C ,  LIU XIAO H

IPC: H01L21/00

Abstract: Verfahren zum Herstellen einer Back-End-of-Line(BEOL)-Verdrahtungsstruktur, BEOL-Verdrahtungsstrukturen (10) sowie Entwurfsstrukturen für eine BEOL-Verdrahtungsstruktur. Die BEOL-Verdrahtungsstruktur kann mittels Bilden eines ersten Drahtes (44, 45) in einer dielektrischen Schicht (18) und Wärmebehandeln des ersten Drahtes in einer sauerstofffreien Umgebung hergestellt werden. Nach der Wärmebehandlung des ersten Drahtes wird ein zweiter Draht (60, 61) in vertikaler Ausrichtung zu dem ersten Draht gebildet. Es wird eine abschließende Passivierungsschicht (74) gebildet, die aus einem organischen Material wie beispielsweise Polyimid besteht, welche eine Gesamtheit einer Seitenwand des zweiten Drahtes bedeckt.

公开(公告)号：DE112011102130T5

公开(公告)日：2013-03-28

申请号：DE112011102130

申请日：2011-06-08

Applicant: IBM

Inventor： DUNBAR GEORGE A ,  HE ZHONG-XIANG ,  MALING JEFFREY C ,  MURPHY WILLIAM J ,  STAMPER ANTHONY K

IPC: H01L23/48 ,  B81B7/00

Abstract: Ein Verfahren zum Bilden mindestens eines mikroelektromechanischen Systems (MEMS) weist das Bilden einer unteren Verdrahtungsschicht auf einem Substrat auf. Das Verfahren weist ferner das Bilden mehrerer diskreter Drähte (14) aus der unteren Verdrahtungsschicht auf. Das Verfahren weist ferner das Bilden eines Elektrodenarms (38) über den mehreren diskreten Drähten auf. Mindestens eines aus dem Bilden des Elektrodenarms und der mehreren diskreten Drähte erfolgt mit einem Layout, welches Hügel und Triplepunkte bei der folgenden Siliciumabscheidung (50) minimiert.

公开(公告)号：GB2494600A

公开(公告)日：2013-03-13

申请号：GB201300265

申请日：2011-06-08

Applicant: IBM

Inventor： DANG DINH ,  DOAN THAI ,  DUNBAR GEORGE A ,  HE ZHONG-XIANG ,  HERRIN RUSSELL T ,  JAHNES CHRISTOPHER V ,  MALING JEFFREY C ,  MURPHY WILLIAM J ,  STAMPER ANTHONY K ,  TWOMBLY JOHN G ,  WHITE ERIC J

IPC: B81B3/00 ,  B81C1/00 ,  H01H57/00

Abstract: Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity (60a, 60b) having a planar surface using a reverse damascene process.

公开(公告)号：GB2494360A

公开(公告)日：2013-03-06

申请号：GB201300091

申请日：2011-06-08

Applicant: IBM

Inventor： DUNBAR GEORGE A ,  HE ZHONG-XIANG ,  MURPHY WILLIAM J ,  STAMPER ANTHONY K ,  MALING JEFFREY

IPC: B81C1/00

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower wiring layer on a substrate. The method further includes forming a plurality of discrete wires (14) from the lower wiring layer. The method further includes forming an electrode beam (38) over the plurality of discrete wires. The at least one of the forming of the electrode beam and the plurality of discrete wires are formed with a layout which minimizes hillocks and triple points in subsequent silicon deposition (50).

公开(公告)号：AU2003300962A1

公开(公告)日：2005-07-14

申请号：AU2003300962

申请日：2003-12-16

Applicant: IBM

Inventor： WANG PING-CHUAN ,  HE ZHONG-XIANG ,  JOSEPH J ALVIN ,  ORNER A BRADLEY ,  RAMACHANDRAN VIDHYA ,  ONGE A STEPHEN ST

IPC: H01L21/768 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/538 ,  H01L27/06 ,  H01L23/48 ,  H01L29/06

Abstract: Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.

公开(公告)号：GB2494360B

公开(公告)日：2013-09-18

申请号：GB201300091

申请日：2011-06-08

Applicant: IBM

Inventor： DUNBAR GEORGE A ,  HE ZHONG-XIANG ,  MURPHY WILLIAM J ,  STAMPER ANTHONY K ,  MALING JEFFREY C

IPC: B81C1/00

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes patterning a wiring layer to form at least one fixed plate and forming a sacrificial material on the wiring layer. The method further includes forming an insulator layer of one or more films over the at least one fixed plate and exposed portions of an underlying substrate to prevent formation of a reaction product between the wiring layer and a sacrificial material. The method further includes forming at least one MEMS beam that is moveable over the at least one fixed plate. The method further includes venting or stripping of the sacrificial material to form at least a first cavity.

公开(公告)号：DE112011103400T5

公开(公告)日：2013-08-22

申请号：DE112011103400

申请日：2011-09-13

Applicant: IBM

Inventor： MIGA DANIEL R ,  MOON MATTHEW D ,  HE ZHONG-XIANG ,  VANSLETTE DANIEL S ,  WHITE ERIC J ,  DEMUYNCK DAVID A

IPC: H01L21/28

Abstract: Die Offenbarung betrifft allgemein integrierte Schaltungen (ICs), IC-Verbindungen und Verfahren zur Herstellung derselben und insbesondere Hochleistungsinduktoren. Die IC (10) weist mindestens einen Graben (20) innerhalb einer Dielektrikumsschicht (25) auf, die auf einem Substrat (30) angeordnet ist. Der Graben wird formangepasst mit einer Auskleidungs- und Keimschicht (35) beschichtet und weist eine Verbindung (40) darin auf. Die Verbindung weist eine Hartmaske (45) auf den Seitenwänden der Verbindung auf.

公开(公告)号：GB2498154A

公开(公告)日：2013-07-03

申请号：GB201307079

申请日：2011-09-13

Applicant: IBM

Inventor： DEMUYNCK DAVID ,  HE ZHONG-XIANG ,  MIGA DANIEL ,  MOON MATTHEW D ,  VANSLETTE DANIEL ,  WHITE ERIC J

IPC: H01L21/768 ,  H01L23/522

Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC (10) includes at least one trench (20) within a dielectric layer (25) disposed on a substrate (30). The trench is conformally coated with a liner and seed layer (35), and includes an interconnect (40) within. The interconnect includes a hard mask (45) on the sidewalls of the interconnect.

公开(公告)号：GB2496985A

公开(公告)日：2013-05-29

申请号：GB201221074

申请日：2012-11-23

Applicant: IBM

Inventor： MCDEVITT THOMAS LEDDY ,  COONEY EDWARD CRANDAL ,  CHRISMAN GREGORY SCOTT ,  GAMBINO JEFFREY ,  SHAH EVA ,  HE ZHONG-XIANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/64

Abstract: A method of fabricating a structure that provides an interconnect metal wire. A damascene metal wire 20 is surrounded by an insulator 12. To prevent cracking within the insulator material caused by thermal expansion of the metal wire an upper portion of the insulator is etched away to leave an exposed portion of said metal wire. The protruding portion of the metal wire is then rounded using a chemical mechanical polishing (CMP) process. This process results in a wire that has a central portion C that is higher than that of its distil edge, and higher than the top surface of the insulator. During the polishing process no material from the central point of the wire is removed. The disclosed method can be used in the formation of integrated damascene inductors.