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    32.
    发明专利
    未知

    公开(公告)号：DE10250204B8

    公开(公告)日：2008-09-11

    申请号：DE10250204

    申请日：2002-10-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STENGL REINHARD ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  BOECK JOSEF ,  SECK MARTIN ,  LACHNER RUDOLF

    IPC: H01L21/8222 ,  H01L21/331 ,  H01L27/082 ,  H01L29/08 ,  H01L29/732

    Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

    33.
    发明专利
    未知

    公开(公告)号：DE10250204B4

    公开(公告)日：2008-04-30

    申请号：DE10250204

    申请日：2002-10-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STENGL REINHARD ,  MEISTER THOMAS ,  SCHAEFER HERBERT ,  BOECK JOSEF ,  SECK MARTIN ,  LACHNER RUDOLF

    IPC: H01L21/8222 ,  H01L21/331 ,  H01L27/082 ,  H01L29/08 ,  H01L29/732

    Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

    34.
    发明专利
    未知

    公开(公告)号：DE102006043484A1

    公开(公告)日：2008-04-03

    申请号：DE102006043484

    申请日：2006-09-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHAEFER HERBERT ,  BOECK JOSEF ,  LIEBL WOLFGANG ,  KNAPP HERBERT

    IPC: H01L23/525

    Abstract: A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.

    36.
    发明专利
    未知

    公开(公告)号：DE19821901C2

    公开(公告)日：2002-05-08

    申请号：DE19821901

    申请日：1998-05-15

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： REISINGER HANS ,  STENGL REINHARD ,  GRUENING ULRIKE ,  LEHMANN VOLKER ,  WENDT HERMANN ,  WILLER JOSEF ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT

    IPC: H01L21/8244 ,  H01L27/11 ,  G11C11/412

    Abstract: An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

    37.
    发明专利
    未知

    公开(公告)号：DE19958062A1

    公开(公告)日：2001-07-05

    申请号：DE19958062

    申请日：1999-12-02

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STENGL REINHARD ,  MEISTER THOMAS F ,  SCHAEFER HERBERT ,  FRANOSCH MARTIN ,  BOECK JOSEF ,  KLEIN WOLFGANG

    IPC: H01L21/331 ,  H01L29/732 ,  H01L27/082

    Abstract: The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.

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