公开(公告)号：FR2838237A1

公开(公告)日：2003-10-10

申请号：FR0204165

申请日：2002-04-03

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  BENSAHEL DANIEL

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/786 ,  H01L27/105

Abstract: The transistor (T) is situated above a base layer (1) formed on a semiconductor substrate (SB) of a relaxed silicon-germanium alloy, and comprises under the insulated gate (7) a first constrained silicon layer (2) rested on the base layer (1), a buried insulator layer (10) and a second constrained silicon layer (4) extending between the regions of the source (S) and the drain (D) of the transistor. The thickness of the two constrained silicon layers (2,4) and that of the intermediate insulator layer (10) is much less than that of the base layer, and it is a few tens of nanometres, for example 20 nm. The thickness of the base layer (1) is of the order of a few micrometres, for example 2 micrometres. The manufacturing method comprises the formation of the base layer (1) on the silicon substrate (SB), the first constrained silicon layer (2), an intermediate layer of silicon-germanium, the second constrained silicon layer (4), the insulated gate (7) of the transistor flanked by insulating regions (8), an etching of the intermediate layer so to form a tunnel below the insulated gate, filling the tunnel with an insulator material (10), and the formation of the regions of the source (S) and the drain (D). The two constrained silicon layers (2,4) and the intermediate layer are formed by non-selective epitaxy, and an isolation zone (5) is formed in upper part of the base layer compatible with non-relaxation of constraints in the constrained silicon layers.

公开(公告)号：FR2812764B1

公开(公告)日：2003-01-24

申请号：FR0010176

申请日：2000-08-02

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  HAOND MICHEL ,  DUTARTRE DIDIER

IPC: H01L21/762 ,  H01L21/328

Abstract: Processes are provided for fabricating a substrate having a silicon-on-insulator (SOI) or silicon-on-nothing (SON) architecture, which are applicable to the manufacture of semiconductor devices, especially transistors such as those of the MOS, CMOS, BICMOS, and HCMOS types. In the fabrication processes, a multilayer stack is grown on a substrate by non-selective full-wafer epitaxy. The multilayer stack includes a silicon layer on a Ge or SiGe layer. Active regions are defined and masked, and insulating pads are formed so as to be located around the perimeter of each of the active regions at predetermined intervals and placed against the sidewalls of the active regions. The insulating trenches are etched, and the SiGe or Ge layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric. In the case of an SOI archiutecture, the tunnel is filled with a dielectric.

公开(公告)号：FR2819341A1

公开(公告)日：2002-07-12

申请号：FR0100295

申请日：2001-01-11

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  MONFRAY STEPHANE ,  MALLARDEAU CATHERINE

IPC: H01L21/8242 ,  H01L27/108

Abstract: A process for making a DRAM-type cell includes growing layers of silicon germanium and layers of silicon, by epitaxy from a silicon substrate; superposing a first layer of N+ doped silicon and a second layer of P doped silicon; and forming a transistor on the silicon substrate. The method also includes etching a trench in the extension of the transistor to provide an access to the silicon germanium layers relative to the silicon layers over a pre-set depth to form lateral cavities, and forming a capacitor in the trench and in the lateral cavities.

公开(公告)号：FR2807208A1

公开(公告)日：2001-10-05

申请号：FR0003983

申请日：2000-03-29

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  FOURNEL RICHARD ,  DUTARTRE DIDIER ,  RIBOT PASCAL ,  PAOLI MARYSE

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L21/8239

Abstract: Non-volatile memory semiconductor device comprises silicon based semiconductor substrate (SB) containing a source region (S) and a drain region (D), a control gate (GC) and a floating gate (GF). The floating gate extends between the source and drain regions formed in the substrate, and the control gate is situated above the floating gate and juts out with respect to source and drain regions. An Independent claim is included for the fabrication of the non-volatile memory semiconductor device.

公开(公告)号：FR2800913A1

公开(公告)日：2001-05-11

申请号：FR9914105

申请日：1999-11-10

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  MALLARDEAU CATHERINE

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/92 ,  H01G4/33 ,  H01G4/38

Abstract: The invention concerns a method which consists in forming on a substrate coated with a dielectric material layer provided with a window a stack of successive layers alternately of germanium or SiGe alloy and polycrystalline silicon; selective partial elimination of the germanium or SiGe alloy layers, to form an arborescent structure; forming a thin layer of dielectric material on the arborescent structure; and coating the arborescent structure with polycrystalline silicon. The invention is useful for making direct access dynamic memories.

公开(公告)号：FR2799305A1

公开(公告)日：2001-04-06

申请号：FR9912406

申请日：1999-10-05

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA

IPC: H01L21/336 ,  H01L29/786

Abstract: Gate-all-around (GAA) architecture semiconductor device production, by gate formation around a bridge structure formed by removing material below a silicon layer (5) having a thin single crystal central portion (5a), is new. A semiconductor device of GAA architecture is produced from a substrate (1) having a central active semiconductor region (2) surrounded by a peripheral insulating region (3) by (a) selective epitaxy of a single crystal Ge or SiGe alloy layer on the active region main surface; (b) non-selective epitaxy of a silicon layer (5) which is monocrystalline above the single crystal layer and which is polycrystalline above the insulating region surface; (c) masking and etching of the silicon layer (5) and the single crystal layer to form, on the active region main surface, a stack with two opposite side walls exposing the single crystal layer; (d) selective etching away of the single crystal layer so that the silicon layer forms a bridge structure having side walls, an external surface and an internal surface defining, with the active region main surface, a tunnel (7); (e) formation of a dielectric thin film (8, 9), which does not fill the tunnel, on the external and internal surfaces and on the side walls of the bridge structure; (f) deposition of conductive material to cover the bridge structure and to fill the tunnel; and (g) masking and etching of the conductive material to form an all-around gate region (10) of desired dimensions and geometry. An Independent claim is also included for a semiconductor device produced by the above process, the central part (5a) of the bridge structure (5) being of single crystal silicon and being 1-50 nm thick.

公开(公告)号：FR3018389A1

公开(公告)日：2015-09-11

申请号：FR1451833

申请日：2014-03-06

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2

Inventor： TRIOUX EMILIE ,  ANCEY PASCAL ,  MONFRAY STEPHANE ,  SKOTNICKI THOMAS ,  BASROUR SKANDAR ,  MURALT PAUL

IPC: H01L21/203 ,  H01L41/08 ,  H01L41/18 ,  H01L41/27

Abstract: L'invention concerne un procédé de fabrication de lamelles bistables (13) de courbures différentes, chaque lamelle comprenant plusieurs portions de couches de matériaux (15, 17, 19, 21), dans lequel au moins une portion de couche particulière est déposée par un procédé de pulvérisation sous plasma dans des conditions différentes pour chacune des lamelles.

公开(公告)号：DE60214463D1

公开(公告)日：2006-10-19

申请号：DE60214463

申请日：2002-04-02

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  DUTARTRE DIDIER ,  RIBOT PASCAL

IPC: H03H9/24 ,  H03H3/00

Abstract: A resonator formed by the steps of defining an active single-crystal silicon layer delimited by a buried insulator layer, depositing a silicon-germanium layer by a selective epitaxy method so that the silicon-germanium layer grows above the active single-crystal silicon area, depositing by a non-selective epitaxy method a silicon layer and etching it according to a desired contour, and removing the silicon-germanium by a selective etching with respect to the silicon and to the insulator.

公开(公告)号：FR2857952B1

公开(公告)日：2005-12-16

申请号：FR0309106

申请日：2003-07-25

Applicant: ST MICROELECTRONICS SA

Inventor： MONFRAY STEPHANE ,  ANCEY PASCAL ,  SKOTNICKI THOMAS ,  SEGUENI KARIM

IPC: B81B3/00 ,  H03H9/24 ,  H03H3/007

Abstract: The resonator has a monocrystalline silicon substrate provided with an active zone surrounded by a shallow trench isolation region (STI). A vibrating beam is anchored on the region by one of free ends (14, 16) and comprises a monocrystalline silicon median part (12). A control electrode (E) is placed above the beam and is supported on the active zone. The median part is separated from the active zone and the electrode. An independent claim is also included for a method of manufacturing an electromechanical resonator.

公开(公告)号：FR2845201B1

公开(公告)日：2005-08-05

申请号：FR0211989

申请日：2002-09-27

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  REGNIER CHRISTOPHE ,  WACQUANT FRANCOIS ,  SKOTNICKI THOMAS

IPC: H01L21/336 ,  H01L21/28

Abstract: The formation of a portion of a composite material from the elements of an initial material and a metal at the heart of an electronic circuit, comprises: (a) formation of a cavity (C) incorporating at least one opening (O) towards an access surface and presenting an internal wall having a zone of an initial material; (b) deposition of a metal (6) in the proximity of this zone of initial material; (c) heating of the circuit to form a portion of composite material (26) in the zone of initial material; (d) withdrawing from the cavity, via the opening, at least one portion of the metal not having formed the composite material. Independent claims are also included for: (a) an electronic circuit incorporating a portion of composite material formed by this method and acting as an electrical connection; (b) a MOS transistor incorporating a gate having a portion of composite material formed by this method.