公开(公告)号：DE112011100159B4

公开(公告)日：2017-02-02

申请号：DE112011100159

申请日：2011-03-08

Applicant: IBM

Inventor： CHAN KEVIN K ,  REN ZHIBIN ,  WANG XINHUI

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: Halbleitereinheit, die Folgendes umfasst: eine erste Schicht 105 eines vergrabenen Oxids (BOX) auf einem Siliciumsubstrat 106 und eine Rückgate-Metallschicht 103, die auf der Oberseite des BOX von einer oberen Schicht 102 und einer unteren Schicht 104 aus dünnem Nitrid umgeben ist; ein dünnes zweites BOX 101 auf der oberen dünnen Nitridschicht und eine darauf angeordnete dünne SOI-Schicht 100, wobei die zweite BOX-Schicht, die obere dünne Nitridschicht und die dünne SOI-Schicht an ein Abstandselement 150 angrenzen; und einen FET, der über einen Gate-Stapel auf der Oberseite der dünnen SOI-Schicht 131, 132, 133 verfügt, wobei der Gate-Stapel eine dielektrische Schicht 131 an der Grundfläche des Gate-Stapels aufweist, wobei die SOI-Schicht einen vertieften Kanal zu dem FET bereitstellt.

公开(公告)号：DE102012217336B4

公开(公告)日：2014-02-13

申请号：DE102012217336

申请日：2012-09-25

Applicant: IBM

Inventor： CHAN KEVIN K ,  D EMIC CHRISTOPHER ,  KIM YOUNG-HEE ,  PARK DAE-GYU ,  YAU JENG-BANG

IPC: H01L21/283 ,  H01L21/336 ,  H01L21/76 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/49

Abstract: Verfahren (100) zum Ersetzen von Halbleitermaterial durch Metall, wobei das Verfahren (100) Folgendes aufweist: Bilden einer strukturierten Halbleiterschicht (126) auf einer Dielektrikumsschicht (124); Bilden (106) einer Feld-Dielektrikumsschicht (144; 134, 136, 138) welche den Raum zwischen Formen auf der strukturierten Halbleiterschicht (126) füllt; Aufbringen (110) von Metall (170) auf die Formen (142); und Tempern (112) des Wafers (120), wobei das aufgebrachte Metall (170) in jeder der Formen (142) den Halbleiter ersetzt, wobei es sich bei den Formen um Silicium-Platzhalter und bei dem Metall (170) um Aluminium handelt, und wobei das Aufbringen (110) von Aluminium (170) das Strukturieren einer aufgebrachten Aluminiumschicht (170) in einem Aluminium-Abhebeverfahren aufweist; und das Tempern (112) des Wafers (120) ein Kurzzeittempern für zwei Stunden bei vierhundert Grad Celsius umfasst.

公开(公告)号：GB2492524A

公开(公告)日：2013-01-02

申请号：GB201220031

申请日：2011-04-08

Applicant: IBM

Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON ,  LI JINGHONG ,  NEWBURY JOSEPH ,  ONTALUS VIOREL ,  PARK DAE-GYU ,  ZHU ZHENGMAO

IPC: H01L29/78 ,  H01L21/8238

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.

公开(公告)号：CA2695715C

公开(公告)日：2011-06-07

申请号：CA2695715

申请日：2003-02-19

Applicant: IBM

Inventor： APPENZELLER JOERG ,  AVOURIS PHAEDON ,  CHAN KEVIN K ,  COLLINS PHILIP G ,  MARTEL RICHARD ,  WONG HON-SUM PHILIP

IPC: H01L21/335 ,  B82Y40/00 ,  H01L29/772 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube [104] deposited on a substrate [102], a source and a drain [106-107] formed at a first end and a second end of the carbon-nanotube [104], respectively, and a gate [112] formed substantially over a portion of the carbon-nanotube [104], separated from the carbon-nanotube by a dielectric film [111].

公开(公告)号：CA2479024C

公开(公告)日：2010-02-16

申请号：CA2479024

申请日：2003-02-19

Applicant: IBM

Inventor： APPENZELLER JOERG ,  AVOURIS PHAEDON ,  CHAN KEVIN K ,  COLLINS PHILIP G ,  MARTEL RICHARD ,  WONG HON-SUM PHILIP

IPC: H01L51/00 ,  H01L51/05 ,  H01L51/30

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube [104] deposited on a substrate [102], a source and a drain [106-107] formed at a first end and a second end of the carbon-nanotube [104], respectively, and a gate [112] formed substantially over a portion of the carbon-nanotube [104], separated from 10 the carbon-nanotube by a dielectric film [111].

公开(公告)号：DE60138161D1

公开(公告)日：2009-05-14

申请号：DE60138161

申请日：2001-02-15

Applicant: IBM

Inventor： CHAN KEVIN K ,  SHI LEATHEN ,  ZIEGLER JAMES F ,  JHANES CHRISTOPHER ,  SPEIDEL JAMES L

IPC: H03H9/05 ,  B81B3/00 ,  B81B7/00 ,  B81C1/00 ,  H03D7/00 ,  H03D9/06 ,  H03H3/007 ,  H03H9/10 ,  H03H9/24 ,  H03H9/46 ,  H04B1/26

Abstract: Communication signal mixing and filtering systems and methods utilizing an encapsulated micro electro-mechanical system (MEMS) device. Furthermore, disclosed is a method of fabricating a simple, unitarily constructed micro electro-mechanical system (MEMS) device which combines the steps of signal mixing and filtering, and which is smaller, less expensive and more reliable in construction and operation than existing devices currently employed in the technology.

公开(公告)号：PL373571A1

公开(公告)日：2005-09-05

申请号：PL37357103

申请日：2003-02-19

Applicant: IBM

Inventor： APPENZELLER JOERG ,  AVOURIS PHAEDON ,  CHAN KEVIN K ,  COLLINS PHILIP G ,  MARTEL RICHARD ,  WONG HON-SUM PHILIP

IPC: H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L51/20 ,  H01L29/51

Abstract: A carbon-nanotube field transistor semiconductor device, comprising: a vertical carbon-nanotube (508) wrapped in a dielectric material (511); a source formed at a first side of the carbon-nanotube; a drain (515) formed on a second side of the carbon-nanotube; a bilayer nitride complex through which a band strap of each of the source and the drain is formed connecting the carbon-nanotube wrapped in the dielectric material to the source and the drain; and a gate (512) formed substantially over a portion of the carbon-nanotube. Further disclosed are methods for forming the following self-aligned carbon-nanotube field effect transistor: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

公开(公告)号：AU2003224668A1

公开(公告)日：2003-10-08

申请号：AU2003224668

申请日：2003-02-19

Applicant: IBM

Inventor： MARTEL RICHARD ,  WONG HON-SUM PHILIP ,  APPENZELLER JOERG ,  AVOURIS PHAEDON ,  CHAN KEVIN K ,  COLLINS PHILIP G

IPC: H01L51/00 ,  H01L51/05 ,  H01L51/30

Abstract: A carbon-nanotube field transistor semiconductor device, comprising: a vertical carbon-nanotube (508) wrapped in a dielectric material (511); a source formed at a first side of the carbon-nanotube; a drain (515) formed on a second side of the carbon-nanotube; a bilayer nitride complex through which a band strap of each of the source and the drain is formed connecting the carbon-nanotube wrapped in the dielectric material to the source and the drain; and a gate (512) formed substantially over a portion of the carbon-nanotube. Further disclosed are methods for forming the following self-aligned carbon-nanotube field effect transistor: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

公开(公告)号：CA2695715A1

公开(公告)日：2003-10-02

申请号：CA2695715

申请日：2003-02-19

Applicant: IBM

Inventor： APPENZELLER JOERG ,  AVOURIS PHAEDON ,  CHAN KEVIN K ,  COLLINS PHILIP G ,  MARTEL RICHARD ,  WONG HON-SUM PHILIP

IPC: H01L21/335 ,  H01L29/772 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube [104] deposited on a substrate [102], a source and a drain [106-107] formed at a first end and a second end of the carbon-nanotube [104], respectively, and a gate [112] formed substantially over a portion of the carbon-nanotube [104], separated from the carbon-nanotube by a dielectric film [111].

公开(公告)号：CA2659479A1

公开(公告)日：2003-10-02

申请号：CA2659479

申请日：2003-02-19

Applicant: IBM

Inventor： MARTEL RICHARD ,  APPENZELLER JOERG ,  CHAN KEVIN K ,  AVOURIS PHAEDON ,  WONG HON-SUM PHILIP ,  COLLINS PHILIP G

IPC: H01L21/18 ,  H01L29/16 ,  H01L29/772 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube [104] deposited on a substrate [102], a source and a drain [106-107] formed at a first end and a second end of the carbon-nanotube [104], respectively, and a gate [112] formed substantially over a portion of the carbon-nanotube [104], separated from the carbon-nanotube by a dielectric film [111].