公开(公告)号：DE102005037029A1

公开(公告)日：2007-01-11

申请号：DE102005037029

申请日：2005-08-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OLLIGS DOMINIK ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  BACH LARS ,  POLEI VERONIKA ,  MUELLER TORSTEN

IPC: H01L21/8247 ,  G11C16/02

Abstract: A semiconductor product includes, a substrate with a first dielectric layer having contact hole fillings for contacting active areas in the substrate. A second dielectric layer with contact holes is provided therein. The contact holes have a width in a first lateral direction. The product further includes conductive lines, each conductive line passing over contact holes in the second dielectric layer and contacting a plurality of contact hole fillings in the first dielectric layer. The conductive lines have a width, in the first lateral direction, that is smaller than the width of the contact holes of the second dielectric layer. The conductive lines are in direct mechanical contact with the contact hole fillings and thereby remove the need to provide any conventional "contact to interconnect" structures.

公开(公告)号：DE102004050927B4

公开(公告)日：2006-10-26

申请号：DE102004050927

申请日：2004-10-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WILLER JOSEF ,  MIKOLAJICK THOMAS

IPC: H01L27/115 ,  G11C7/18 ,  G11C11/4097

Abstract: Bitline conductor tracks are arranged parallel to one another and electrically insulated from a substrate provided with a basic doping. A memory layer sequence, especially a charge-trapping layer sequence with a dielectric memory layer between dielectric confinement layers, is provided at least in regions adjacent to the bitline conductor tracks. The memory cells comprise gate electrodes connected by wordlines, and channel regions below the gate electrodes. They can be programmed by the trapping of channel hot electrons that are accelerated between source and drain regions formed by induced bitlines that are generated by the application of voltages to the bitline conductor tracks.

公开(公告)号：DE10131627B4

公开(公告)日：2006-08-10

申请号：DE10131627

申请日：2001-06-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRUCHHAUS RAINER ,  ENDERS GERHARD ,  HARTNER WALTER ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS ,  NAGEL NICOLAS ,  ROEHNER MICHAEL

IPC: H01L21/8239 ,  H01L21/02 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

Abstract: Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration extending into the third dimension. A contacting of plug regions is performed after producing the capacitor devices. Such capacitor devices provide an increased integration density in a semiconductor memory device.

公开(公告)号：DE102004050927A1

公开(公告)日：2006-03-30

申请号：DE102004050927

申请日：2004-10-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WILLER JOSEF ,  MIKOLAJICK THOMAS

IPC: H01L27/115 ,  G11C7/18 ,  G11C11/4097

Abstract: Bitline conductor tracks are arranged parallel to one another and electrically insulated from a substrate provided with a basic doping. A memory layer sequence, especially a charge-trapping layer sequence with a dielectric memory layer between dielectric confinement layers, is provided at least in regions adjacent to the bitline conductor tracks. The memory cells comprise gate electrodes connected by wordlines, and channel regions below the gate electrodes. They can be programmed by the trapping of channel hot electrons that are accelerated between source and drain regions formed by induced bitlines that are generated by the application of voltages to the bitline conductor tracks.

公开(公告)号：DE10355561A1

公开(公告)日：2005-06-30

申请号：DE10355561

申请日：2003-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEZI RECAI ,  WALTER ANDREAS ,  ENGL REIMUND ,  MALTENBERGER ANNA ,  DEHM CHRISTINE ,  ARKALGUD SITARAM ,  KASKO IGOR ,  NUETZEL JOACHIM ,  KRIZ JAKOB ,  MIKOLAJICK THOMAS ,  PINNOW CARL-UWE

IPC: C09D5/24 ,  C09D5/25 ,  G11C13/02 ,  H01L27/24 ,  H01L27/28 ,  H01L51/00 ,  H01L51/30

公开(公告)号：DE10326805A1

公开(公告)日：2005-01-13

申请号：DE10326805

申请日：2003-06-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  MIKOLAJICK THOMAS ,  BIRNER ALBERT

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L27/115 ,  H01L21/8247

Abstract: Silicon nanocrystals are applied as storage layer ( 6 ) and removed using spacer elements ( 11 ) laterally with respect to the gate electrode ( 5 ). By means of an implantation of dopant, source/drain regions ( 2 ) are fabricated in a self-aligned manner with respect to the storage layer ( 6 ). The portions of the storage layer ( 6 ) are interrupted by the gate electrode ( 5 ) and the gate dielectric ( 4 ), so that a central portion of the channel region ( 3 ) is not covered by the storage layer ( 6 ). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.

公开(公告)号：DE10308970A1

公开(公告)日：2004-09-09

申请号：DE10308970

申请日：2003-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  MIKOLAJICK THOMAS

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L27/115 ,  H01L21/8247

公开(公告)号：AU2003292985A1

公开(公告)日：2004-06-18

申请号：AU2003292985

申请日：2003-11-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLOSE HELMUT ,  MIKOLAJICK THOMAS ,  WERNER WOLFGANG

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/00

Abstract: A semiconductor memory device with a phase transformation memory effect includes at least one memory element in a semiconductor substrate, and a cavity arrangement including at least one cavity in spatial proximity to the respective memory element. The cavity is in spatial arrangement with the respective memory element so as to reduce thermal coupling of the respective memory element to the areas surrounding the memory element, which also reduces the thermal conductivity between memory element and the areas surrounding the memory element.

公开(公告)号：DE10153561C2

公开(公告)日：2003-09-04

申请号：DE10153561

申请日：2001-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS

IPC: G11C16/04 ,  H01L21/28 ,  H01L29/792

Abstract: The cell has a charge-trapping gate configuration with each gate substantially independently storing the information. The storage of the information units and binary bits are done independent of each another in a memory cell (10). The charge tipping gate configurations are accessed by a source/drain configuration (SD1, SD2) and controlled by a control gate configuration. An Independent claim is also included for a method to fabricate a charge trapping memory cell.

公开(公告)号：DE10140758A1

公开(公告)日：2003-04-24

申请号：DE10140758

申请日：2001-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MIKOLAJICK THOMAS

IPC: G11C11/56 ,  H01L29/788 ,  G11C11/02 ,  G11C11/21

Abstract: A memory element includes a number of material areas isolated from one another to form at least one area with changed electrical and/or magnetic characteristics in an isolation area, which material areas have or form free charge carriers. An information unit can correspondingly be written to, deleted, and/or read from by influencing the material areas by applying an electrical potential to line devices that are provided in areas.