公开(公告)号：JPH0855496A

公开(公告)日：1996-02-27

申请号：JP7308495

申请日：1995-03-30

Applicant: ST MICROELECTRONICS SRL

Inventor： ROLANDI PAOLO

IPC: G11C29/00 ,  G11C14/00 ,  G11C16/04 ,  G11C16/26 ,  G11C29/04

Abstract: PURPOSE: To eliminate the need for a reset circuit by connecting a 1st and a 2nd memory cell to a write circuit during writing and to a bistable circuit during reading by a switching circuit element. CONSTITUTION: During a test, a connection with the write circuit WRT is made by switching circuits SW1 and SW2 of electronic or complementary transistors to perform a writing process. During this operation, elements WS1 and WS2 enable only a reading process instead of a connection with a memory cell to store storage information in a flip-flop type circuit LATCH. During the writing process, one cell is written and the other cell is cleared. When the device turns on, the elements SW1 and SW2 enters a direct operation state in response to actuation to the circuit LATCH and there is no power consumption. When one memory cell is written to a logical high level in response to the said turning-on operation, the circuit LATCH enters a prescribed state. The circuit LATCH which is made unbalanced by the cell where the information is written holds the other cell in the cleared state each time the power source is turned on.

公开(公告)号：JPH0855486A

公开(公告)日：1996-02-27

申请号：JP6942595

申请日：1995-03-28

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  DALLABORA MARCO

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  G11C16/34

Abstract: PURPOSE: To maintain the precision of a virgin cell for a long period and improve the reliability of the circuit by using the virgin cell which has characteristics shifted by a voltage shifter. CONSTITUTION: A cell and virgin cells 12 and 13 have gate-source voltages lower than a source voltage through voltage shifters 14 and 15 and their characteristics depend upon an operating load. In read mode, a logical signal R is low and a logical signal V is high, so switches 21, 26, 29, 33, and 40 are closed and a switch 42 is opened. When the source voltage is lower than 2.3V as the threshold voltage of the cells 12 and 13, the cells 11, 12, and 13 are turned off. When the source voltage exceeds it, the cells 12 and 13 turn on, but their characteristics become smaller than a logical slope because of the presence of the load. The cell 11 is off between 2.3V and the source voltage and then a current flows to neither a load transistor 18 nor a mirror transistor 23; and only the cell 12 has a high resistance value and a current is made to flow through a load transistor 30 for supply current limitation.

公开(公告)号：JPH0846200A

公开(公告)日：1996-02-16

申请号：JP17871495

申请日：1995-07-14

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/74 ,  H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/749 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide an MOS technology power device having integrated circuit in which the series resistance of gate can be decreased without increasing the number of gate metal finger parts. SOLUTION: The MOS technology power device of integrated structure comprises a plurality of functional units of basic component formed in a lightly doped first conductivity type semiconductor layer 1 wherein the functional unit has a second conductivity type channel region 6 coated with a conductive insulation gate layer 8 including a polysilicon layer 5. The conductive insulation gate layer 8 has resistivity significantly lower than that of the polysilicon layer 5 superposed by a highly conductive layer 9. Since a resistance introduced by the polysilicon layer 5 is shunted by a resistance introduced by the highly conductive layer 9, total resistivity of the conductive insulation gate layer 8 is decreased.

公开(公告)号：JPH0831122A

公开(公告)日：1996-02-02

申请号：JP12230495

申请日：1995-05-22

Applicant: ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  GADDUCCI PAOLO ,  MOLONEY DAVID ,  PISATI VALERIO

IPC: G11B20/14 ,  G11B5/02 ,  G11B5/09 ,  G11B5/596 ,  G11B20/06 ,  G11B20/10 ,  G11B20/18 ,  G11B21/10

Abstract: PURPOSE: To obtain a servo signal processing device which is effectively used by a parallel structure PRML reading apparatus. CONSTITUTION: This device is used in a parallel structure PRML reading apparatus comprising a variable-gain input amplifier 21, a low-pass analog filter 22, a transversal continuous-time analog filter 23 and a couple of individual parallel processing channels 24, 34 sandwiched between the transversal analog filter 23 and RLL-NRZ decoder 25. Two processing channels 24, 34 are respectively provided with analog-digital converters 26, 36 and subsequent viterbi detectors 27, 37 and are operated depending on alternate sampling systems. The servo signal processing device 30 is provided with a rectifier 31 and an integrator 32 connected to the analog digital converters 26, 36.

公开(公告)号：JPH0822698A

公开(公告)日：1996-01-23

申请号：JP2664295

申请日：1995-02-15

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

Abstract: PURPOSE: To eliminate the need of generating an ON-CHIP exclusive signal to reduce the chip size by using the existing signal line in a memory to program a redundant register. CONSTITUTION: A two-dimensional array memory matrix provided with a 16-bit data bus is divided into a plurality of portions each of which is composed of a plurality of bit groups. Redundant registers RR1-4 composed of programmable non-volatile memory is capable of programming an address of the defective bit line received from a column address signal CABUS in its first block 1. Moreover, in the second block 2, an identification code MCS7-10 of the bit group to which a defective bit line belongs obtained from the first part R1-4 of the row address signal set RABUS. A programming selection means 6 selects the redundant register RR1-4 with the second part R5-8 of the row address signal set RABUS to store the address information of the defective bit line.

公开(公告)号：JPH07326680A

公开(公告)日：1995-12-12

申请号：JP32565594

申请日：1994-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： KRAMER ALAN ,  SABATINI MARCO

IPC: H01L21/8247 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To obtain a very small sized capacitive element which has a nonlinear characteristic and is capable of programming in an analog mode. CONSTITUTION: A flash EEPROM memory cell 30 is a nonvolatile memory cell includes a 2 level polycrystalline silicon, and a source region 38, a drain region 31, a channel region 34 between the source region and the drain region, a floating gate 33, and a control gate 32, the channel region extending to two transversal zone below the floating gate and the control gate and perpendicularly to a source/drain direction.

公开(公告)号：JPH07298101A

公开(公告)日：1995-11-10

申请号：JP29325394

申请日：1994-11-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： MANCUSO MASSIMO ,  POLUZZI RINALDO ,  RIZZOTTO GIANGUIDO

IPC: G06F9/44 ,  G06N7/02 ,  G06T5/00 ,  H03H17/00 ,  H04N5/21 ,  H04N5/93 ,  H03H17/02

Abstract: PURPOSE: To attain noise reduction through a filter for filtering only the noise- containing signal sections in digital video signals. CONSTITUTION: Each circuit means is operated by a fuzzy logic and provided with inference circuits (look-up tables) C1 and C2 and digital subtracters S1-S4. Each subtracter has an input terminal and is provided for receiving an individual digital video signal for reporting information concerning the pixel to be processed. The number of circuit means included in a filter 1 depends on the size of an image to be processed, and secondly, depends on the number of directions under the operation of a line operator. While using fuzzy type logic rules, a noise calculation circuit 4 compares trigger levels determined in the circuits C1 and C2 with such a trigger level. Thus, noise contained in the digital video signal are reduced effectively.

公开(公告)号：JPH07283664A

公开(公告)日：1995-10-27

申请号：JP29668694

申请日：1994-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PERNICI SERGIO

IPC: H03F1/08 ,  H03F1/34 ,  H03F1/52 ,  H03F3/45

Abstract: PURPOSE: To obtain a high output dynamic characteristic, a satisfactory gain bandwidth product, and a satisfactory stability with a low voltage power source by constituting input and output circuits of differential types using FETs having low and high thresholds and inversely feeding back them to each other by first and second capacitors. CONSTITUTION: The input circuit consists of a differential stage of transistors TRs M1 and M2, a cascode stage of TRs M3 to M6, and a TR M0, and the output circuit consists of TRs M7A, M7B2, M8A, and M8B, and they are constituted of differential types. Control terminals of output TRs M8A and M8B are connected to nodes A and B and output terminals VOUT+ and VOUT- are connected to nodes C and D through capacitors CcA and CcB to perform mutual inverse feedback. A power VCC is supplied to input and output circuits through current generators of these TRs M0, M7A, and M7B, and MOS TRs having a high threshold are used as TRs M8A and M8B, and MOS TRs having a low threshold are used as TRs M3 to M6. Thus, a high output dynamic characteristic, a satisfactory gain bandwidth product, and a satisfactory stability are obtained with a low voltage power source.

公开(公告)号：JPH07263982A

公开(公告)日：1995-10-13

申请号：JP24959994

申请日：1994-10-14

Applicant: ST MICROELECTRONICS SRL

Inventor： CORDINI PAOLO ,  PEDRAZZINI GIORGIO ,  ROSSI DOMENICO

IPC: H03K19/018 ,  G06J1/00 ,  H03F3/62 ,  H03F3/68

Abstract: PURPOSE: To obtain an effective interface by providing an integrated circuit which operates with a low-voltage and a high-voltage input signal and outputs a high-voltage or low-voltage signal corresponding to them. CONSTITUTION: Cutoff circuit block 4 inhibits a 1st amplifying circuit block 2 from becoming conductive when a high-voltage output terminal operates as an input terminal. Consequently, any high-voltage signal applied to the high- voltage output terminal B operates on only a 2nd amplification block 3. A 2nd amplifying circuit block 3, on the other hand, consists of a power element which operates with a high voltage, withstands high-voltage input, and outputs a low-voltage signal. For the application of this interface circuit 1 to an industrial control unit, the 1st amplifying circuit block 2 operates relatively to an actuator, but the 2nd amplifying circuit block 3 operates relatively to a microcontroller. This block 2 can be powered directly by the same power source with the actuator and the block 3 can share a low-voltage power source with the microcontroller.

公开(公告)号：JPH07263971A

公开(公告)日：1995-10-13

申请号：JP6682295

申请日：1995-02-28

Applicant: ST MICROELECTRONICS SRL

Inventor： CHRAPPAN FRANCESCO ,  NESSI MAURIZIO ,  SALINA ALBERTO

IPC: H03F3/20 ,  H02P25/034 ,  H03F1/32 ,  H03F3/30 ,  H03F3/347

Abstract: PURPOSE: To effectively control the operation of an externally connected output power transistor(TR) by directly driving it with the output of an operational amplifier without using any external sense resistance. CONSTITUTION: A buffer stage BF1 shifts its input voltage toward a ground potential by a value equal to the threshold voltage of M2 under a zero-input condition. Therefore, the gate-source voltage of the external power transistor TRM 4 which is driven by the buffer becomes zero under the zero-input condition and its turn-off state is secured. As the current which is led out by the load increases, the output voltage VOP1 of a signal amplifier OP1 increases and a TRM2 is placed nearly in its saturated state. Here, when the current that the load requires becomes larger than the limit current IM2 passing through the M2, a maximum current like this which passes through the M2 is limited by a resistance R, so the output voltage of the signal amplifier OP1 increases until it meets a condition of VBF1 >Vth M4 +V0 and an external power TR is turned off.