公开(公告)号：DE10341592B4

公开(公告)日：2008-01-24

申请号：DE10341592

申请日：2003-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HIRLER FRANZ ,  TIHANYI JENOE ,  HENNINGER RALF ,  KRUMREY JOACHIM ,  POELZL MARTIN ,  RIEGER WALTER

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

公开(公告)号：DE10234996B4

公开(公告)日：2008-01-03

申请号：DE10234996

申请日：2002-07-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENNINGER RALF ,  HIRLER FRANZ ,  KRUMREY JOACHIM ,  RIEGER WALTER ,  POELZL MARTIN ,  HOFER HEIMO

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78

公开(公告)号：DE10212149B4

公开(公告)日：2007-10-04

申请号：DE10212149

申请日：2002-03-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENNINGER RALF ,  HIRLER FRANZ ,  KRUMREY JOACHIM ,  RIEGER WALTER ,  POELZL MARTIN

IPC: H01L29/78 ,  H01L27/105 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417

Abstract: The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD of the transistor configuration is reduced by the shielding electrode located in the edge region.

公开(公告)号：DE10214151B4

公开(公告)日：2007-04-05

申请号：DE10214151

申请日：2002-03-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENNINGER RALF ,  HIRLER FRANZ ,  KRUMREY JOACHIM ,  ZUNDEL MARKUS ,  RIEGER WALTER ,  POELZL MARTIN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

Abstract: The device has a cell field with identical cells and an edge cell(s). Each cell has a first connection zone, a channel zone and a control electrode(s) in a trench. The individual cells' trenches are arranged at intervals. The edge cell has a field plate in a trench isolated from the semiconducting body by an insulating coating. The distance from the edge cell trench to that of the adjacent cell is less than between trenches of cell field cells. The device has a cell field with several identical transistor cells (Z1-Z3) and at least one edge cell (RZ). Each cell has a first connection zone, a channel zone (20) and at least one control electrode (42) in a trench (40), whereby the trenches of the individual cells are arranged at intervals in the horizontal direction. The edge cell has a field plate (52) in a trench (50) and isolated from the semiconducting body (100) by an insulating coating (54). The distance from the edge cell trench to that of the adjacent cell is less than the distance between trenches of cells in the cell field.

公开(公告)号：DE10129348B4

公开(公告)日：2007-04-05

申请号：DE10129348

申请日：2001-06-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WERNER WOLFGANG ,  HIRLER FRANZ

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor component includes a first connection zone of a first conductivity type for providing a contact at a first side of a semiconductor body and a second connection zone of the first conductivity type for providing a contact at the second side of the semiconductor body. A drift zone adjoins the first connection zone and extends in a vertical direction of the semiconductor body as far as the second side of the semiconductor body. A body zone of a second conductivity type is disposed between the second connection zone and the first connection zone or the drift zone. A control electrode is insulated from the semiconductor body and disposed above the body zone such that the control electrode substantially does not overlap with the drift zone and the second connection zone in a lateral direction. A method for manufacturing a semiconductor component is also provided.

公开(公告)号：DE102005020075A1

公开(公告)日：2006-11-09

申请号：DE102005020075

申请日：2005-04-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HIRLER FRANZ ,  ZUNDEL MARKUS ,  KRUMREY JOACHIM

IPC: H01L21/76 ,  H01L21/336

Abstract: A ditch structure (30) of a first type is formed on the upper surface area (20a) of a semiconductor material section (20). Another ditch structure (40) of a second type is formed outside of the ditch structure (30) on the upper surface area of the semiconductor material section (20). The ditch structures are formed neighboring each other and simultaneously in a common process block.

公开(公告)号：DE102004057235A1

公开(公告)日：2006-06-01

申请号：DE102004057235

申请日：2004-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HIRLER FRANZ ,  WERNER WOLFGANG ,  KRUMREY JOACHIM

IPC: H01L29/78 ,  H01L21/336

Abstract: The transistor has transistor cells with source regions (6), body regions (7), gate electrode (9) and contact holes. The contact holes are designed for contacting the source and body regions, where borders of the holes adjoin at a drift region. Body contact regions are arranged between the body regions and the contact holes. The dimensions and designs of the body regions or body contact regions are selected. An independent claim is also included for a method for manufacturing body regions and accordingly body contact regions in a vertical trench transistor.

公开(公告)号：DE102004052643A1

公开(公告)日：2006-05-04

申请号：DE102004052643

申请日：2004-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HIRLER FRANZ ,  WAHL UWE ,  MEYER THORSTEN ,  RUEB MICHAEL ,  WILLMEROTH ARMIN ,  SCHMITT MARKUS ,  TOLKSDORF CAROLIN ,  SCHAEFFER CARSTEN

IPC: H01L29/78 ,  H01L21/336

Abstract: Lateral trench transistor (200) has a body region (4) inside which a semiconductor region (10) is provided adjoining to it. The semiconductor region is electrically connected with the source contact (12) and its type of endowment corresponds to the type of endowment of body region. An independent claim is also included for a method for manufacturing of endowed semiconductor region.

公开(公告)号：DE102004041892A1

公开(公告)日：2006-03-02

申请号：DE102004041892

申请日：2004-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZUNDEL MARKUS ,  WERNER WOLFGANG ,  HIRLER FRANZ

IPC: H01L21/336 ,  H01L29/739 ,  H01L29/78

Abstract: Trench transistor comprises cell field with several cell field trenches (2) and at least one edge trench (51,52) adjacent to cell field. Sum of widths of all m esa regions (24,25), between last cell field trench and between different edge trenches, at least partly cleaned in blocked state, is specified.Sum of widths lies in region of 0 to 0.7 times of mesa width between two adjacent active cell field trenches, typically 0.5 times. Trench transistor may contain two edge trenches with specified spacing between last cell field trench and first edge trench. INDEPENDENT CLAIM is included for edge structure forming method.

公开(公告)号：DE10210138B4

公开(公告)日：2005-07-21

申请号：DE10210138

申请日：2002-03-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUPP ANDREAS ,  HIRLER FRANZ ,  KOTEK MANFRED ,  HAEBERLEN OLIVER

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78