公开(公告)号：AT550782T

公开(公告)日：2012-04-15

申请号：AT07813250

申请日：2007-07-24

Applicant: IBM

Inventor： CHAKRAVARTI ASHIMA ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/8238

Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.

公开(公告)号：GB2484030A

公开(公告)日：2012-03-28

申请号：GB201122001

申请日：2010-07-13

Applicant: IBM

Inventor： SEKARIC LIDIJA ,  CHIDAMBARRAO DURESETI ,  LIU XIAO HU

IPC: H01L29/775

Abstract: An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tc; and a gate stack of thickness tg in contact with a surface of the channel. Further, the gate stack comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.

公开(公告)号：DE602005024611D1

公开(公告)日：2010-12-16

申请号：DE602005024611

申请日：2005-12-13

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

公开(公告)号：AU2003296359A1

公开(公告)日：2005-07-21

申请号：AU2003296359

申请日：2003-12-08

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DORIS BRUCE B ,  HUANG HSIANG-JEN ,  YANG HAINING ,  BUEHRER FREDERICK WILLIAM

IPC: H01L21/265 ,  H01L21/324 ,  H01L21/336 ,  H01L21/425 ,  H01L21/8238 ,  H01L27/01 ,  H01L29/10 ,  H01L29/167 ,  H01L29/76

Abstract: A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.

公开(公告)号：DE10361272A1

公开(公告)日：2004-08-05

申请号：DE10361272

申请日：2003-12-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  VAN ROIJEN RAYMOND

IPC: H01L21/8242

Abstract: A DRAM cell with a vertical transistor forms a buried strap outdiffusion with reduced lateral extent by shifting high temperature steps that affect the thermal budget before the initial buried strap diffusion. The gate conductor is formed in two steps, with poly sidewalls being put down above a sacrificial Trench top oxide to form a self-aligned poly-gate insulator structure before the formation of the LDD extension.

公开(公告)号：DE69228792D1

公开(公告)日：1999-05-06

申请号：DE69228792

申请日：1992-11-19

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  NIJHUIS ROLF HENK ,  SRINIVASAN GURUMAKONDA RAMASAM ,  MURLEY PHILIP CLYDE ,  ROBBINS GORDON JAY ,  WALTERS TIMOTHY LAWTON

IPC: H01L23/522 ,  H01L21/60 ,  H01L21/768 ,  H01L23/49 ,  H01L23/556

公开(公告)号：GB2484030B

公开(公告)日：2013-10-02

申请号：GB201122001

申请日：2010-07-13

Applicant: IBM

Inventor： SEKARIC LIDIJA ,  CHIDAMBARRAO DURESETI ,  LIU XIAO HU

IPC: H01L29/775

公开(公告)号：DE602004032035D1

公开(公告)日：2011-05-12

申请号：DE602004032035

申请日：2004-08-04

Applicant: IBM

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN L ,  YANG HAINING S

IPC: H01L31/0328 ,  H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

公开(公告)号：DE602004025135D1

公开(公告)日：2010-03-04

申请号：DE602004025135

申请日：2004-06-30

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  GLUSCHENKOV OLEG G

IPC: H01L21/00 ,  H01L21/311 ,  H01L21/76 ,  H01L21/82 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L29/24 ,  H01L29/808

公开(公告)号：DE602006011501D1

公开(公告)日：2010-02-11

申请号：DE602006011501

申请日：2006-10-03

Applicant: IBM

Inventor： CHIDAMBARRAO DURESETI

IPC: H01L21/762

Abstract: A semiconductor structure and its method of fabrication utilize a semiconductor substrate having an active region mesa surrounded by an isolation trench. A first isolation region having a first stress is located in the isolation trench. A second isolation region having a second stress different than the first stress is also located in the isolation trench. The first isolation region and the second isolation region are sized and positioned to rotationally shear stress the active region mesa.