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公开(公告)号:GB2494600A
公开(公告)日:2013-03-13
申请号:GB201300265
申请日:2011-06-08
Applicant: IBM
Inventor: DANG DINH , DOAN THAI , DUNBAR GEORGE A , HE ZHONG-XIANG , HERRIN RUSSELL T , JAHNES CHRISTOPHER V , MALING JEFFREY C , MURPHY WILLIAM J , STAMPER ANTHONY K , TWOMBLY JOHN G , WHITE ERIC J
Abstract: Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity (60a, 60b) having a planar surface using a reverse damascene process.
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公开(公告)号:GB2494360A
公开(公告)日:2013-03-06
申请号:GB201300091
申请日:2011-06-08
Applicant: IBM
Inventor: DUNBAR GEORGE A , HE ZHONG-XIANG , MURPHY WILLIAM J , STAMPER ANTHONY K , MALING JEFFREY
IPC: B81C1/00
Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower wiring layer on a substrate. The method further includes forming a plurality of discrete wires (14) from the lower wiring layer. The method further includes forming an electrode beam (38) over the plurality of discrete wires. The at least one of the forming of the electrode beam and the plurality of discrete wires are formed with a layout which minimizes hillocks and triple points in subsequent silicon deposition (50).
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83.
公开(公告)号:MY134796A
公开(公告)日:2007-12-31
申请号:MYPI20030029
申请日:2003-01-06
Applicant: IBM , INFINEON TECHNOLOGIES CORP
Inventor: CHEN TZE-CHIANG , WANG YUN YU , KALTALIOGLU ERDEM , ENGEL BRETT H , FITZSIMMONS JOHN A , KANE TERENCE , LUSTIG NAFTALI E , MCDONALD ANN , MCGAHAY VINCENT , SEO SOON-CHEON , STAMPER ANTHONY K
IPC: H01L21/44 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532
Abstract: AN ADVANCED BACK-END-OF-LINE (BEOL) METALLIZATION STRUCTURE IS DISCLOSED. THE STRUCTURE INCLUDES A BILAYER DIFFUSION BARRIER OR CAP, WHERE THE FIRST CAP LAYER (116, 123) IS FORMED OF A DIELECTRIC MATERIAL PREFERABLY DEPOSITED BY A HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION (HDP CVD) PROCESS, AND THE SECOND CAP LAYER (117, 124) IS FORMED OF A DIELECTRIC MATERIAL PREFERABLY DEPOSITED BY A PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION (PE CVD) PROCESS. A METHOD FOR FORMING THE BEOL METALLIZATION STRUCTURE IS ALSO DISCLOSED. THE INVENTION IS PARTICULARLY USEFUL IN INTERCONNECT STRUCTURES COMPRISING LOW-K DIELECTRIC MATERIAL FOR THE INTER-LAYER DIELECTRIC (ILD) AND COPPER FOR THE CONDUCTORS.
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公开(公告)号:MY127478A
公开(公告)日:2006-12-29
申请号:MYPI9704675
申请日:1997-10-06
Applicant: IBM
Inventor: COONEY EDWARD C , LEE HYUN K , MCDEVITT THOMAS L , STAMPER ANTHONY K
IPC: H05K1/00 , H01L21/285 , H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522
Abstract: METHOD OF IMPROVING THE RESISTANCE OF A METAL AGAINST DEGRADATION FROM EXPOSURE TO FLUORINE RELEASED FROM A FLUORINE- CONTAINING MATERIAL BY FORMING A FLUORINE-BARRIER LAYER BETWEEN THE INSULATOR MATERIAL AND THE METAL. THE INVENTION IS ESPECIALLY USEFUL IN IMPROVING CORROSION AND POISONING RESISTANCE OF METALLURGY, SUCH AS ALUMINUM METALLURGY, IN SEMICONDUCTOR STRUCTURES. THE INVENTION ALSO COVERS INTEGRATED CIRCUIT STRUCTURES MADE BY THIS METHOD. (FIG. 2F)
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公开(公告)号:GB2366077B
公开(公告)日:2005-01-19
申请号:GB0105197
申请日:2001-03-02
Applicant: IBM
Inventor: GEFFKEN ROBERT M , STAMPER ANTHONY K
IPC: H01L21/02 , H01L21/768 , H01L21/3205 , H01L21/822 , H01L23/522 , H01L27/04 , H01L29/92
Abstract: A metal capacitor formed as part of metal dual damascene process in the BEOL, of a wafer. A lower plate (27) of the capacitor is sandwiched between an insulating layer (25) and a dielectric layer (29). The insulating layer on an opposite side abuts a layer of metalization (23, 24) and the dielectric layer separates the lower plate of the capacitor from an upper plate (59) of the capacitor. A portion (27A) of the lower plate projects into a via (37) adjacent to it that is filled with copper (63). The via projects up to a common surface with the upper plate but is electrically isolated form the upper plate. The via also extends down to the layer of metalization.
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公开(公告)号:DE102012221818B4
公开(公告)日:2016-07-21
申请号:DE102012221818
申请日:2012-11-29
Applicant: IBM
Inventor: CZABAJ BRAIN M , DEMUYNCK DAVID A , STAMPER ANTHONY K
Abstract: Verfahren, aufweisend: – Bilden einer ersten Metallschicht (28) auf einer mindestens ersten Isolatorschicht (24), die ein darunter liegendes erstes Opfermaterial (18) bedeckt, das auf einem Substrat (10) gebildet wurde; – Bilden einer zweiten Isolatorschicht (30) auf der ersten Metallschicht (28); – Bilden einer zweiten Metallschicht (32) auf der zweiten Isolatorschicht (30); – Bilden einer dritten Isolatorschicht (34) auf der zweiten Metallschicht (32); – Bilden einer Maske (36) auf der dritten Isolatorschicht (34) zum Schutz von Teilen der dritten Isolatorschicht (34), der zweiten Metallschicht (32), der zweiten Isolatorschicht (30), der ersten Isolatorschicht (24) und der ersten Metallschicht (28), wobei eine Öffnung (38) in der Maske teilweise das darunter liegende erste Opfermaterial (18) überlappt; – Entfernen freiliegender Teile der ersten Isolatorschicht (24), der zweiten Isolatorschicht (30), der dritten Isolatorschicht (34), der ersten Metallschicht (28) und der zweiten Metallschicht (32) in einem einzigen Entfernungsprozess zum Bilden einer Balkenstruktur (45), umfassend verbleibende Bereiche der ersten Isolatorschicht (24), der zweiten Isolatorschicht (30), der dritten Isolatorschicht (34), der ersten Metallschicht (28) und der zweiten Metallschicht (32), und zum Freilegen des überlappten Teils des darunter liegenden ersten Opfermaterials (18); – Bilden eines zweiten Opfermaterials (44) über der Balkenstruktur (45) und in Kontakt mit dem freiliegenden Teil des darunter liegenden ersten Opfermaterials (18); – Bereitstellen einer Decklage (46) auf dem zweiten Opfermaterial (44); und – Austreiben des zweiten Opfermaterials (44) und des darunter liegenden ersten Opfermaterials (18) durch die Decklage (46), um eine obere (50a) und untere (50b) Kammer mit einer diese verbindenden Durchkontaktierung (50c) um die Balkenstruktur (45) zu bilden.
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公开(公告)号:GB2505825B
公开(公告)日:2015-06-10
申请号:GB201322198
申请日:2012-06-01
Applicant: IBM
Inventor: JAHNES CHRISTOPHER V , STAMPER ANTHONY K
IPC: B81B3/00
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公开(公告)号:GB2494600B
公开(公告)日:2015-02-25
申请号:GB201300265
申请日:2011-06-08
Applicant: IBM
Inventor: DANG DINH , DOAN THAI , DUNBAR GEORGE A , HE ZHONG-XIANG , HERRIN RUSSELL T , JAHNES CHRISTOPHER V , MALING JEFFREY C , MURPHY WILLIAM J , STAMPER ANTHONY K , TWOMBLY JOHN G , WHITE ERIC J
Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes patterning a wiring layer to form at least one fixed plate and forming a sacrificial material on the wiring layer. The method further includes forming an insulator layer of one or more films over the at least one fixed plate and exposed portions of an underlying substrate to prevent formation of a reaction product between the wiring layer and a sacrificial material. The method further includes forming at least one MEMS beam that is moveable over the at least one fixed plate. The method further includes venting or stripping of the sacrificial material to form at least a first cavity.
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公开(公告)号:GB2494824B
公开(公告)日:2015-01-14
申请号:GB201300040
申请日:2011-06-15
Applicant: IBM
Inventor: STAMPER ANTHONY K , JAHNES CHRISTOPHER VINCENT
Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes patterning a wiring layer to form at least one fixed plate and forming a sacrificial material on the wiring layer. The method further includes forming an insulator layer of one or more films over the at least one fixed plate and exposed portions of an underlying substrate to prevent formation of a reaction product between the wiring layer and a sacrificial material. The method further includes forming at least one MEMS beam that is moveable over the at least one fixed plate. The method further includes venting or stripping of the sacrificial material to form at least a first cavity.
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90.
公开(公告)号:GB2509680A
公开(公告)日:2014-07-09
申请号:GB201408505
申请日:2012-08-14
Applicant: IBM
Inventor: HARAME DAVID L , STAMPER ANTHONY K
Abstract: Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam (18) from a silicon layer (14) on an insulator (12). The method further includes providing a coating of insulator material (22) over the single crystalline beam. The method further includes forming a via (34a) through the insulator material exposing a wafer (10) underlying the insulator. The insulator material remains over the single crystalline beam. The method further includes providing a sacrificial material (36) in the via and over the insulator material. The method further includes providing a lid (38) on the sacrificial material. The method further includes venting, through the lid, the sacrificial material and a portion of the wafer under the single crystalline beam to form an upper cavity (42a) above the single crystalline beam and a lower cavity (42b) in the wafer, below the single crystalline beam.
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