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    Electronic structures having a joining geometry providing reduced capacitive loading
    162.
    发明授权
    Electronic structures having a joining geometry providing reduced capacitive loading 失效
    具有提供降低的电容负载的接合几何形状的电子结构

    公开(公告)号：US5471090A

    公开(公告)日：1995-11-28

    申请号：US28023

    申请日：1993-03-08

    Applicant: Alina Deutsch ,  David A. Lewis ,  Chandrasekhar Narayan ,  Anthony L. Plachy

    Inventor： Alina Deutsch ,  David A. Lewis ,  Chandrasekhar Narayan ,  Anthony L. Plachy

    IPC: H01L23/12 ,  H01L23/538 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H01L23/48 ,  H01L29/44

    CPC classification number: H01L23/5385 ,  H05K1/0216 ,  H05K1/111 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0289 ,  H05K2201/0373 ,  H05K2201/0792 ,  H05K2201/0939 ,  H05K2201/09427 ,  H05K2201/10719 ,  H05K2203/061 ,  H05K3/4614 ,  Y02P70/611

    Abstract: Electrical interconnection structures are described. The electrical interconnection structures are formed by electrically interconnecting in a stack a plurality of discrete substrates. By using a plurality of discrete substrates, a multilayer dielectric/electrical conductor structure can be fabricated from individual discrete substrates each of which can be tested prior to forming a composite stack so that defects in each discrete substrate can be eliminated before inclusion into the stack. Electrical interconnection between adjacent substrate is provided by an array of contact locations on each surface of the adjacent substrates. Corresponding contacts on adjacent substrates are adapted for mutual electrical engagement. Adjacent contact locations can be thermocompression bonded. To reduce the parasitic capacitance and coupled noise between the contact pads and the electrical conductors within the interior of each discrete substrate, the contact pads on each substrate have elongated shape. The elongated contact pads or lattice pads on adjacent substrates are nonparallel and preferably orthogonal so that the corresponding pads of adjacent substrates electrically interconnect an intersecting area which varies in location along the elongated contact pads as the placement of the adjacent substrates varies in the manufacture.

    Abstract translation: 描述电互连结构。 电互连结构通过在堆叠中电互连而形成，多个分立的衬底。 通过使用多个分立的衬底，多层电介质/电导体结构可以由单独的离散衬底制成，每个离散衬底可以在形成复合堆叠之前进行测试，以便在包含在堆叠中之前可以消除每个离散衬底中的缺陷。 相邻基板之间的电气互连通过相邻基板的每个表面上的接触位置阵列来提供。 相邻基板上的相应触点适于相互电接合。 相邻的接触位置可以热压粘合。 为了减小接触焊盘和每个离散衬底内部的电导体之间的寄生电容和耦合噪声，每个衬底上的接触焊盘具有细长形状。 相邻基板上的细长接触焊盘或网格焊盘是不平行的并且优选地是正交的，使得相邻衬底的相应焊盘在制造中随着相邻衬底的布置变化而沿着细长的接触焊盘将位置变化的相交区域电连接。

    Surge protector
    163.
    发明授权
    Surge protector 失效
    浪涌保护器

    公开(公告)号：US5303116A

    公开(公告)日：1994-04-12

    申请号：US760740

    申请日：1991-09-16

    Applicant: Glenn F. Grotz

    Inventor： Glenn F. Grotz

    IPC: H01R13/66 ,  H02H9/04 ,  H05K1/02 ,  H05K1/18 ,  H02H3/20 ,  H01R9/09

    CPC classification number: H01R13/6666 ,  H02H9/044 ,  H05K1/0216 ,  H05K1/0254 ,  H05K1/181 ,  H05K2201/0715 ,  H05K2201/0792 ,  H05K2201/093

    Abstract: A surge protector or transient suppressors for AC power lines having its components mounted on a circuit board. The metalization of the board are configured to present as large a surface area as possible, given the topology of the board, to the flow of current. A return conductor is placed on the opposite side of the board with a large surface area corresponding to the first conductor. The magnetic field between the two conductors is substantially cancelled. This configuration reduces the magnetic field intensities associated with the flow of current, thereby reducing self-inductance.

    Abstract translation: 交流电源线的浪涌保护器或瞬态抑制器，其组件安装在电路板上。 电路板的金属化被配置为根据电路板的拓扑结构，呈现尽可能大的表面积，达到电流。 返回导体放置在板的相对侧上，具有对应于第一导体的大表面积。 基本上消除了两个导体之间的磁场。 该配置减小了与电流流动相关联的磁场强度，从而降低了自感。

    Circuit board having printed thereon conductive patterns to be connected with input and output lead wires of acoustic surface wave filter element
    164.
    发明授权
    Circuit board having printed thereon conductive patterns to be connected with input and output lead wires of acoustic surface wave filter element 失效
    印刷有导电图案的电路板，与声表面波滤波器元件的输入和输出引线连接

    公开(公告)号：US4250473A

    公开(公告)日：1981-02-10

    申请号：US886607

    申请日：1978-03-14

    Applicant: Tomoji Gemba

    Inventor： Tomoji Gemba

    IPC: H01R12/00 ,  H03H9/145 ,  H05K1/02 ,  H05K3/34 ,  H05K9/00 ,  H03H9/04 ,  H01L41/04 ,  H03H9/26 ,  H03H9/32

    CPC classification number: H05K1/0243 ,  H03H9/14597 ,  H05K9/0039 ,  H05K1/0219 ,  H05K2201/0792 ,  H05K2201/09336 ,  H05K2201/10083 ,  H05K2201/10969 ,  H05K3/3447

    Abstract: An acoustic surface wave filter element provided with two input and two output pins connected with the input and the output interdigital electrodes, respectively and an earth pin connected with a filter element shield casing is disposed on one surface of a circuit board, with the five pins extending through corresponding through holes in the circuit board to the other surface of the circuit board on which the pins are connected with corresponding conductive circuit patterns of the circuit board. The circuit patterns include a first signal pattern to be connected with one of the input pins, a first earth pattern connected with the other of the input pins, a second and a third signal pattern connected with one and another of the output pins, and a second earth pattern connected with the earth pin of the filter element. The first and the second signal pattern have end portions opposedly positioned to each other, and an earth pattern portion is positioned between the opposed end portions of the first and the second signal pattern to connect the first and the second earth pattern with each other. Portions of the patterns positioned beneath the filter element are arrayed symmetrically about an axis lying on the center of the terminal of the end portion of the first signal pattern and external between the second and third signal patterns.

    Abstract translation: 一个声表面波滤波器元件分别设置有与输入和输出叉指电极相连的两个输入和两个输出引脚，一个与滤波器元件屏蔽壳连接的接地引脚设置在电路板的一个表面上，其中五个引脚 延伸通过电路板中相应的通孔延伸到电路板的与电路板的相应导电电路图形连接的另一个表面。 电路图案包括要与输入引脚之一连接的第一信号图案，与另一个输入引脚连接的第一接地图案​​，与一个和另一个输出引脚连接的第二和第三信号图案，以及 第二接地图与过滤元件的接地销连接。 第一和第二信号图案具有彼此相对定位的端部，并且接地图案部分位于第一和第二信号图案的相对端部之间，以将第一和第二接地图彼此连接。 位于过滤器元件下方的图案的部分围绕位于第一信号图案的端部的端子的中心上的轴对称地排列，并且在第二和第三信号图案之间是外部的。

    INDUCTOR AND PRINTED CIRCUIT BOARD
    168.
    发明申请
    INDUCTOR AND PRINTED CIRCUIT BOARD 审中-公开
    电感和印刷电路板

    公开(公告)号：US20170018351A1

    公开(公告)日：2017-01-19

    申请号：US15208882

    申请日：2016-07-13

    Applicant: Taiyo Yuden Co., Ltd.

    Inventor： Masuo YATABE ,  Kozue IMAIZUMI ,  Noriyuki MABUCHI ,  Kazuhiko OYAMA

    IPC: H01F27/29 ,  H05K1/18 ,  H01F27/28

    CPC classification number: H01F27/292 ,  H01F27/2804 ,  H01F2027/2809 ,  H05K3/3431 ,  H05K2201/0792 ,  H05K2201/1003 ,  H05K2201/10636 ,  H05K2203/048 ,  Y02P70/611 ,  Y02P70/613

    Abstract: One object is to compensate the reduction of the Q value due to reduction of core sectional area of a coil of an inductor, and the reduction of positional accuracy and adhesive strength of components mounted on a printed circuit board due to reduction of area of external electrodes, both caused by downsizing of component sizes. An inductor is provided which includes: a coil formed in an insulator and having one end and the other end thereof formed in a direction away from a mounting surface; and lead-out portions connected to the coil at positions more distant from the mounting surface than a portion of the coil closest to the mounting surface.

    Abstract translation: 一个目的是为了补偿由于电感器线圈的芯截面积的减小引起的Q值的降低，以及由于外部电极的面积的减小而安装在印刷电路板上的部件的位置精度和粘合强度的降低 都是由于组件尺寸的缩小造成的。 提供一种电感器，其包括：形成在绝缘体中的线圈，并且其一端和另一端沿远离安装表面的方向形成; 以及与最靠近安装表面的线圈的一部分相比，在与安装表面更远的位置连接到线圈的引出部分。

    Printed circuit board
    169.
    发明授权
    Printed circuit board 有权
    印刷电路板

    公开(公告)号：US09538634B2

    公开(公告)日：2017-01-03

    申请号：US13960469

    申请日：2013-08-06

    Applicant: CANON KABUSHIKI KAISHA

    Inventor： Hiroyuki Yamaguchi

    IPC: H05K1/18 ,  H05K1/02

    CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0245 ,  H05K2201/0792 ,  H05K2201/09272 ,  H05K2201/09418 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611

    Abstract: A printed circuit board (e.g., 103) includes capacitor elements (e.g., 121 and 122). The capacitor element (e.g., 121) returns a common mode current included in a signal output from a signal output terminal (e.g., 111) of a semiconductor element (e.g., 102), to a ground terminal (e.g., 113) of the semiconductor element (e.g., 102). The capacitor element (e.g., 122) returns a common mode current included in a signal output from a signal output terminal (e.g., 112) of the semiconductor element (e.g., 102), to the ground terminal (e.g., 113) of the semiconductor element (e.g., 102). The capacitor elements (e.g., 121 and 122) are arranged such that the mutual inductance between a parasitic inductance of the capacitor element (e.g., 121) and a parasitic inductance of the capacitor element (e.g., 122) for the common mode currents is a negative value. Accordingly, the effective inductances of the first and second capacitor elements for the common mode currents are reduced, which suppresses radiation noise.

    Abstract translation: 印刷电路板（例如，103）包括电容元件（例如121和122）。 电容器元件（例如，121）将从半导体元件（例如，102）的信号输出端子（例如，111）输出的信号中包含的共模电流返回到半导体的接地端子（例如，113） 元素（例如，102）。 电容器元件（例如，122）将包括在从半导体元件（例如，102）的信号输出端子（例如，112）输出的信号中的共模电流返回到半导体的接地端子（例如，113） 元素（例如，102）。 电容器元件（例如，121和122）被布置成使得电容器元件（例如，121）的寄生电感与用于共模电流的电容器元件（例如，122）的寄生电感之间的互感是 负值。 因此，减小了用于共模电流的第一和第二电容器元件的有效电感，这抑制了辐射噪声。

    Substrate Material Favoring Via Hole Electroplating
    170.
    发明申请
    Substrate Material Favoring Via Hole Electroplating 审中-公开
    基板材料优选通孔电镀

    公开(公告)号：US20160323998A1

    公开(公告)日：2016-11-03

    申请号：US14698635

    申请日：2015-04-28

    Applicant: Fameson Technology Co., Ltd.

    Inventor： Rong-Seng CHANG

    IPC: H05K1/03

    CPC classification number: H05K1/0373 ,  H05K3/424 ,  H05K2201/012 ,  H05K2201/0133 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0162 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/0792 ,  H05K2201/093

    Abstract: The present invention proposes substrate material favoring via hole electroplating to overcome the conventional problem that the polymer-based printed circuit board is hard to conduct electricity and likely to have poor electroplating quality. The present invention adds a conductive material to a polymeric material and controls the proportions and structure thereof to form a substrate material so as to improve the affinity of the substrate material to the metal electroplated inside the via hole with the resistance of the substrate material remaining in an allowable range. Thereby is increased yield and efficiency and saved time and cost in fabricating printed circuit boards. Further, the present invention reduces the proportion of the polymeric material with the mechanical strength remaining in an allowable range so as to decrease the overall expansion rate and obtain a fire-proof effect. Therefore, the substrate material can be used to fabricate precision products.

    Abstract translation: 本发明提出了有利于通孔电镀的基板材料，以克服聚合物基印刷电路板难以导电并且可能具有差的电镀质量的常规问题。 本发明将导电材料添加到聚合物材料中并控制其比例和结构以形成基底材料，以便提高衬底材料对通孔内部电镀的金属的亲和性，其中衬底材料的电阻保持在 允许范围。 从而提高了产量和效率，并节省了制造印刷电路板的时间和成本。 此外，本发明将机械强度保持在容许范围内的聚合物材料的比例降低，从而降低整体膨胀率并获得防火效果。 因此，基板材料可用于制造精密产品。

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