公开(公告)号：US20180228061A1

公开(公告)日：2018-08-09

申请号：US15943338

申请日：2018-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Sik PARK ,  Seung-Ki CHOI ,  Joon HEO ,  Hyun-Ju HONG

IPC: H05K9/00 ,  H05K5/00 ,  H05K1/02

CPC classification number: H05K9/002 ,  H01L2224/16225 ,  H05K1/0218 ,  H05K1/0259 ,  H05K5/0004 ,  H05K5/0017 ,  H05K9/0024 ,  H05K9/0039 ,  H05K2201/0919 ,  H05K2201/09354 ,  H05K2201/10371

Abstract: An electronic device is provided that includes a PCB including a first surface, a second surface, and a side surface; an electronic component arranged on the first surface, adjacent to a portion of the side surface; a shield structure including a cap that covers the electronic component and a sidewall extending from a periphery of the cap toward the first surface of the PCB, wherein the sidewall extends in a first direction that is non-parallel to the first surface of the PCB; a first conductive structure that is formed on a portion of the side surface of the PCB; and a second conductive structure that is formed on a portion of the first surface to be connected to the first conductive structure. The sidewall contacts with the first surface of the PCB and overlaps with the second conductive structure, when viewed from above the first surface of the PCB.

公开(公告)号：US09698109B2

公开(公告)日：2017-07-04

申请号：US14615956

申请日：2015-02-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takayuki Tsukizawa ,  Jun Adachi ,  Takayuki Imada ,  Takahiro Sumi

IPC: H01L23/60 ,  H01T1/22 ,  H01T4/10 ,  H05K1/02 ,  H01B1/14 ,  H05F3/04 ,  H01B1/16 ,  H01B1/18 ,  H05K3/46 ,  H01L23/498

CPC classification number: H01L23/60 ,  H01B1/14 ,  H01B1/16 ,  H01B1/18 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/0002 ,  H01T1/22 ,  H01T4/10 ,  H05F3/04 ,  H05K1/026 ,  H05K3/4697 ,  H05K2201/09063 ,  H05K2201/0919 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An ESD protection device 1 has a ceramic insulating material 10, first and second discharge electrodes 21 and 22, and a discharge-assisting section 51. The first and second discharge electrodes 21 and 22 are disposed somewhere of the ceramic insulating material 10. The discharge-assisting section 51 is located between the distal end portion of the first discharge electrode 21 and the distal end portion of the second discharge electrode 22. The discharge-assisting section 51 is an electrode configured to reduce the discharge starting voltage between the first discharge electrode 21 and the second discharge electrode 22. The discharge-assisting section 51 is made from a sintered body containing conductive particles and at least one of semiconductor particles and insulating particles. The first and second discharge electrodes contain at least one of the semiconductor material constituting the semiconductor particles and the insulating material constituting the insulating particles.

公开(公告)号：US20170186533A9

公开(公告)日：2017-06-29

申请号：US14531079

申请日：2014-11-03

Applicant: James Jen-Ho Wang

Inventor： James Jen-Ho Wang

IPC: H01F41/02 ,  H05K1/18 ,  H05B33/08

CPC classification number: H01F41/0206 ,  H01F17/0013 ,  H01F41/046 ,  H01F2017/006 ,  H01F2017/0066 ,  H05B33/0803 ,  H05B33/0821 ,  H05B33/0845 ,  H05K1/0209 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/028 ,  H05K1/0283 ,  H05K1/165 ,  H05K1/183 ,  H05K1/189 ,  H05K3/0005 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/0097 ,  H05K3/281 ,  H05K3/427 ,  H05K3/4697 ,  H05K2201/056 ,  H05K2201/086 ,  H05K2201/0919 ,  H05K2201/09672 ,  H05K2201/09709 ,  H05K2201/09845 ,  H05K2203/0126 ,  H05K2203/0384 ,  H05K2203/0571 ,  H05K2203/063 ,  H05K2203/1545

Abstract: An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.

公开(公告)号：US20170148713A1

公开(公告)日：2017-05-25

申请号：US15369443

申请日：2016-12-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Atsuko IIDA ,  Tadahiro Sasaki ,  Nobuto Managaki ,  Yutaka Onozuka ,  Hiroshi Yamada

IPC: H01L23/498 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L23/04 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/60 ,  H01L23/66 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0657 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/24195 ,  H01L2224/82106 ,  H01L2224/95 ,  H01L2224/96 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2924/15788 ,  H01L2924/19105 ,  H01P1/20 ,  H01P1/2005 ,  H01P1/202 ,  H01P5/028 ,  H05K1/117 ,  H05K3/403 ,  H05K2201/0919 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/0231 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079

Abstract: A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.

公开(公告)号：US09451694B2

公开(公告)日：2016-09-20

申请号：US14663447

申请日：2015-03-19

Applicant: IBIS Innotech Inc.

Inventor： Chih-Kung Huang ,  Wei-Jen Lai ,  Wen-Chun Liu

IPC: H05K7/10 ,  H05K7/12 ,  H05K1/03 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46 ,  H05K1/11 ,  H05K3/00 ,  H05K3/10

CPC classification number: H05K1/0373 ,  H01L21/568 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L25/04 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/96 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/1715 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19105 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: A package structure includes a selective-electroplating epoxy compound, a first patterned circuit layer, second patterned circuit layers, metal studs, contact pads and conductive vias. The selective-electroplating epoxy compound includes cavities, a first surface and a second surface. The cavities disposed on the first surface in array arrangement. The selective-electroplating epoxy compound is formed by combining non-conductive metal complex. The metal studs are disposed in the cavities respectively and protruded from the first surface. The first patterned circuit layer is directly disposed on the first surface. The selective-electroplating epoxy compound exposes a top surface of the patterned circuit layer. The top surface is lower than or coplanar with the first surface. The second patterned circuit layers are directly disposed on the second surface. The conductive vias are disposed at the selective-electroplating epoxy compound to electrically connect the second patterned circuit layers to the corresponding metal studs.

Abstract translation: 封装结构包括选择性电镀环氧化合物，第一图案化电路层，第二图案化电路层，金属柱，接触焊盘和导电通孔。 选择性电镀环氧化合物包括空腔，第一表面和第二表面。 排列在第一表面上的空腔。 选择性电镀环氧化合物通过组合非导电金属络合物形成。 金属螺柱分别设置在空腔中并从第一表面突出。 第一图案化电路层直接设置在第一表面上。 选择性电镀环氧化合物暴露图案化电路层的顶表面。 顶面低于或与第一表面共面。 第二图案化电路层直接设置在第二表面上。 导电通孔设置在选择性电镀环氧化合物处，以将第二图案化电路层电连接到相应的金属螺柱。

公开(公告)号：US20160157352A1

公开(公告)日：2016-06-02

申请号：US15013128

申请日：2016-02-02

Applicant: SunASIC Technologies, Inc.

Inventor： Chi-Chou LIN

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/182 ,  B42D25/313 ,  G06K9/0002 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H05K1/115 ,  H05K1/183 ,  H05K3/0044 ,  H05K3/4046 ,  H05K3/421 ,  H05K3/4623 ,  H05K3/4697 ,  H05K2201/0187 ,  H05K2201/0919 ,  H05K2201/09845 ,  H05K2201/10106 ,  H05K2201/10121 ,  H05K2201/10287 ,  H05K2203/0228 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/4913

Abstract: A printed circuit board having an electronic component embedded is disclosed. The printed circuit board has four electrically conductive layers and three core layers formed interleavedly. By properly removing a portion of the printed circuit board, the electronic component can be exposed. It has advantages that the exposed electronic component can be a CCD, CMOS or module. When the devices mentioned are embedded in the printed circuit board, one part of them can be exposed from the printed circuit board for normal functions. The overall thickness of the printed circuit board assembly can be minimized to meet the trend of compact design of electronic products.

Abstract translation: 公开了一种嵌有电子部件的印刷电路板。 印刷电路板具有交错形成的四个导电层和三个核心层。 通过适当地去除印刷电路板的一部分，可以暴露电子部件。 它具有暴露的电子部件可以是CCD，CMOS或模块的优点。 当所提到的装置嵌入印刷电路板时，其一部分可以从印刷电路板露出以用于正常功能。 可以将印刷电路板组件的总体厚度最小化以满足电子产品的紧凑设计的趋势。

公开(公告)号：US09318820B2

公开(公告)日：2016-04-19

申请号：US14227574

申请日：2014-03-27

Applicant: Molex, LLC

Inventor： Toshihiro Niitsu ,  Motohisa Haga

IPC: H01R13/62 ,  H01R12/52 ,  H01R12/79 ,  H05K1/11 ,  H05K3/36 ,  H05K3/32 ,  H05K3/40

CPC classification number: H01R12/523 ,  H01R12/79 ,  H05K1/117 ,  H05K3/326 ,  H05K3/365 ,  H05K3/368 ,  H05K3/403 ,  H05K2201/0367 ,  H05K2201/09163 ,  H05K2201/0919 ,  H05K2201/09863 ,  H05K2201/10303 ,  H05K2201/10386

Abstract: A connector for a multilayered board to connect a flat cable to a middle layer of a multilayered board while minimizing the impact due to variations in the dimensional precision and strength of multilayered boards and/or preventing deformation of the multilayered board and improving contact stability. The connector includes a board-side connecting portion and a cable-side connecting portion. The board-side connecting portion includes a column-shaped terminal, and the cable-side connecting portion includes flat terminals. The column-shaped terminal protrudes from the middle layer of the multilayered board in the thickness direction. The flat terminals include resilient contact portions, contacting a side surface portion of the column-shaped terminal from the width direction of the insertion slot in response to insertion of the cable-side connecting portion into the insertion slot.

Abstract translation: 一种用于多层板的连接器，用于将扁平电缆连接到多层板的中间层，同时最小化由于多层板的尺寸精度和强度的变化引起的冲击和/或防止多层板的变形并提高接触稳定性。 连接器包括板侧连接部和电缆侧连接部。 板侧连接部包括柱状端子，电缆侧连接部包括扁平端子。 柱状端子在厚度方向从多层板的中间层突出。 扁平端子包括弹性接触部分，其响应于电缆侧连接部分插入到插槽中而从插入槽的宽度方向接触到柱状端子的侧表面部分。

公开(公告)号：US09295158B2

公开(公告)日：2016-03-22

申请号：US14071724

申请日：2013-11-05

Applicant: SunASIC Technologies, Inc.

Inventor： Chi-Chou Lin

IPC: H01K3/10 ,  H05K1/18 ,  B42D25/313 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/182 ,  B42D25/313 ,  G06K9/0002 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H05K1/115 ,  H05K1/183 ,  H05K3/0044 ,  H05K3/4046 ,  H05K3/421 ,  H05K3/4623 ,  H05K3/4697 ,  H05K2201/0187 ,  H05K2201/0919 ,  H05K2201/09845 ,  H05K2201/10106 ,  H05K2201/10121 ,  H05K2201/10287 ,  H05K2203/0228 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/4913

Abstract: A printed circuit board having an electronic component embedded and a method making the same are disclosed. The printed circuit board has four electrically conductive layers and three core layers formed interleavedly. By properly removing a portion of the printed circuit board, the electronic component can be exposed. It has advantages that the exposed electronic component can be a CCD, CMOS or module. When the devices mentioned are embedded in the printed circuit board, one part of them can be exposed from the printed circuit board for normal functions. The overall thickness of the printed circuit board assembly can be minimized to meet the trend of compact design of electronic products.

Abstract translation: 公开了一种具有嵌入式电子元件的印刷电路板及其制造方法。 印刷电路板具有交错形成的四个导电层和三个核心层。 通过适当地去除印刷电路板的一部分，可以暴露电子部件。 它具有暴露的电子部件可以是CCD，CMOS或模块的优点。 当所提到的装置嵌入印刷电路板时，其一部分可以从印刷电路板露出以用于正常功能。 可以将印刷电路板组件的总体厚度最小化以满足电子产品的紧凑设计的趋势。

公开(公告)号：US20160064793A1

公开(公告)日：2016-03-03

申请号：US14938881

申请日：2015-11-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kuniaki YOSUI

IPC: H01P3/08

CPC classification number: H01P3/08 ,  H01L23/12 ,  H01L23/66 ,  H01L2924/0002 ,  H01P3/085 ,  H01P5/028 ,  H05K1/0251 ,  H05K1/0253 ,  H05K1/118 ,  H05K1/147 ,  H05K2201/0191 ,  H05K2201/058 ,  H05K2201/0919 ,  H05K2201/09445 ,  H05K2201/09727 ,  H05K2201/09845 ,  H05K2201/10189 ,  H01L2924/00

Abstract: A signal transmission cable as a signal transmission component includes a laminate including a first thin portion on one of the opposite ends in a first direction and a second thin portion on the other end in the first direction. A portion between the first thin portion and the second thin portion in the laminate is a main line portion. The thickness of the first and second thin portions is thinner than the thickness of the main line portion. The surface on one end in the thickness direction of the laminate defined by the main line portion and the first and second thin portions is a continuous flat surface. A connector for external connection is arranged on the surfaces of the first and second thin portions, on the sides in which each of the thin portions and the main line portion have a difference in level.

Abstract translation: 作为信号传输部件的信号传输电缆包括层压体，其包括在第一方向上的相对端中的一个上的第一薄部分和在第一方向上的另一端的第二薄部分。 层叠体中的第一薄部分和第二薄部分之间的部分是主线部分。 第一和第二薄部分的厚度比主线部分的厚度薄。 由主线部分和第一和第二薄部分限定的层压体的厚度方向上的一端的表面是连续的平坦表面。 用于外部连接的连接器布置在第一和第二薄部分的表面上，其中每个薄部分和主线部分具有水平差。

公开(公告)号：US20160037637A1

公开(公告)日：2016-02-04

申请号：US14449089

申请日：2014-07-31

Applicant: Keysight Technologies, Inc.

Inventor： Brian Wade Carlson ,  William Hollender ,  Donald Ingram

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0269 ,  H05K3/4638 ,  H05K2201/041 ,  H05K2201/0919 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2201/09936 ,  H05K2203/166

Abstract: A printed circuit board (PCB) includes a stack of core layers disposed one over another, and electrically conductive interconnects extending vertically in the stack. Each of the core layers includes a substrate having opposite major surfaces, an electrically conductive active trace extending along at least one of the major surfaces, and an indicium. The stack also has an exposed edge where the indicia of the layers are together revealed. The indicia provide identifying and/or fiducial information about the PCB.

Abstract translation: 印刷电路板（PCB）包括一层叠置的芯层，以及在堆叠中垂直延伸的导电互连。 每个芯层包括具有相反主要表面的基底，沿主要表面中的至少一个延伸的导电活性迹线和标记。 堆叠还具有暴露的边缘，其中层的标记一起显露。 标记提供关于PCB的识别和/或基准信息。