公开(公告)号：EP1875508A4

公开(公告)日：2009-08-05

申请号：EP06750977

申请日：2006-04-21

Applicant: IBM

Inventor： DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

IPC: H01L29/04

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

Abstract: Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.

公开(公告)号：EP1687457A4

公开(公告)日：2009-06-17

申请号：EP04812387

申请日：2004-11-29

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  DETAVERNIER CHRISTOPHER ,  JAMMY RAJARAO ,  SAENGER KATHERINE L

IPC: H01L21/8238 ,  C23C14/06 ,  C23C16/32 ,  H01L27/108 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/823842

Abstract: A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET that comprises a gate electrode comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

公开(公告)号：EP1535297A4

公开(公告)日：2007-07-18

申请号：EP02768707

申请日：2002-08-26

Applicant: IBM

Inventor： JAHNES CHRISTOPHER V ,  LUND JENNIFER L ,  SAENGER KATHERINE L ,  VOLANT RICHARD P

IPC: B81B3/00 ,  B81C1/00 ,  G02B5/00 ,  G02B26/00 ,  G02B26/08 ,  H01H57/00 ,  H01H59/00

CPC classification number: H01H59/0009 ,  H01H2057/006

Abstract: A micro-electromechanical (MEM) RF switch provided with a deflectable membrane (60) activates a switch contact or plunger (40). The membrane incorporates interdigitated metal electrodes (70) which cause a stress gradient in the membrane when activated by way of a DC electric field. The stress gradient results in a predictable bending or displacement of the membrane (60), and is used to mechanically displace the switch contact (30). An RF gap area (25) located within the cavity (250) is totally segregated from the gaps (71) between the interdigitated metal electrodes (70). The membrane is electrostatically displaced in two opposing directions, thereby aiding to activate and deactivate the switch. The micro-electromechanical switch includes: a cavity (250); at least one conductive path (20) integral to a first surface bordering the cavity; a flexible membrane (60) parallel to the first surface bordering the cavity (250), the flexible membrane (60) having a plurality of actuating electrodes (70); and a plunger (40) attached to the flexible membrane (60) in a direction away from the actuating electrodes (70), the plunger (40) having a conductive surface that makes electric contact with the conductive paths, opening and closing the switch.

公开(公告)号：EP1535296A4

公开(公告)日：2007-04-04

申请号：EP02746591

申请日：2002-06-14

Applicant: IBM

Inventor： DELIGIANNI HARIKLIA ,  GREENBERG DAVID R ,  JAHNES CHRISTOPHER V ,  LUND JENNIFER L ,  SAENGER KATHERINE L ,  VOLANT RICHARD P

IPC: H01H57/00 ,  H01H59/00 ,  H01L21/00

CPC classification number: H01H59/0009

Abstract: A micro-electromechanical switch (MEMS) having a deformable elastomeric element (1) which exhibits a large change in conductivity with a small amount of displacement. The deformable elastomeric element (1) is displaced by an electrostatic force that is applied laterally resulting in a small transverse displacement. The transversal displacement, in turn, pushes a metallic contact (7) against two conductive paths (5, 6), allowing passage of electrical signals. The elastomer (1) is provided on two opposing sids with embedded metallic elements (9, 10), such as impregnated metallic rods, metallic sheets, metallic particles, or conductive paste. Actuation electrodes (18, 8) are placed parallel to the conductive sides of the elastomer. A voltage applied between the conductive side of the elastomer and the respective actuation electrodes (18, 8) generate the electrostatic attractive force that compresses the elastomer (1), creating the transverse displacement that closes the MEMS. The elastomeric based MEMS extends the lifetime of the switch by extending fatigue life of the deformable switch elements.

公开(公告)号：WO2006076086A3

公开(公告)日：2009-04-16

申请号：PCT/US2005043552

申请日：2005-12-02

Applicant: IBM ,  CALLEGARI ALESSANDRO C ,  GRIBELYUK MICHAEL A ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  SAENGER KATHERINE L ,  ZAFAR SUFI

Inventor： CALLEGARI ALESSANDRO C ,  GRIBELYUK MICHAEL A ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  SAENGER KATHERINE L ,  ZAFAR SUFI

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/4966 ,  C23C14/0036 ,  C23C14/0635 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

Abstract: A compound metal comprising TiC which is a p-type metal having a workfunction of about 4.75 to about 5.3, preferably about 5, eV that is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer is provided as well as a method of fabricating the TiC compound metal. Furthermore, the TiC metal compound of the present invention is a very efficient oxygen diffusion barrier at 1000°C allowing very aggressive equivalent oxide thickness (EOT) and inversion layer thickness scaling below 14 Å in a p-metal oxide semiconductor (pMOS) device.

Abstract translation: 提供了包含TiC的复合金属，其是在包括高k电介质和界面层的栅极堆叠上具有约4.75至约5.3，优选约5e的功函数的功函数的热电稳定的p型金属，以及 制造TiC复合金属的方法。 此外，本发明的TiC金属化合物在1000℃下是非常有效的氧扩散阻挡层，在p-金属氧化物半导体（pMOS）器件中允许非常有侵蚀性的等效氧化物厚度（EOT）和低于14的反型层厚度标度。

公开(公告)号：WO2005062752A2

公开(公告)日：2005-07-14

申请号：PCT/US2004039855

申请日：2004-11-29

Applicant: IBM ,  CABRAL CYRIL JR ,  DETAVERNIER CHRISTOPHER ,  JAMMY RAJARAO ,  SAENGER KATHERINE L

Inventor： CABRAL CYRIL JR ,  DETAVERNIER CHRISTOPHER ,  JAMMY RAJARAO ,  SAENGER KATHERINE L

IPC: H01L21/8238 ,  H01L27/108 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/823842

Abstract: A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET that comprises a gate electrode comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

Abstract translation: 提供了包括至少一个FET的半导体器件，例如互补金属氧化物半导体（CMOS），其包括包含金属碳化物的栅电极和制造方法。 CMOS包括双功能金属栅电极，由此双功能功能由金属和金属的碳化物提供。

公开(公告)号：WO2005057631A2

公开(公告)日：2005-06-23

申请号：PCT/US2004039970

申请日：2004-11-30

Applicant: IBM ,  DE SOUZA JOEL P ,  OTT JOHN A ,  REZNICEK ALEXANDER ,  SAENGER KATHERINE L

Inventor： DE SOUZA JOEL P ,  OTT JOHN A ,  REZNICEK ALEXANDER ,  SAENGER KATHERINE L

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/78696 ,  H01L21/2022 ,  H01L21/76251 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/66772 ,  H01L29/78654

Abstract: A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid­-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.

Abstract translation: 提供了利用层叠模板层的局部非晶化和重结晶的方法，用于制造具有不同晶体取向的半导体层的平面基板。 还提供了利用本发明的方法构建的混合取向半导体衬底结构，以及与各种CMOS电路集成的这种结构，其包括设置在不同表面取向上的至少两个半导体器件，用于增强器件性能。

公开(公告)号：GB2510058A

公开(公告)日：2014-07-23

申请号：GB201322674

申请日：2012-05-07

Applicant: IBM

Inventor： CHEN ZHIHONG ,  FRANKLIN AARON D ,  HAN SHU-JEN ,  HANNON JAMES BOWLER ,  SAENGER KATHERINE L ,  TULEVSKI GEORGE STOJAN

IPC: H01L29/423 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/16 ,  H01L29/49 ,  H01L29/778 ,  H01L29/786 ,  H01L51/00

Abstract: Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

公开(公告)号：DE112012002305T5

公开(公告)日：2014-03-13

申请号：DE112012002305

申请日：2012-05-08

Applicant: IBM ,  KING ABDULAZIZ CITY SCI & TECH

Inventor： KHAYYAT MAHA M ,  SOSA CORTES NORMA E ,  SAENGER KATHERINE L ,  BEDELL STEPHEN W ,  SADANA DEVENDRA K

IPC: H01L21/30

Abstract: Es wird ein Verfahren bereitgestellt, um (i) eine zusätzliche Steuerung in einen Prozess für ein Spalling von Material einzubringen, um so sowohl die Initiierung von Rissen als auch die Ausbreitung von Rissen zu verbessern, und um (ii) den Bereich von auswahlbaren Spalling-Tiefen zu vergrößern. In einer Ausführungsform beinhaltet das Verfahren ein Bereitstellen einer Stressorschicht auf einer Oberfläche eines Grundsubstrats bei einer ersten Temperatur, welche die Raumtemperatur ist. Als Nächstes wird das Grundsubstrat, das die Stressorschicht beinhaltet, auf eine zweite Temperatur gebracht, die niedriger als Raumtemperatur ist. Das Grundsubstrat wird bei der zweiten Temperatur abgeplatzt, um eine abgeplatzte Materialschicht zu bilden. Danach wird die abgeplatzte Materialschicht auf Raumtemperatur, d. h. die erste Temperatur, zurückgebracht.

公开(公告)号：GB2503851A

公开(公告)日：2014-01-08

申请号：GB201318741

申请日：2012-05-08

Applicant: IBM

Inventor： KHAYYAT MAHA M ,  CORTES NORMA E SOSA ,  SAENGER KATHERINE L ,  BEDELL STEPHEN W ,  SADANA DEVENDRA K

IPC: H01L21/18 ,  H01L21/30

Abstract: Method to (i) introduce additional control into a material spalling process, thus improving both the crack initiation and propagation, and (ii) increase the range of selectable spalling depths are provided. In one embodiment, the method includes providing a stressor layer on a surface of a base substrate at a first temperature which is room temperature. Next, the base substrate including the stressor layer is brought to a second temperature which is less than room temperature. The base substrate is spalled at the second temperature to form a spalled material layer. Thereafter, the spalled material layer is returned to room temperature, i.e., the first temperature.