公开(公告)号：US09730313B2

公开(公告)日：2017-08-08

申请号：US14947065

申请日：2015-11-20

Applicant: Amphenol Corporation

Inventor： Mark W. Gailus ,  Marc B. Cartier, Jr. ,  Vysakh Sivarajan ,  David Levine

IPC: H05K1/09 ,  H05K1/11 ,  H05K7/10 ,  H05K1/02 ,  H01R43/20 ,  H05K3/40 ,  H05K3/00

CPC classification number: H05K1/0222 ,  H01R43/205 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/025 ,  H05K1/0251 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/07 ,  H05K2201/09063 ,  H05K2201/09318 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/097 ,  H05K2201/09718 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/10189

Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; first and second signal vias forming a differential signal pair, the first and second signal vias extending through the attachment layers and connecting to respective signal traces on a breakout layer of the routing layers; an antipad of a first type around and between the first and second signal vias in one or more of the attachment layers; and antipads of a second type around the first and second signal vias in at least one routing layer adjacent to the breakout layer.

公开(公告)号：US20170156205A1

公开(公告)日：2017-06-01

申请号：US15284510

申请日：2016-10-03

Applicant: UNIFLEX Technology Inc.

Inventor： Yi-Chun Liu ,  Chiu-Pei Huang ,  Pei-Hao Hung ,  Yuan-Chih Lee

IPC: H05K1/02 ,  H05K3/46 ,  H05K3/06 ,  H05K1/11 ,  H05K3/42

CPC classification number: H05K1/0278 ,  H05K1/115 ,  H05K3/064 ,  H05K3/421 ,  H05K3/423 ,  H05K3/429 ,  H05K3/4652 ,  H05K3/4664 ,  H05K3/4691 ,  H05K2201/0195 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2203/0502

Abstract: A rigid-flex circuit board includes a flexible circuit board, a plurality of patterned photo-imageable substrates and a plurality of patterned circuit layers. The flexible circuit board includes a plurality of exposed regions, a top surface and a bottom surface opposite to the top surface. The exposed regions are respectively located at the top surface and the bottom surface. The patterned photo-imageable substrates are disposed on the top surface and the bottom surface respectively. Each patterned photo-imageable substrate includes an opening exposing the corresponding exposed region. Each patterned photo-imageable substrate includes photo-sensitive material. The patterned circuit layers are disposed on the patterned photo-imageable substrates respectively and expose the exposed regions. A manufacturing method of the rigid-flex circuit board is also provided.

公开(公告)号：US20170149155A1

公开(公告)日：2017-05-25

申请号：US14952242

申请日：2015-11-25

Applicant: MERCURY SYSTEMS, INC.

Inventor： Darryl J. MCKENNEY ,  Absu METHRATTA ,  Erica OUELLETTE

IPC: H01R12/71 ,  H05K1/02 ,  H01R12/58

CPC classification number: H01R12/58 ,  H01R4/028 ,  H01R12/00 ,  H01R12/526 ,  H01R12/714 ,  H01R12/716 ,  H01R13/05 ,  H01R13/405 ,  H01R13/652 ,  H05K1/0213 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/111 ,  H05K1/112 ,  H05K1/115 ,  H05K1/181 ,  H05K1/184 ,  H05K3/308 ,  H05K3/34 ,  H05K3/3421 ,  H05K3/42 ,  H05K3/421 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09827 ,  H05K2201/10098 ,  H05K2201/10189 ,  H05K2201/10295 ,  H05K2201/1078 ,  H05K2201/10803 ,  H05K2201/10871 ,  H05K2201/10878 ,  H05K2201/10901 ,  H05K2203/0455 ,  Y02P70/611

Abstract: According to exemplary embodiments, a tapered surface interconnect is formed on a printed circuit board (PCB). A compliant pin of an electrical connector may be coupled to the tapered surface interconnect and soldered thereto. The surface interconnect may be formed by drilling through one or more layers of the PCB. The depth of the surface interconnect may be shorter than a height or a thickness of the PCB. The surface interconnect may have a tapered side wall to allow for a better fit with a tapered compliant pin. The inclination of the side wall of the surface interconnect may be linear or concave. The intersection between the tapered sidewall and the bottom of the surface interconnect may be rounded to minimize pin insertion issues and may allow for easier solder flux evacuation from the surface interconnect during the soldering process. The compliant pin may be soldered into place upon being coupled to the tapered surface interconnect.

公开(公告)号：US20170118842A1

公开(公告)日：2017-04-27

申请号：US14918678

申请日：2015-10-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce J. CHAMBERLIN ,  Andreas HUBER ,  Harald HUELS ,  Thomas STRACH ,  Thomas-Michael WINKEL

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/09 ,  H05K1/02 ,  H05K3/40 ,  H05K3/00 ,  H05K1/11

CPC classification number: H05K1/184 ,  B23K1/0016 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/111 ,  H05K1/113 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/185 ,  H05K1/186 ,  H05K3/0047 ,  H05K3/3447 ,  H05K3/429 ,  H05K3/46 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09345 ,  H05K2201/09381 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/1006 ,  H05K2201/10174

Abstract: Embedding a discrete electrical device in a printed circuit board (PCB) includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to an electrically conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first electrical device contact device and the electrically conductive structure in the first layer; and establishing a second electrical connection between a second electrical device contact and a second layer, the second layer being one of the electrically conductive layers of a second horizontal core section.

公开(公告)号：US20170079140A1

公开(公告)日：2017-03-16

申请号：US14851083

申请日：2015-09-11

Applicant: Intel Corporation

Inventor： Raul Enriquez Shibayama ,  Kai Xiao ,  Nicte A. Zavala Castro ,  Beom-Taek Lee

IPC: H05K1/14 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/144 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/181 ,  H05K1/184 ,  H05K3/368 ,  H05K2201/041 ,  H05K2201/09545 ,  H05K2201/10159 ,  H05K2201/10303 ,  H05K2201/10734

Abstract: In one embodiment, first and second circuit boards may be coupled together. The first circuit board may include a first trace to electrically couple a first integrated circuit to a first via of the first circuit board. In turn, the second circuit board may include a second trace to electrically couple a first contact of a first memory socket adapted to the first circuit board and a first contact of a second memory socket adapted to the first circuit board. This second trace, when the circuit boards are coupled together, is to electrically couple to a first via of the second circuit board, to enable the first via of the second board to electrically couple to the first via of the first circuit board. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，第一和第二电路板可以耦合在一起。 第一电路板可以包括将第一集成电路电耦合到第一电路板的第一通孔的第一迹线。 反过来，第二电路板可以包括第二迹线，用于电耦合适于第一电路板的第一存储器插座的第一触点和适于第一电路板的第二存储器插槽的第一触点。 当电路板耦合在一起时，该第二迹线将电耦合到第二电路板的第一通孔，以使得第二板的第一通孔能够电耦合到第一电路板的第一通孔。 描述和要求保护其他实施例。

公开(公告)号：US09526178B2

公开(公告)日：2016-12-20

申请号：US14519677

申请日：2014-10-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongxing Yang ,  Feng Gao ,  Mingli Huang

IPC: H05K3/42 ,  H05K3/00

CPC classification number: H05K3/0047 ,  H05K3/429 ,  H05K2201/09545 ,  H05K2203/0207 ,  Y10T29/49156

Abstract: A printed circuit board (PCB) backdrilling method is disclosed, where a conductive layer is disposed between a surface of a PCB on an intended-for-backdrilling side of a plated through hole (PTH) and a target signal layer of the PCB, and the method includes: performing a first backdrilling on the PTH with a first preset depth starting from the surface of the PCB; controlling the backdrill bit to move along the drill hole formed in the first backdrilling toward the target signal layer; and when the backdrill bit is in contact with the conductive layer, completing a second backdrilling with a second preset depth starting from the conductive layer.

Abstract translation: 公开了一种印刷电路板（PCB）回钻方法，其中将导电层设置在电镀通孔（PTH）的预期的后向钻孔侧的PCB的表面与PCB的目标信号层之间，以及 该方法包括：以从PCB的表面开始的第一预设深度在PTH上执行第一次回钻; 控制回钻头沿着形成在第一反向钻削中的钻孔朝向目标信号层移动; 并且当所述反钻头与所述导电层接触时，从所述导电层开始以第二预设深度完成第二次回钻。

公开(公告)号：US09480162B2

公开(公告)日：2016-10-25

申请号：US14691468

申请日：2015-04-20

Applicant: INTEL CORPORATION

Inventor： Md Altaf Hossain ,  Jin Zhao ,  John T. Vu

IPC: H05K1/18 ,  H05K1/16 ,  H05K1/03 ,  H05K3/32 ,  H05K3/42 ,  H05K1/11

CPC classification number: H05K1/183 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0326 ,  H05K1/113 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/32 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/09709 ,  H05K2201/0989 ,  H05K2201/10734 ,  Y10T29/4913

Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.

公开(公告)号：US20160278207A1

公开(公告)日：2016-09-22

申请号：US14834180

申请日：2015-08-24

Applicant: Multek Technologies Ltd.

Inventor： Kwan Pen ,  Pui Yin Yu

IPC: H05K1/11 ,  H05K3/18 ,  H05K3/06 ,  H05K3/42 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K1/115 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0058 ,  H05K3/06 ,  H05K3/181 ,  H05K3/188 ,  H05K3/42 ,  H05K3/422 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/095 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/10303

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

Abstract translation: 用于制造电路板的选择性段通过电镀工艺选择性地将内部导电层互连在相同的通孔内的单独的段。 电镀抗蚀剂插入内芯通孔，然后在化学镀处理后剥离。 在电镀抗蚀剂上剥离化学镀导致通孔壁上的电镀不连续。 在随后的电镀工艺中，由于电镀不连续，内芯层不能镀覆。 所得到的电路板结构在通孔内具有单独的电互连段。

公开(公告)号：US20160242280A1

公开(公告)日：2016-08-18

申请号：US14620880

申请日：2015-02-12

Applicant: International Business Machines Corporation

Inventor： Bruce J. Chamberlin ,  Joseph Kuczynski ,  Paula M. Nixa

IPC: H05K1/03 ,  C09D139/04 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42 ,  C09D143/04 ,  C09D183/00

CPC classification number: H05K1/0366 ,  C03B37/022 ,  C03B37/0756 ,  C09D139/04 ,  C09D143/04 ,  C09D183/04 ,  H05K1/024 ,  H05K1/115 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/029 ,  H05K2201/09545 ,  H05K2203/1147

Abstract: An enhanced substrate for use in printed circuit boards (PCBs) includes low-Dk-core glass fibers having low dielectric constant (Dk) cores. In some embodiments, the low-Dk-core glass fibers are filled with a low Dk fluid, such as a gas (e.g., air, nitrogen and/or a noble gas) or a liquid. After via holes are drilled or otherwise formed in the substrate, silane is applied to the ends of hollow glass fibers exposed in the via holes to seal the low Dk fluid within the cores of the hollow glass fibers. In some embodiments, the low-Dk-core glass fibers are filled with a solid (e.g., a low Dk resin). For example, a hollow glass fiber may be provided, and then filled with a low Dk resin in a liquid state. The low Dk resin within the hollow glass fiber is then cured to a solid state.

Abstract translation: 用于印刷电路板（PCB）的增强型基板包括具有低介电常数（Dk）芯的低Dk芯玻璃纤维。 在一些实施例中，低Dk芯玻璃纤维填充有低Dk流体，例如气体（例如空气，氮气和/或惰性气体）或液体。 在基板中钻孔或以其他方式形成通孔之后，将硅烷施加到暴露在通孔中的中空玻璃纤维的端部，以密封中空玻璃纤维的芯内的低Dk流体。 在一些实施方案中，低-Dk芯玻璃纤维用固体（例如低Dk树脂）填充。 例如，可以设置中空玻璃纤维，然后以液态填充低Dk树脂。 然后将中空玻璃纤维内的低Dk树脂固化成固态。

公开(公告)号：US20160135283A1

公开(公告)日：2016-05-12

申请号：US14653522

申请日：2013-12-13

Applicant: VALEO SYSTEMES THERMIQUES

Inventor： Karen Chauvin ,  Xavier Goumain ,  Friedbald Kiel

IPC: H05K1/02 ,  H05K1/18 ,  H05K7/20 ,  H05K1/11

CPC classification number: H05K1/0206 ,  H05K1/115 ,  H05K1/181 ,  H05K7/20163 ,  H05K7/205 ,  H05K7/20854 ,  H05K7/20863 ,  H05K2201/066 ,  H05K2201/09545

Abstract: The invention relates to a cooling device for a printed circuit board, comprising a printed circuit board equipped with at least one face or first face and at least one heat sink (9) brazed to said at least one face of the printed circuit, in which said at least one heat sink (9) can be disposed in a flow of coolant. The invention is suitable for motor vehicles.

Abstract translation: 本发明涉及一种用于印刷电路板的冷却装置，包括装配有至少一个面或第一面的印刷电路板和钎焊到印刷电路的所述至少一个面的至少一个散热器（9），其中 所述至少一个散热器（9）可以设置在冷却剂流中。 本发明适用于机动车辆。