公开(公告)号：KR1020050063619A

公开(公告)日：2005-06-28

申请号：KR1020030095038

申请日：2003-12-22

Applicant: 한국전자통신연구원

Inventor： 한선호 ,  한진호 ,  박문양

IPC: H03B28/00

CPC classification number: H03B5/1841 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03B5/1293

Abstract: 본 발명은 발진기 및 주파수 합성기에 관한 발명이다. 특히 전압 제어 디지털 아날로그 발진기 및 이를 이용한 주파수 합성기에 관한 것이다.
본 발명은 아날로그 입력단에 입력되는 전압 및 디지털 입력단에 입력되는 디지털 값에 따라 출력 신호의 주파수가 변화하는 발진기, 및 간헐적으로 상기 아날로그 입력단에 입력되는 전압을 제 1 임계 전압 및 제 2 임계 전압과 대소를 비교하여, 그 결과에 따라 상기 디지털 입력단에 입력되는 디지털 값을 변화시키는 디지털 동조기를 포함하는 전압 제어 디지털 아날로그 발진기를 제공한다. 또한 이를 이용한 주파수 합성기를 제공한다.
본 발명에 의한 발진기는 및 주파수 합성기는 잡음은 적으면서도 광대역의 주파수 출력을 얻을 수 있다는 장점이 있다.

公开(公告)号：KR100457175B1

公开(公告)日：2004-11-16

申请号：KR1020020079924

申请日：2002-12-14

Applicant: 한국전자통신연구원

Inventor： 조민형 ,  이승철 ,  박문양

IPC: H04L27/26

CPC classification number: H04L27/365 ,  H03C3/40

Abstract: There is provided a quadrature modulation transmitter which is capable of solving several problems of the conventional transmitter while performing the same function as the heterodyne transmitter or the digital IF transmitter, in which a circuit structure is simplified and a power consumption is reduced compared with the conventional transmitter. The quadrature modulation transmitter includes: a digital processing block for receiving an I-channel data, a Q-channel data and a clock signal, modulating the I-channel data or an inverted I-channel data into a first analog signal by means of an I-channel DAC according to a switching of an I-clock signal identical to the clock signal, and modulating the Q-channel data and an inverted Q-channel data into a second analog signal by means of a Q-channel DAC according to a switching of a Q-clock signal, the Q-clock signal being an inverted clock signal; and an analog processing block for receiving the first and second analog signals from the digital processing block, adding the first and second analog signals, converting the added signal into an RF domain signal through a mixing operation, and amplifying and transmitting the RF domain signal.

Abstract translation: 提供了一种正交调制发送器，其能够解决常规发送器的若干问题，同时执行与外差发送器或数字中频发送器相同的功能，其中电路结构被简化并且功耗比常规的 发射机。 该正交调制发射机包括：数字处理块，用于接收I信道数据，Q信道数据和时钟信号，借助于一个调制器将I信道数据或反相的I信道数据调制成第一模拟信号 根据与时钟信号相同的I时钟信号的切换，将Q信道数据和反相Q信道数据通过Q信道DAC调制为第二模拟信号， 切换Q时钟信号，所述Q时钟信号是反相时钟信号; 以及模拟处理模块，用于接收来自数字处理模块的第一模拟信号和第二模拟信号，添加第一模拟信号和第二模拟信号，通过混合操作将所添加的信号转换为RF域信号，以及放大并发送RF域信号。

公开(公告)号：KR1020040051366A

公开(公告)日：2004-06-18

申请号：KR1020020079287

申请日：2002-12-12

Applicant: 한국전자통신연구원

Inventor： 권종기 ,  조규형 ,  박문양 ,  김종대

IPC: H03G3/30

Abstract: PURPOSE: A variable gain amplifier is provided to supply a variable amplification function for the input signal which has a wide range by the external control signal at a low supply power. CONSTITUTION: A variable gain amplifier includes an input circuit(110), a variable gain control circuit(120) and a current/voltage converting circuit(130). The input circuit(110) which is composed of a folded cascode structure receives a first and a second input signal in the form of differential form. The input circuit(110) amplifies the differential signal between the first and the second input signals in response to the first bias voltage to thereby generate a first and a second differential signals. The input circuit(110) outputs the first and the second differential signals from a current mirror. The variable gain control circuit(120) determines the direct current operational point by receiving the first and the second differential signals and the bias current from the current mirror, generates a first and a second variable current by varying the variable voltage gain in response to the gain control voltage signal and outputs the first and the second variable currents in response to the second bias voltage. And, the current/voltage converting circuit(130) receives the first and the second variable currents and outputs the signals by converting the first and the second variable currents into the first and the second output voltages.

Abstract translation: 目的：提供可变增益放大器，为低输入功率下外部控制信号提供宽范围输入信号的可变放大功能。 构成：可变增益放大器包括输入电路（110），可变增益控制电路（120）和电流/电压转换电路（130）。 由折叠共源共栅结构组成的输入电路（110）接收差分形式的第一和第二输入信号。 输入电路（110）响应于第一偏置电压放大第一和第二输入信号之间的差分信号，从而产生第一和第二差分信号。 输入电路（110）从电流镜输出第一和第二差分信号。 可变增益控制电路（120）通过接收来自电流镜的第一和第二差分信号和偏置电流来确定直流操作点，通过响应于第二和第二可变电流而改变可变电压增益，产生第一和第二可变电流 增益控制电压信号，并响应于第二偏置电压输出第一和第二可变电流。 并且，电流/电压转换电路（130）接收第一和第二可变电流，并通过将第一和第二可变电流转换为第一和第二输出电压来输出信号。

公开(公告)号：KR1020040042130A

公开(公告)日：2004-05-20

申请号：KR1020020070287

申请日：2002-11-13

Applicant: 한국전자통신연구원

Inventor： 김천수 ,  박필재 ,  박문양 ,  유현규

IPC: H01L27/04

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F21/12 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: PURPOSE: A stack type variable inductor is provided to be capable of considerably reducing the surface area of an IC(Integrated Circuit) chip. CONSTITUTION: A stack type variable inductor is provided with the first to N-th inductor formed at stacked metal layers and connected with each other in series, the first and second port(Port1,Port2) connected with the uppermost inductor and the lowermost inductor, and at least one switching device(6). At this time, one end portion of the switching device is connected with one out of the ports and the other end portion of the switching device is connected with one out of neighboring serial connection terminals between the first to N-th inductor. Preferably, the metal layer-stacked structure is formed by using a CMOS(Complementary Metal Oxide Semiconductor) technique and an MOSFET(Metal Oxide Semiconductor Field Effect Transistor) is used as the switching device.

Abstract translation: 目的：提供堆叠式可变电感器，以便大大减少IC（集成电路）芯片的表面积。 构成：堆叠型可变电感器具有形成在堆叠金属层上的第一至第N电感器，并且彼此串联连接，第一和第二端口（Port1，Port2）与最上层电感器和最下层电感器连接， 和至少一个开关装置（6）。 此时，开关装置的一端与端口中的一个连接，开关装置的另一端与第一〜第N电感之间的相邻串联连接端子中的一个连接。 优选地，通过使用CMOS（互补金属氧化物半导体）技术形成金属层堆叠结构，并且使用MOSFET（金属氧化物半导体场效应晶体管）作为开关器件。

公开(公告)号：KR100415547B1

公开(公告)日：2004-01-24

申请号：KR1020010047553

申请日：2001-08-07

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  이상국 ,  황남 ,  박정우 ,  이진택 ,  박문양 ,  김성도 ,  윤용식 ,  한선호 ,  김남수

IPC: H01L27/04

Abstract: PURPOSE: A high-Q poly-to-poly capacitor structure for RF ICs is provided to reduce an area of a lower electrode plate to lower parasitic capacitance by using an interdigit structure. CONSTITUTION: A lower electrode plate(23) of a capacitor is formed on a silicon substrate(21). The lower electrode plate(23) is formed with the first polysilicon layer. An upper electrode plate(25) is formed on the lower electrode plate(23). The upper electrode plate(25) is formed with the second polysilicon layer. The upper electrode plate(25) is connected with the first metal layer(28) through a plurality of contacts(27). A contact/the first metal layer/via layer(27/28/29) are sequentially laminated on the lower electrode plate(23). The second metal layer(31) is connected with the via layer(29). The first and the second metal layers(28,31) are connected to each other by using the via layer(29). The lower electrode plate(23) and the upper electrode plate(25) are formed within silicon oxide layers(22,24,26,30). The contact(29) and the first metal layer(28) are formed within the silicon oxide layers(22,24,26,30).

Abstract translation: 目的：提供用于RF IC的高Q多对多电容器结构，以通过使用叉指结构来减小下电极板的面积以降低寄生电容。 构成：在硅基板（21）上形成电容器的下部电极板（23）。 下电极板（23）形成有第一多晶硅层。 上电极板（25）形成在下电极板（23）上。 上电极板（25）形成有第二多晶硅层。 上电极板（25）通过多个触点（27）与第一金属层（28）连接。 接触/第一金属层/通孔层（27/28/29）顺序层叠在下电极板（23）上。 第二金属层（31）与通孔层（29）连接。 第一和第二金属层（28,31）通过使用通孔层（29）彼此连接。 下电极板（23）和上电极板（25）形成在氧化硅层（22,24,26,30）内。 触点（29）和第一金属层（28）形成在氧化硅层（22,24,26,30）内。

公开(公告)号：KR1020030062072A

公开(公告)日：2003-07-23

申请号：KR1020020002493

申请日：2002-01-16

Applicant: 한국전자통신연구원

Inventor： 박문양 ,  김성도 ,  유현규 ,  김경수

IPC: H03H11/32

CPC classification number: H03D7/1441 ,  H03B5/1209 ,  H03B5/1228 ,  H03D2200/0023 ,  H03D2200/0043 ,  H03D2200/009

Abstract: PURPOSE: A local oscillator balloon using an inverting circuit is provided to improve the driving amplitude and reduce a phase difference between two complementary outputs by using the inverting circuit. CONSTITUTION: A local oscillator balloon using an inverting circuit includes a complementary output conversion circuit(21), a differential amplification circuit(22), and an inverting circuit(24). The complementary output conversion circuit is used for receiving and amplifying a weak signal from a local oscillator to output two complementary signals. The differential amplification circuit is used for outputting two signals having the predetermined amplitude according to the complementary signals of the complementary output conversion circuit. The inversion circuit is used for inverting the output signals of the differential amplification circuit and outputting the inverted signals.

Abstract translation: 目的：提供使用反相电路的本地振荡器气球，以通过使用反相电路来提高驱动振幅并减少两个互补输出之间的相位差。 构成：使用反相电路的本地振荡器气球包括互补输出转换电路（21），差分放大电路（22）和反相电路（24）。 互补输出转换电路用于接收和放大来自本地振荡器的弱信号以输出两个互补信号。 差分放大电路用于根据互补输出转换电路的互补信号输出具有预定幅度的两个信号。 反相电路用于反相差分放大电路的输出信号并输出​​反相信号。

公开(公告)号：KR1020030039720A

公开(公告)日：2003-05-22

申请号：KR1020010070752

申请日：2001-11-14

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  한선호 ,  박문양 ,  박필재 ,  김남수 ,  김천수 ,  김성도 ,  윤용식

IPC: H01P1/15

CPC classification number: H03H7/0115 ,  H03H2001/0085

Abstract: PURPOSE: A high frequency integrated circuit and an integrated type high frequency semiconductor device are provided to achieve improved performance of the integrated circuit and improved yield rate by allowing for trimming of the high frequency integrated circuit. CONSTITUTION: A high frequency integrated circuit comprises a plurality of inductors(L2 to L2n) serially connected between a high frequency input terminal(RFin) and a high frequency output terminal(RFout); a plurality of capacitors(C1 to C2n+1) having ends connected to the connection nodes between the inductors; a switching unit connected to the other ends of the capacitors and a ground terminal; and a feedback control unit(21) for forming a loop for feeding back the signal output from the high frequency output terminal and controlling the switching unit. The feedback control unit includes a decoding section(52) for determining on/off operation of the switching unit; a feedback section(54) for forming a feedback loop; and a control section(53) for outputting a signal for determining on/off operation of the switching unit to the decoding section.

Abstract translation: 目的：提供高频集成电路和集成型高频半导体器件，通过允许修整高频集成电路来实现集成电路的改进性能和提高的成品率。 构成：高频集成电路包括串联连接在高频输入端（RFin）和高频输出端（RFout）之间的多个电感器（L2〜L2n）。 多个电容器（C1至C2n + 1），其端部连接到电感器之间的连接节点; 连接到电容器的另一端的开关单元和接地端子; 以及反馈控制单元（21），用于形成用于反馈从高频输出端输出的信号并控制切换单元的回路。 反馈控制单元包括用于确定开关单元的接通/断开操作的解码部分（52） 用于形成反馈回路的反馈部分（54）; 以及用于输出用于确定切换单元的接通/断开操作的信号到解码部分的控制部分（53）。

公开(公告)号：KR1020030004496A

公开(公告)日：2003-01-15

申请号：KR1020010039998

申请日：2001-07-05

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  한선호 ,  박문양 ,  김성도 ,  윤용식 ,  김이섭 ,  성기혁 ,  양병도 ,  김영준

IPC: H03B28/00

CPC classification number: G06F1/0356 ,  G06F1/0328 ,  G06F2101/04 ,  G11C17/00

Abstract: PURPOSE: A ROM driving method and a digital frequency synthesizer(DDFS) using the same are provided to reduce a power consumption and a size by minimizing a size of a ROM in a digital frequency synthesizer. CONSTITUTION: When an original ROM has 2k input addresses and 2i sections, "i" is initialized as "k"(S31). A variable "q" is initialized as an output bit number of the original ROM(S32). A smallest one among q bit values is stored in a quantization ROM(S33). A difference of quantization values stored in the quantization ROM is obtained(S34). A bit number "e" bit is searched in order to store the greatest error among errors in all input addresses(S35). A total ROM size is calculated(S36). A "q" is reduced by "1" until it becomes "1"(S37). A "i" is reduced by "1" until it becomes "1"(S38). "i, q, and e" values having the smallest ROM size are searched(S39).

Abstract translation: 目的：提供使用其的ROM驱动方法和数字频率合成器（DDFS），以通过使数字频率合成器中的ROM的尺寸最小化来降低功耗和尺寸。 构成：当原始ROM具有2k个输入地址和2i个区段时，“i”被初始化为“k”（S31）。 变量“q”被初始化为原始ROM的输出位数（S32）。 q位值中的最小值存储在量化ROM中（S33）。 获得存储在量化ROM中的量化值的差异（S34）。 搜索位数“e”，以便在所有输入地址中存储错误中的最大误差（S35）。 计算总ROM大小（S36）。 A“q”减小到“1”（S37）。 A“i”减少到“1”（S38）。 搜索具有最小ROM大小的“i，q和e”值（S39）。

公开(公告)号：KR1020010064258A

公开(公告)日：2001-07-09

申请号：KR1019990062408

申请日：1999-12-27

Applicant: 한국전자통신연구원

Inventor： 김충환 ,  유현규 ,  김천수 ,  박민 ,  김성도 ,  박문양 ,  한선호 ,  윤용식

IPC: H01F5/00

Abstract: PURPOSE: A high performance active inductor is provided to be used at a low voltage, and attain impedance of an output port higher than when being used an inductor or a resistance as a load of an output port. CONSTITUTION: A condenser(C31) is connected to a gate and a source of an NMOS(m31) in parallel. A resistor(R31) is ground connected with Vdd on the gate of the NMOS(M31). A high performance active inductor is activated with a simple load without requiring an additional circuit. The active inductor supplies a DC necessary for an amplifying termination, such that any additional circuit, for example, a current source, is not needed. A higher impedance is ensured than a case when a resistor is used as a load through an optimization process.

Abstract translation: 目的：提供一种低电压使用的高性能有源电感器，其输出端口的阻抗高于使用电感器或电阻作为输出端口负载时的阻抗。 构成：电容器（C31）并联连接到NMOS（m31）的栅极和源极。 电阻（R31）与NMOS（M31）的栅极上的Vdd接地。 高性能有源电感器通过简单的负载被激活，而不需要额外的电路。 有源电感器提供放大终端所需的DC，使得不需要任何附加电路，例如电流源。 比通过优化过程使用电阻作为负载的情况下，确保更高的阻抗。

公开(公告)号：KR100246536B1

公开(公告)日：2000-03-15

申请号：KR1019970043554

申请日：1997-08-30

Applicant: 한국전자통신연구원

Inventor： 송규상 ,  박문양 ,  송원철 ,  구진근

IPC: G09G3/296

CPC classification number: H03K19/00315 ,  G09G3/22 ,  G09G3/28 ,  G09G3/296 ,  G09G3/30 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2330/02

Abstract: 기체 플라즈마 발광 표시장치(PDP; Plasma Display Panel) 등의 평면 표시장치(FDP; Flat Display Panel) 구동용으로 사용되는 고전압 구동회로는 로직 레벨의 신호를 고전압의 신호로 변환시켜 출력시키는 기능을 한다. 일반적으로 이런 고전압 구동회로에서는 신호가 하이(high) 또는 로우(low) 상태로 유지되는 시간동안 흐르는 정적전류(static current)나 신호가 스위칭하는 과정에서 흐르는 과도전류(transient current)가 흐르게 된다. 이 두 전류의 흐름에 의하여 불필요한 전력소모가 발생하게 된다. 이러한 문제점을 해결하기 위하여 새로운 회로가 많이 개발되어 있으나 지금까지의 회로는 대부분 정적전류를 줄이기 위하여 고안되었다.
그러나, 본 발명에서는 이 구동회로 내에서 인가되는 상보(complementary)형 두 신호의 스위칭 시간을 조절하는 회로를 부가함으로써 과도전류의 흐름을 제거하였다.