公开(公告)号：US20230352067A1

公开(公告)日：2023-11-02

申请号：US17730401

申请日：2022-04-27

Applicant: NVIDIA Corp.

Inventor： Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir ,  Jaewon Lee

IPC: G11C7/10 ,  G11C7/14

CPC classification number: G11C7/1066 ,  G11C7/1093 ,  G11C7/109 ,  G11C7/1063 ,  G11C7/14

Abstract: A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.

公开(公告)号：US11799799B2

公开(公告)日：2023-10-24

申请号：US17377943

申请日：2021-07-16

Applicant: NVIDIA Corp.

Inventor： Matthias Augustin Blumrich ,  Nan Jiang ,  Larry Robert Dennison

IPC: H04L29/08 ,  H04L49/101 ,  H04L49/00 ,  H04L49/9047 ,  H04L49/253

CPC classification number: H04L49/101 ,  H04L49/254 ,  H04L49/3036 ,  H04L49/70 ,  H04L49/9047

Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

公开(公告)号：US20230337350A1

公开(公告)日：2023-10-19

申请号：US17723172

申请日：2022-04-18

Applicant: NVIDIA Corp.

Inventor： Joey Cai ,  Tiger Yan ,  Zhu Hao ,  Yi Dinghai

IPC: H05K1/02

CPC classification number: H05K1/0203 ,  H05K2201/09227 ,  H05K2201/10734

Abstract: A circuit board includes chip die mounted on a three dimensional rectangular structure, a three dimensional triangular prism structure, or a combination thereof. A ball grid array for the chip die mounted on any such three dimensional structure is interposed between the three dimensional structure and the circuit board itself.

公开(公告)号：US20230275572A1

公开(公告)日：2023-08-31

申请号：US17680763

申请日：2022-02-25

Applicant: NVIDIA Corp.

Inventor： Tezaswi Raja ,  Prashant Singh

IPC: H03K3/037 ,  H03K3/03 ,  H03K5/01

CPC classification number: H03K3/037 ,  H03K3/0315 ,  H03K5/01 ,  H03K2005/00078

Abstract: A ring oscillator circuit with a frequency that is sensitive to the timing of a clock-to-Q (clk2Q) propagation delay of one or more flip-flops utilized in the ring oscillator. The clock2Q is the delay between the clock signal arriving at the clock pin on the flop and the Q output reflecting the state of the input data signal to the flop. Clk2q delay measurements are made based on measurement of the ring oscillator frequency, leading to more accurate estimates of clk2Q for different types of flip-flops and flip-flop combinations, which may in turn enable improvements in circuit layouts, performance, and area.

公开(公告)号：US20230246661A1

公开(公告)日：2023-08-03

申请号：US17931472

申请日：2022-09-12

Applicant: NVIDIA Corp.

Inventor： Xi Chen ,  Yoshinori Nishi ,  John Poulton

IPC: H04B1/04 ,  H03H7/38 ,  H04B1/38

CPC classification number: H04B1/0483 ,  H03H7/38 ,  H04B1/38

Abstract: A simultaneous bi-directional (SBD) transceiver includes a main transmit driver, a replica transmit driver, and a series-series-bridged (SSB) tri-impedance network. A pre-driver stage includes parallel delay paths for the main transmit driver and the replica transmit driver, enabling the delay for signals received by the main transmit driver and the replica transmit driver to be independently configured.

公开(公告)号：US20230197696A1

公开(公告)日：2023-06-22

申请号：US17553519

申请日：2021-12-16

Applicant: NVIDIA Corp.

Inventor： Shuo Zhang ,  Eric Zhu ,  Minto Zheng ,  Michael Zhai ,  Town Zhang ,  Jie Ma

IPC: H01L25/10 ,  H01L25/16 ,  H01L23/538 ,  H05K1/18

CPC classification number: H01L25/105 ,  H01L23/5386 ,  H01L25/16 ,  H05K1/181 ,  H01L2225/107 ,  H01L2225/1094 ,  H05K2201/10015 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10704

Abstract: Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.

公开(公告)号：US20230038061A1

公开(公告)日：2023-02-09

申请号：US17819243

申请日：2022-08-11

Applicant: NVIDIA Corp.

Inventor： Daniel Robert Johnson ,  Jack Choquette ,  Olivier Giroux ,  Michael Patrick McKeown ,  Mark Stephenson ,  Sana Damani

IPC: G06F9/52 ,  G06F9/38 ,  G06F9/48

Abstract: Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.

公开(公告)号：US11574097B2

公开(公告)日：2023-02-07

申请号：US17231866

申请日：2021-04-15

Applicant: NVIDIA Corp.

Inventor： Harbinder Sikka ,  Kaushik Narayanun ,  Lijuan Luo ,  Karthikeyan Natarajan ,  Manjunatha Gowda ,  Sandeep Gangundi

IPC: G06F7/50 ,  G06F30/327 ,  G06N3/08 ,  G06N7/00 ,  G06K9/62 ,  G06N3/04

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

公开(公告)号：US20220292335A1

公开(公告)日：2022-09-15

申请号：US17679681

申请日：2022-02-24

Applicant: NVIDIA Corp.

Inventor： Haoxing Ren

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: An automatic standard cell layout generator that generates circuit layouts for an industry standard cell library on an advanced technology node leverages reinforcement learning (RL) to generate device placements in the layouts and also to fix design rule violations during routing. A genetic algorithm is utilized to generate routing candidates to which a reinforcement learning model is applied to correct the design rule constraint violations incrementally. A design rule checker provides feedback on the violations to the reinforcement learning model and the model learns how to fix the violations. A layout device placer based upon a simulated annealing method may also be utilized.

公开(公告)号：US11409597B2

公开(公告)日：2022-08-09

申请号：US16811499

申请日：2020-03-06

Applicant: NVIDIA Corp.

Inventor： Michael Sullivan ,  Siva Hari ,  Brian Zimmer ,  Timothy Tsai ,  Stephen W. Keckler

IPC: G06F11/10 ,  G06F9/30 ,  G06F11/07

Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.