公开(公告)号：JP2007149325A

公开(公告)日：2007-06-14

申请号：JP2006317757

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ELLIS WAYNE F ,  MANN RANDY W ,  WAGER DAVID J ,  WONG ROBERT C

IPC: G11C11/413 ,  G11C11/412

CPC classification number: G11C5/14 ,  G11C11/413

Abstract: PROBLEM TO BE SOLVED: To provide a static/random/access/memory (SRAM) including a plurality of SRAM cells arranged in an array state.
SOLUTION: The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control circuit corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuit is coupled to an output of a power supply. Each voltage control circuit has a function to temporarily reduce voltage provided to the power supply input of a plurality of SRAM cells that belong to the selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供包括以阵列状态排列的多个SRAM单元的静态/随机/存取/存储器（SRAM）。 解决方案：阵列包括多个行和多个列。 SRAM包括与阵列的多个列中的相应列对应的多个电压控制电路。 多个电压控制电路中的每一个耦合到电源的输出端。 每个电压控制电路具有临时降低提供给属于SRAM的选定列列的多个SRAM单元的电源输入的电压的功能。 选择的列被选择，并且在将位写入属于所选列的SRAM单元之一的写操作期间，该列的电源电压减小。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2000332101A

公开(公告)日：2000-11-30

申请号：JP2000131432

申请日：2000-04-28

Applicant: IBM

Inventor： JEFFREY SCOTT BROWN ,  BRYANT ANDRES ,  ROBERT J GAUTHIER JR ,  MANN RANDY W ,  VOLDMAN STEVEN H

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a silicon-on-insulator(SOI) element having both an element which is completely depleted and an element which is partially depleted on a common substrate. SOLUTION: The semiconductor structure which has a continuous buried oxide layer 24 and multiple trench separate structures 33 and 35 and its formation are disclosed. The buried oxide layer is arranged in the substrate at >=2 trench separate structures in depth. The trench separate structures are variable in depth and it is not important whether the trench separate structures are in contact with the buried oxide layer or not. The two trench separate structures enter the substrate to the same or different depths. The trench separate structures provide insulating separation between areas in the substrate and the separated areas may include a semiconductor element. The semiconductor structure makes it easy to provide a digital element and an analog element on a common wafer. The dual-depth buried oxide layer facilitates the formation of an asymmetrical semiconductor structure.

公开(公告)号：JPH1154454A

公开(公告)日：1999-02-26

申请号：JP19988497

申请日：1997-07-25

Applicant: IBM

Inventor： CABRAL JR CYRIL ,  LAWRENCE ALFRED CLEVENGER ,  FRANCOIS MAXDOLE ,  HARPER JAMES M E ,  MANN RANDY W ,  GLENN LESTER MILES ,  NAKOS JAMES S ,  RONEN ANDREW ROY ,  CATHERINE L SAENGER

IPC: C22C14/00 ,  C30B3/00 ,  H01L21/28

Abstract: PROBLEM TO BE SOLVED: To provide an improved method for forming a C54 phase titanium silicide without requiring a second high-temperature annealing. SOLUTION: A low resistivity titanium silicide and semiconductor devices incorporating the same are formed by a titanium alloy comprising titanium and 1-20 atom percent refractory metal deposited in a layer overlying a silicon substrate. The substrate is then heated to a temperature which is sufficient to practically form a C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, but more preferably be Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900 deg.C, and more preferably between about 600 to 700 deg.C.

公开(公告)号：JP2000357732A

公开(公告)日：2000-12-26

申请号：JP2000124263

申请日：2000-04-25

Applicant: IBM

Inventor： JEFFREY SCOTT BROWN ,  ROBERT J GAUTHIER JR ,  MANN RANDY W ,  VOLDMAN STEVEN H

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for improving latch up characteristic of a semiconductor element. SOLUTION: Dual depth STI 20 is used for mutually separating wells. A trench contains a first substantially horizontal face in a first depth and a second substantially horizontal face in a second depth which is deeper than the first depth. An n-well 26 and a p-well 28 are formed on the respective sides of the trench. A heavily-doped region 18 is formed below the second substantially horizontal face of the trench in a substrate. The heaving-doped region is adjacent to the first and second wells, and the separation of the trench is extended.

公开(公告)号：JPH11261040A

公开(公告)日：1999-09-24

申请号：JP10599

申请日：1999-01-04

Applicant: IBM

Inventor： JOYCE MORINERI AKOSERA ,  MANN RANDY W

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a floating gate in a nonvolatile memory cell, which has the floating gate and a control gate. SOLUTION: First, a plurality of isolation structures 20, which are extended above the surface of a substrate 22 and below the surface of the substrate 22, are formed in the substrate. Then, a floating gate layer 26 is formed on the substrate on at least one part of each isolation structure and between the isolation structures. Lastly, for forming a plurality of floating gate regions isolated by the isolation structures, the gate layer is flattened up to reach the isolation structures.

公开(公告)号：CA2118147A1

公开(公告)日：1995-04-30

申请号：CA2118147

申请日：1994-10-14

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  CLEVENGER LAWRENCE A ,  D HEURLE FRANCOIS M ,  HARPER JAMES M E ,  MANN RANDY W ,  MILES GLEN L ,  RAKOWSKI DONALD W D

IPC: C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  C30B31/02

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10 atoms/cm . The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700 DEG C, and more preferably between about 600-700 DEG C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900 DEG C.

公开(公告)号：SG77259A1

公开(公告)日：2000-12-19

申请号：SG1999003558

申请日：1999-07-17

Applicant: IBM

Inventor： ALLEN ARCHIBALD ,  WHITE FRANCIS R ,  RANKIN JED H ,  MANN RANDY W ,  LASKY JEROME B

IPC: H01L21/285 ,  H01L21/28 ,  H01L21/311

Abstract: A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.

公开(公告)号：DE102007007132A1

公开(公告)日：2007-09-13

申请号：DE102007007132

申请日：2007-02-13

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： GABOR ALLEN H ,  MANN RANDY W ,  SCHEER STEVEN ,  SCHROEDER UWE PAUL

IPC: H01L27/11 ,  H01L21/28 ,  H01L21/8244 ,  H01L27/112

Abstract: The arrangement has a line (126) with a rectangular tip (128) that is provided opposite to another rectangular tip (124) of another line (122) for forming a tip-to-tip characteristic (120), where the two lines are formed as an individual continuous line in a lithographic step. A contact-like characteristic is formed on the individual continuous line for separation of the individual continuous line. The two rectangular tips of the two lines are provided in another lithographic step. The two lines include polysilicon conductor, where the two lines overlap a diffusion region, respectively. An independent claim is also included for the production of a semiconductor arrangement.

公开(公告)号：MY122155A

公开(公告)日：2006-03-31

申请号：MYPI9904298

申请日：1999-10-06

Applicant: IBM

Inventor： BRACCHITTA JOHN A ,  MANN RANDY W ,  OPPOLD JEFFREY H

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/768 ,  H01L29/00 ,  H01L29/76 ,  H01L31/119

Abstract: A SEMICONDUCTOR INTEGRATED CIRCUIT MEMORY CELL, INCLUDING AT LEAST THREE TRANSISTORS (20, 21. 22) AND A CAPACITOR (10) TO FORM A DRAM. THE MEMORY CELL IS FABRICATED ON A SEMICONDUCTOR SUBSTRATE INCLUDING IMPURITY REGIONS (5), AND USING TWO SEMICONDUCTOR FILMS (6, 9), WITH DIELECTRIC FILMS (16) BETWEEN THE SEMICONDUCTOR FILMS. THE CAPACITOR CONTAINS TWO ELECTRODES. A SUBSTRATE IMPURITY REGION FORMS ONE OF THE ELECTRODES; THE OTHER ELECTRODE IS A SEMICONDUCTOR FILM WHICH CONNECTS THE GATE OF ONE DEVICE TO AN IMPURITY REGION OF ANOTHER. THE METHOD FOR MANUFACTURING THE ABOVE-DESCRIBED INTEGRATED CIRCUIT, WHICH MAY BE USED FOR THE MANUFACTURE OF SIMILAR CIRCUITS, IS ALSO DISCLOSED.

公开(公告)号：CA2043172A1

公开(公告)日：1991-12-29

申请号：CA2043172

申请日：1991-05-24

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  MANN RANDY W ,  PARRIES PAUL C ,  SPRINGER JULIE A

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which the devices are formed. A layer of silicon is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions to be connected. The etch-stop material at those regions is then removed. Following this a high-conductivity material, which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions.