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公开(公告)号:DE69929496D1
公开(公告)日:2006-04-06
申请号:DE69929496
申请日:1999-03-09
Applicant: IBM
Inventor: EDELSTEIN DANIEL CHARLES , HARPER JAMES MCKELL EDWIN C O , HU CHAO-KUN , SIMON ANDREW H , UZOH CYPRIAN EMEKA
IPC: H01L23/52 , H01L23/532 , H01L21/3205 , H01L21/768
Abstract: The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper conductor body and the electronic device for improving the electromigration resistance, the adhesion property and other surface properties of the interconnection structure. The present invention also discloses methods for forming an interconnection structure for providing electrical connections to an electronic device by first depositing a seed layer of copper alloy or other metal that does not contain copper on an electronic device, and then forming a copper conductor body on the seed layer intimately bonding to the layer such that electromigration resistance, adhesion and other surface properties of the interconnection structure are improved.
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公开(公告)号:MY121455A
公开(公告)日:2006-01-28
申请号:MYPI20005562
申请日:2000-11-28
Applicant: IBM
Inventor: WALTON ERICK GREGORY , UZOH CYPRIAN EMEKA , CHUNG DEAN S , COLLINS LARA SANDRA , CORBIN WILLIAM E , DELIGIANNI HARIKLIA , EDELSTEIN DANIEL CHARLES , FLUEGEL JAMES E , KOREJWA JOSEF WARREN , LOCKE PETER S
Abstract: AA METAL PLATING APPARATUS IS DESCRIBED WHICH INCLUDES A COMPRESSIBLE MEMBER HAVING A CONDUCTIVE SURFACE COVERING SUBSTANTIALLY ALL OF THE SURFACE OF THE SUBSTRATE TO BE PLATED. THE PLATING CURRENT IS THEREBY TRANSMITTED OVER A WIDE AREA OF THE SUBSTRATE, RATHER THAN A FEW LOCALIZED CONTACT POINTS. THE COMPRESSIBLE MEMBER IS POROUS SO AS TO ABSORB THE PLATING SOLUTION AND TRANSMIT THE PLATING SOLUTION TO THE SUBSTRATE. THE WAFER AND COMPRESSIBLE MEMBER MAY ROTATE WITH RESPECT TO EACH OTHER. THE COMPRESSIBLE MEMBER MAY BE AT CATHODE POTENTIAL OR MAY BE A PASSIVE CIRCUIT ELEMENT.
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公开(公告)号:AU2002241147A1
公开(公告)日:2003-03-03
申请号:AU2002241147
申请日:2002-03-21
Applicant: IBM
Inventor: DEV PRAKASH , EDELSTEIN DANIEL CHARLES , SHAFER PADRAIC , SIMPSON ALEXANDER , LOW KIA-SENG , WRSCHKA PETER , CONTI RICHARD , DOBUZINSKY DAVID MARK , LEE GILL
IPC: H01L21/28 , H01L21/316 , H01L23/532 , H01L29/51
Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.
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公开(公告)号:DE10106161A1
公开(公告)日:2001-09-13
申请号:DE10106161
申请日:2001-02-10
Applicant: IBM
Inventor: DAVIS CHARLES R , EDELSTEIN DANIEL CHARLES , HAY JOHN C , HEDRICK JEFFREY C , JAHNES CHRISTOPHER , MC GAHAY VINCENT , NYE HENRY
IPC: H01L21/768 , H01L21/3205 , H01L23/52 , H01L23/522 , H01L23/532
Abstract: Planar layer for conductors, includes numerous connecting lines separated from each other by dielectric. This has relatively low: dielectric constant and modulus of elasticity. A planar, perforated dielectric film layer included, has a higher modulus of elasticity. One of the conductor- and the perforated layers, is located on an integrated circuit substrate, defining a first layer. The other conductor- and perforated layer is located on the first, such that perforations make selective contact with conductors of the conductor layer.
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公开(公告)号:MY118419A
公开(公告)日:2004-10-30
申请号:MYPI20001978
申请日:2000-05-08
Applicant: IBM
Inventor: EDELSTEIN DANIEL CHARLES , MCGAHAY VINCENT , NYE HENRY A III , OTTEY BRIAN R , PRICE WILLIAM H
IPC: H01L21/4763 , H01L23/52 , H01L21/3205 , H01L21/60 , H01L23/485
Abstract: A STRUCTURE COMPRISING A LAYER OF COPPER, A BARRIER LAYER, A LAYER OF ALCU, AND A PAD-LIMITING LAYER, WHEREIN THE LAYER OF ALCU AND BARRIER LAYER ARE INTERPOSED BETWEEN THE LAYER OF COPPER AND PAD-LIMITING LAYER. (FIGURE 2)
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公开(公告)号:SG77224A1
公开(公告)日:2000-12-19
申请号:SG1999001210
申请日:1999-03-22
Applicant: IBM
Inventor: EDELSTEIN DANIEL CHARLES , HARPER JAMES MCKELL EDWIN , KU CHAO-KUN , SIMONS ANDREW H , UZOH CYPRIAN EMEKA
IPC: H01L21/3205 , H01L23/52 , H01L21/768 , H01L23/532 , H01L23/525
Abstract: The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper conductor body and the electronic device for improving the electromigration resistance, the adhesion property and other surface properties of the interconnection structure. The present invention also discloses methods for forming an interconnection structure for providing electrical connections to an electronic device by first depositing a seed layer of copper alloy or other metal that does not contain copper on an electronic device, and then forming a copper conductor body on the seed layer intimately bonding to the layer such that electromigration resistance, adhesion and other surface properties of the interconnection structure are improved.
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公开(公告)号:AU1330897A
公开(公告)日:1998-07-15
申请号:AU1330897
申请日:1996-12-16
Applicant: IBM
Inventor: ANDRICACOS PANAYOTIS CONSTANTI , DELIGIANNI HARIKLIA , DUKOVIC JOHN OWEN , HORKANS WILMA JEAN , UZOH CYPRIAN EMEKA , WONG KWONG HON , HU CHAO-KUN , EDELSTEIN DANIEL CHARLES , RODBELL KENNETH PARKER , HURD JEFFERY LOUIS
IPC: C25D7/12 , H01L21/28 , H01L21/288 , H01L21/768 , H01L23/532
Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches.
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