公开(公告)号：JP2000298625A

公开(公告)日：2000-10-24

申请号：JP2000038187

申请日：2000-02-10

Applicant: ST MICROELECTRONICS SRL

Inventor： MODELLI ALBERTO

IPC: G06F11/10 ,  G06F12/16 ,  G11C11/56 ,  H03M13/09 ,  H03M13/11

Abstract: PROBLEM TO BE SOLVED: To correct single or plural error bits with the minimum number of correction bits by allocating an error code to a single error for every set of the bits of a binary word and allocating error codes allocated to the individual errors of a partial set at every partial set of multiplex errors. SOLUTION: An error code which is not allocated to other errors is allocated to a single error for the respective sets of the bits of a binary word. An error code depending on an error code allocated to the individual errors of partial sets themselves for the respective partial sets of the multiplex errors. When the error code is previously allocated to the other error, the error code allocated to the partial set or the error code allocated to the single error of the partial set itself is denied. The new error code is allocated to the single error associated with the denied error code. The correction circuit 110 is provided with a decoding means 112 receiving a check word obtained in a decoding process as input and outputting a binary correction string.

公开(公告)号：JP2000183348A

公开(公告)日：2000-06-30

申请号：JP34999899

申请日：1999-12-09

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a MOS gate power device with low output resistance. SOLUTION: A MOS gate power device is provided with plural element function units. The element function units are provided with first conductivity- type main body regions 3 formed in second conductivity-type semiconductor material layers 2, 21, 22 and 23. Plural first conductivity-type impurity addition regions 20, 201 and 202 are formed in the semiconductor material layers 2, 21, 22 and 23, and the impurity addition regions 20, 201 and 202 are arranged below the respective main body regions 3 and are detached from the adjacent impurity addition regions by the semiconductor material layers 2, 21, 22 and 23.

公开(公告)号：JP2000174626A

公开(公告)日：2000-06-23

申请号：JP33007299

申请日：1999-11-19

Applicant: ST MICROELECTRONICS SRL

Inventor： OTTINI DANIELE ,  BRUCCOLERI MELCHIORRE ,  BOLLATI GIACOMINO ,  DEMICHELI MARCO

IPC: H03M1/36 ,  H03M1/08 ,  H03M1/12

Abstract: PROBLEM TO BE SOLVED: To provide a flash analog/digital converter capable of outputting a temperature measurement digital code. SOLUTION: This flash analog/digital converter is provided with a bank composed of comparators (COMPi) provided with differential output for generating a temperature measurement code and 3-input (A, B and C) logical NOR gates (NORj) and is provided with a passive interface respectively composed of the plural pieces of voltage dividers (Ra-Rb) connected between the non- inverted output (out-p) of the respective comparators (COMPi) and the inverted output (out-n) of the comparators (COMPi+1) of the higher order of the bank. The corresponding logical NOR gate (NORj) of the bank is provided with first input (A) connected to the inverted output (out-n) of the respective comparators (COMPi-1), second input (B) connected to the non-inverted output (out-p) of the comparators (COMPi) of the higher order and third input (C) connected to the intermediate tap of the voltage dividers (Ra-Rb).

公开(公告)号：JP2000173186A

公开(公告)日：2000-06-23

申请号：JP34210599

申请日：1999-12-01

Applicant: ST MICROELECTRONICS SRL

Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  OTTINI DANIELE ,  SAVO ALESSANDRO

IPC: G11B20/10 ,  G11B20/00 ,  H03M1/10 ,  H03M1/12 ,  H04L27/08

Abstract: PROBLEM TO BE SOLVED: To prevent the generation of accidental patterns in a frequency domain by individually controlling two identical offest compensating circuits for two ATOD converters. SOLUTION: An interleave type ATOD converter is constituted of two identical analog digital converters, i.e., one for even bit EVEN-S signal path and one for ATOD-EVEN and odd bit ODD-S signal path and an ATOD-ODD. The offsets of digital analog converters included in the ATOD-EVEN and the ATOD-ODD are independently compensated for by the loop constituted of offset compensation stages and OFFSET-EVEN-STAGE and OFFSET-ODD- STAGE controlled by a digital post process blocks through a dedicated digital analog converter DA-OFF-E and a DAC-OFF-O.

公开(公告)号：JP2000164841A

公开(公告)日：2000-06-16

申请号：JP28993099

申请日：1999-10-12

Applicant: ST MICROELECTRONICS SRL

Inventor： POLMAN ALBERT ,  HAMELIN NICHOLAS ,  KIK PETER ,  COFFA SALVATORE ,  FRISINA FERRUCCIO ,  SAGGIO MARIO

IPC: H01L31/108 ,  G01J1/02 ,  G02B6/12 ,  H01L27/14 ,  H01L31/0352 ,  H01L31/103

Abstract: PROBLEM TO BE SOLVED: To obtain an infrared detector device, exhibiting a high efficiency of transfer from infrared radiation to electrical currents by a semiconductor material. SOLUTION: An infrared detector device 1 is provided with P-N junctions 9 and 10, comprised of a first semiconductor material region 9 doped with rare-earth ions and a second semiconductor material region 10 of the oppositely doped type P. The detector device extends on a substrate 2, including a reflection layer 4 and is provided with a wave guide path 8 formed by protrusions whose range in horizontal direction is demarcated by an oxide a region for protection and containment. At least a part of the wave guide path 8 is formed of a P-N junction and has an end to which light to be detected is supplied. The detector device has electrodes 18 and 13, placed on the side and top of the wave guide path 8 and enables efficient collection of charge carriers produced by optical transfer.

公开(公告)号：JP2000133729A

公开(公告)日：2000-05-12

申请号：JP30259599

申请日：1999-10-25

Applicant: ST MICROELECTRONICS SRL

Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  GALBIATI NADIA ,  VAJANA BRUNO

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To enable integration of all together a nonvolatile memory cell and a high- speed transistor subjected to salicide processing, by forming firstly the region to form a high-voltage transistor, and by forming thereafter the region to form a low-voltage transistor. SOLUTION: Into a sacrificial oxide layer 10 present on a substrate 2, N-type ionized dopants are injected using a mask for forming an H-HV region of a high-voltage(HV) PMOS transistor. Then, after masking the entire surface of a wafer 1 while leaving an HV active region and an array active region, P-type ionized dopants are injected thereinto to form a P-HV region 13 of an HV transistor and form a P-matrix region 14 of a memory cell. Subsequently, N-type ionized dopants are injected into the layer 10, using a mask to form an N-LV region of a low-voltage(LV) PMOS transistor. Continuously, after masking the entire surface of the wafer 1, leaving an LV active region, P-type ionized dopants 18 are injected thereinto to form P-LV region 19 of an L V-NMOS transistor.

公开(公告)号：JP2000124335A

公开(公告)日：2000-04-28

申请号：JP28933699

申请日：1999-10-12

Applicant: ST MICROELECTRONICS SRL

Inventor： BALDI LIVIO ,  MAURELLI ALFONSO

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a low-cost OTP memory. SOLUTION: In manufacturing an integrated semiconductor device, having at least a nonvolatile floating gate memory cell 20 and at least a logic transistor 10 between a step of selectively etching and moving a dielectric layer 7 on a region for forming the logic transistor 10 and a first polysilicon layer 3 and a step of depositing a second polysilicon layer 11, a first substep of removing a first gate oxide layer 2 at the logic transistor 10 region and a second substep of growing a second gate oxide layer 9 on this region are provided, so as to make the second gate oxide layer 9 different from the first gate oxide layer 2.

公开(公告)号：JP2000058803A

公开(公告)日：2000-02-25

申请号：JP21892299

申请日：1999-08-02

Applicant: ST MICROELECTRONICS SRL

Inventor： MASTROMATTEO UBALDO ,  VILLA FLAVIO ,  BARLOCCHI GABRIELE

IPC: H01L21/316 ,  H01L21/762 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To allow a wider range of selections in the dimensional ratio between a trench and a pillar, enable a required crystal quality of an epitaxial layer to be achieved and ensure a continuous embedded oxide layer. SOLUTION: This manufacturing method has a process to perform selective anisotropic etching to form a plurality of trenches 16 that extend from the main surface 3 of a substrate 2 in the substrate 2 and form a plurality of portions therebetween, a process to perform selective anisotropic etching starting at a predetermined distance from the main surface to enlarge the plurality of trenches so that the plurality of portions 18' between adjacent trenches 16 have a reduced thickness, a process to substantially perform selective oxidation starting at the above predetermined distance to convert the plurality of portions of the substrate 2 that were made thinner to silicon dioxide and fill the plurality of trenches 16 with silicon dioxide, and a process to epitaxially grow a silicon layer on the above main surface of the substrate 2.

公开(公告)号：JP2000056946A

公开(公告)日：2000-02-25

申请号：JP12688799

申请日：1999-05-07

Applicant: ST MICROELECTRONICS SRL

Inventor： SAVO PIERANDREA ,  ZANGRANDI LUIGI ,  MARCHESES STEFANO

IPC: G06F7/505 ,  G06F7/00 ,  G06F7/50 ,  G06F7/509

Abstract: PROBLEM TO BE SOLVED: To provide a digital accumulator operatable at a high speed in a wide dynamic range. SOLUTION: A digital accumulator 10 contains a first adder stage 15 where an input addend is added to the least significant value of the output of the accumulator at a previous clock cycle. The accumulator contains at least one second stage and it has an incremental/decremental unit means 18 for executing an incremental, decremental or identification operation on the most significant output of the accumulator. The incremental/decremental unit means contains a logic means for triggering the incremental, decremental or identification operation on the most significant output of the accumulator based on decision by a result obtained at the previous clock cycle.

公开(公告)号：JPH11345468A

公开(公告)日：1999-12-14

申请号：JP12604599

申请日：1999-05-06

Applicant: ST MICROELECTRONICS SRL

Inventor： MASTROMATTEO UBALDO ,  MURARI BRUNO ,  VIGNA BENEDETTO ,  ZERBINI SARAH

IPC: G11B5/596 ,  G11B5/55 ,  G11B5/58 ,  G11B21/10 ,  H02N1/00

Abstract: PROBLEM TO BE SOLVED: To manufacture a read/write unit without generating offset and residual stress as much as possible. SOLUTION: An integrated device 54 having a micro-actuator 10 is formed on a semiconductor material wafer 29, and immovable structures 45, 47 consisting of organic material are formed on the wafer 29, a fixing flange 51 integrated with the micro-actuator 10 and an electric connection part for connecting the integrated device 54 to a read/write head are formed simultaneously, a converter 6 supporting the read/write head is connected to the fixing flange 51, the electric connection part is connected to the read/write head, and the wafer is cut to a dice, an actuator unit is connected to a suspension, and the immovable structures 45, 47 are removed.