公开(公告)号：EP1981316A3

公开(公告)日：2009-11-04

申请号：EP08251323.5

申请日：2008-04-04

Applicant: Kabushiki Kaisha Toshiba

Inventor： Suzuki, Ryota c/o Toshiba Corporation ,  Tanabe, Masahiro c/o Toshiba Corporation ,  Nakada, Taihei c/o Toshiba Corporation ,  Kumamoto, Tsuyoshi c/o Toshiba Corporation ,  Yamashita, Yuusuke c/o Toshiba Corporation

IPC: H05K1/02

CPC classification number: H05K1/0251 ,  H05K1/0222 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

Abstract: A multilayer high-frequency circuit board includes a signal line layer (102) in which a high-frequency signal line (11) is formed, ground layers (101, 103) which are laminated on both sides of the signal line layer, and an interlayer circuit which is provided in the signal line layer and which includes a ground connecting portion (13) connected to the ground layers and a signal line connecting portion (12) connected to the signal line. The interlayer circuit is characterized in that one of the signal line connecting portion and the ground connecting portion surrounds an outer periphery of the other concentrically with the one being separated from the outer periphery of the other along the signal line layer, and an inner periphery of the one and the outer periphery of the other have a similar shape excluding a complete circle.

公开(公告)号：EP1809083A3

公开(公告)日：2007-07-25

申请号：EP07001746.2

申请日：2002-03-13

Applicant: Ibiden Co., Ltd.

Inventor： Toyoda, Yukihiko ,  Kawamura, Yoichiro ,  Ikeda, Tomoyuki

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/116 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/068 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09745 ,  H01L2924/00

Abstract: A multilayered printed circuit board (200) comprising a substrate and, as serially built up thereon, a conductor circuit and an interlaminar resin insulating layer in an alternate fashion and in repetition, and a solder resist layer (114) formed further thereon as an outermost layer, with a connection of said conductor circuits through said interlaminar resin insulating layer being performed by a via-hole, wherein via-holes in different level layers among said via-holes (1072) are piled on one another, and among said piled via-holes, the via-hole (1071) in the uppermost level has a concave portion formed thereon.

Abstract translation: 一种多层印刷电路板（200），其包括基板和，为顺序建立在其上，导体电路和以交替的方式重复的层间树脂绝缘层和阻焊剂在其上形成进一步作为最外层（114） 层，用的连接通过所述层间树脂绝缘层的导体电路由一个通孔，其中通孔中在不同级别层中的所述通孔（1072）是在彼此堆积执行，并且经由所述堆积中 在最上层的通孔1071上形成有凹部。

公开(公告)号：EP1545175A3

公开(公告)日：2007-05-30

申请号：EP04257610.8

申请日：2004-12-08

Applicant: Endicott Interconnect Technologies, Inc.

Inventor： Larnerd, James M. ,  Lauffer, John M. ,  Markovich, Voya R. ,  Papathomas, Kostas I.

IPC: H05K3/42 ,  H05K1/11 ,  H01L23/498

CPC classification number: H05K3/429 ,  H01L2224/13 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/421 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/09845

Abstract: A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste (61). In the case of the latter, it is also possible to provide a top covering conductive layer (63) over the paste, e.g., to serve as a pad or the like on the board's external surface.

公开(公告)号：EP1545175A2

公开(公告)日：2005-06-22

申请号：EP04257610.8

申请日：2004-12-08

Applicant: Endicott Interconnect Technologies, Inc.

Inventor： Larnerd, James M. ,  Lauffer, John M. ,  Markovich, Voya R. ,  Papathomas, Kostas I.

IPC: H05K3/42 ,  H05K1/11 ,  H01L23/498

CPC classification number: H05K3/429 ,  H01L2224/13 ,  H05K1/113 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/421 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/09845

Abstract: A method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent layers and the other connects two adjacent layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste (61). In the case of the latter, it is also possible to provide a top covering conductive layer (63) over the paste, e.g., to serve as a pad or the like on the board's external surface.

Abstract translation: 在哪一种制造印刷电路板的方法，导电通孔被板的结构的两个介电层内形成，以连接指定导电层。 一个孔连接两个相邻的层和其他连接两个相邻层，包括通过另一个孔连接在所述导电层中的一个。 因此，它可以连接使用一个或多个孔全部三个导电层。 将所得的孔可填充，E. G.，用金属镀敷，或导电或其他非导电性糊剂（61）。 在后者的情况下，因此有可能以提供对膏的顶部覆盖导电层（63），E. G.，以用作垫或在板的外表面等。

公开(公告)号：EP1286579A4

公开(公告)日：2005-03-23

申请号：EP02705111

申请日：2002-03-13

Applicant: IBIDEN CO LTD

Inventor： TOYODA YUKIHIKO ,  KAWAMURA YOICHIRO ,  IKEDA TOMOYUKI

IPC: H01L21/48 ,  H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K3/28 ,  H05K3/46

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/116 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/068 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09745 ,  H01L2924/00

Abstract: A multilayer printed wiring board (100) which is excellent in reliability because of the short wiring distance of a conductor circuit, high freedom of conductor circuit design, and little possibility of cracks developing in an interlayer resin insulation layer in the vicinity of a via hole, and which comprises conductor circuits (105) and interlayer resin insulation layers (102) sequentially laminated on a substrate (101), conductor circuits sandwiching an interlayer resin insulation layer being connected via a via hole (107), characterized in that via holes in different hierarchies out of all the via holes are formed to be in a stack via structure, and at least one via hole (1072) out of the above via holes in different hierarchies has a land diameter different from those of other via holes (1071, 1073).

Abstract translation: 由于导体电路的布线距离短，导体电路设计的自由度高，在通孔附近的层间树脂绝缘层中产生裂纹的可能性小，因此可靠性优异的多层印刷布线板（100） （101）上依次层叠有导体电路（105）和层间树脂绝缘层（102），夹着层间树脂绝缘层的导体电路通过通孔（107）连接，其特征在于， 所有通孔中的不同层次形成为堆叠通孔结构，并且不同层次中的上述通孔中的至少一个通孔（1072）具有不同于其他通孔（1071， 1073）。

公开(公告)号：EP1157459B1

公开(公告)日：2002-11-27

申请号：EP00908800.6

申请日：2000-02-23

Applicant: FORMFACTOR, INC.

Inventor： MILLER, Charles, A.

IPC: H03H7/38

CPC classification number: H05K1/025 ,  H01L2224/48091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H03H7/0115 ,  H03H7/38 ,  H03H2001/0085 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/113 ,  H05K1/116 ,  H05K1/162 ,  H05K3/3421 ,  H05K3/429 ,  H05K2201/09263 ,  H05K2201/09454 ,  H05K2201/09672 ,  H05K2201/09727 ,  H05K2201/10689 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of optimizing the frequency response of an interconnect system of the type which conveys high frequency signals between bond pads of separate integrated circuits (ICs) mounted on a printed circuit board (PCB) through inductive conductors, such as bond wires and package legs, and a trace on the surface of the PCB. To improve the interconnect system, capacitance is added to the trace and inductance is added to the conductors, with the added trace capacitance and conductor inductance being appropriately sized relative to one another and to various other interconnect system impedances to optimize the interconnect system impedance matching frequency response.

公开(公告)号：EP0817548A1

公开(公告)日：1998-01-07

申请号：EP96942586.7

申请日：1996-12-19

Applicant: IBIDEN CO., LTD.

Inventor： MORI, Yoji ,  KAWAMURA, Yoichiro

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/116 ,  H05K1/0201 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/09881 ,  Y10T29/49126 ,  Y10T428/24917

Abstract: A printed wiring board in which an opening existing around a pad which is a photovia land is arranged so that it is not overlapped with the pad, the area of an opening existing around a pad and that of another opening are equalized, the quantity of resin which is filled in each opening or is equalized throughout a printed wiring board and the quantity of resin overflowing from each opening or when resin is filled in each opening or is uniformed is provided. According to such a printed wiring board, a reliable printed wiring board wherein secure connection is enabled without causing disconnection can be realized when a circuit pattern provided on an interlayer insulating board formed on the printed wiring board and a conductor pad are connected by arranging an opening existing around a conductor pad so that it is not overlapped with the conductor pad and substantially equalizing the quantity of resin which is filled in an opening around a conductor pad and that of resin which is filled in another opening.

Abstract translation: 印刷电路板，其中存在于作为光电二极管的焊盘周围的开口布置成使其不与焊盘重叠，存在于焊盘周围的开口的面积和另一个开口的面积相等，树脂的量 填充在每个开口中或在整个印刷线路板上均匀化，并且设置从每个开口溢出的树脂量或当树脂在每个开口中填充或均匀时。 根据这样的印刷电路板，当通过布置开口来连接设置在形成在印刷线路板上的层间绝缘板上的电路图案和导体焊盘时，可以实现其中安全连接不会导致断开的可靠的印刷线路板 存在于导体焊盘周围，使得其不与导体焊盘重叠，并且基本上均匀地填充在导体焊盘周围的开口中的树脂的量和填充在另一个开口中的树脂的量。

公开(公告)号：EP0329414A2

公开(公告)日：1989-08-23

申请号：EP89301441.5

申请日：1989-02-15

Applicant: BICC Public Limited Company

Inventor： Lawrence, Howard

IPC: H05K1/00 ,  H05K3/10 ,  H05K3/36 ,  H05K3/40 ,  H05K1/11

CPC classification number: H05K3/326 ,  H05K1/0287 ,  H05K1/0298 ,  H05K1/118 ,  H05K3/0058 ,  H05K3/306 ,  H05K3/4046 ,  H05K3/4611 ,  H05K2201/091 ,  H05K2201/09454 ,  H05K2201/096 ,  H05K2201/09945 ,  H05K2201/10303 ,  H05K2201/1059 ,  H05K2201/2009

Abstract: A printed circuit board which is of such a construction that patterns of electrically conductive strips and/or pads of either standard or non-standard form can be readily provided comprises a rigid board 1 of which at least the major surfaces are of electrically insulating material, which has extending through the board a multiplicity of holes 2 arranged in a pattern of rows and columns and which carries on one or each of its major surfaces a multiplicity of annular metal islands 3 each bounding a hole in the board and discrete with respect to the other annular islands. The rigid board 1 may also carry on said one or each of its major surfaces supplementary metal islands 4 and 5 each positioned between and discrete with respect to annular islands bounding adjacent holes in the rigid board. A circuit of either a standard or non-standard pattern can be formed by electrically interconnecting selected adjacent metal islands 3, 4 and 5 with local deposits of material of high electrical conductivity in such a way as to bridge the gap between adjacent islands. The local deposits may be effected manually but are preferably effected automatically using a modified computer aided design plotter or an automatic fluid dispensing machine.

Abstract translation: 具有这样一种结构的印刷电路板可以容易地提供标准或非标准形式的导电条和/或垫的图案，其包括刚性板1，其至少主表面是电绝缘材料， 它具有多个沿行和列排列的孔2，并在其一个或多个主表面上承载多个环形金属岛3，每个环形金属岛3在板上限定一个孔并相对于 其他环形岛。 刚性板1还可以在所述一个或每个主表面上承载辅助金属岛4和5，每个补充金属岛4和5位于限定刚性板中的相邻孔的环形岛之间并且相对于环岛独立。 标准或非标准图案的电路可以通过将选定的相邻金属岛3,4和5与局部高电导率材料沉积物电连接以形成桥接相邻岛之间的间隙来形成。 局部沉积物可以手动进行，但优选使用改进的计算机辅助设计绘图仪或自动流体分配机自动进行。

公开(公告)号：EP0180183A2

公开(公告)日：1986-05-07

申请号：EP85113697.8

申请日：1985-10-28

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Igarashi, Yutaka ,  Hiraoka, Masaru

IPC: H05K3/46

CPC classification number: H05K1/116 ,  H05K1/0287 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/09609 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/09945 ,  H05K2201/10689

Abstract: A multilayer printed wiring board comprises at least one layer with interlayer connection pattern (200, 300) at the basic grids. The interlayer connection pattern (200, 300) has a clearance (62, 204, 304) when a small diameter through hole (60B) is formed and has a land part (63, 205, 303) contacted to the through hole wall (61A) when a large diameter through hole (60A) is formed.
In order to obtain interlayer connection or non-connection, the diameter of a through hole is varied.

Abstract translation: 多层印刷线路板包括至少一层在基本网格处具有层间连接图案（200,300）的层。 当形成小直径通孔（60B）时，层间连接图案（200,300）具有间隙（62,204,304），并且具有与通孔壁（61A）接触的接合部分（63,205,303） ）形成大直径通孔（60A）。 为了获得层间连接或不连接，通孔的直径是变化的。

公开(公告)号：EP2479690B1

公开(公告)日：2017-11-01

申请号：EP12154766.5

申请日：2005-09-22

Applicant: Digi International Inc. Delaware Corporation

Inventor： Rogers, Norman L. ,  Hoffman, John W. ,  Feng, Jun ,  Krauter, Charles

IPC: G06F17/50 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00

CPC classification number: G06F17/5068 ,  H05K1/0206 ,  H05K1/029 ,  H05K1/0295 ,  H05K1/111 ,  H05K1/114 ,  H05K3/0005 ,  H05K3/0064 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09418 ,  H05K2201/09454 ,  H05K2201/09663 ,  H05K2201/09954 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2201/10636 ,  H05K2203/173 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49124

Abstract: A method and apparatus for configurable circuitry have been disclosed.