公开(公告)号：KR1020090076597A

公开(公告)日：2009-07-13

申请号：KR1020080002636

申请日：2008-01-09

Applicant: 삼성전자주식회사 ,  재단법인서울대학교산학협력재단

Inventor： 김철규 ,  권민호 ,  강윤호 ,  강윤선 ,  이태연 ,  허성 ,  김기범 ,  남성욱 ,  이동복

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/126 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16 ,  H01L45/143

Abstract: A phase change memory device and a method of manufacturing the same are provided, which can prevent misalignment problem of the bottom electrode and diffusion stopper. The phase change memory device comprises the storage node and the switching element connected to the storage node. The storage node comprises electrode and phase-change layer(30). The diffusion stopper(20) includes the silicide compound between the electrode and phase-change layer. The silicide compound includes at least one among silicide, silicide oxide, and silicide nitride. The electrode is the bottom electrode(10).

Abstract translation: 提供了一种相变存储器件及其制造方法，其可以防止底部电极和扩散塞的不对准问题。 相变存储器件包括存储节点和连接到存储节点的开关元件。 存储节点包括电极和相变层（30）。 扩散阻挡层（20）包括电极和相变层之间的硅化物。 硅化物化合物包括硅化物，硅化物氧化物和氮化硅中的至少一种。 电极是底部电极（10）。

公开(公告)号：KR1020100007255A

公开(公告)日：2010-01-22

申请号：KR1020080067813

申请日：2008-07-11

Applicant: 삼성전자주식회사

Inventor： 박경수 ,  이은경 ,  이재학 ,  최병룡 ,  정재관 ,  허성

IPC: B82B3/00 ,  C01B37/02

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L31/03529 ,  Y02E10/50 ,  Y10S977/762 ,  Y10S977/774

Abstract: PURPOSE: A silicon nano wire containing silicon nano dot is provided to produce nano wire having improve various material property by controlling size, density, crystallization, and interval. CONSTITUTION: A silica nano wire contains silicon nano dot as a nano wire containing silica. The nano wire containing the silica comprises a core portion. The core portion contains silicon-rich oxide or metal nano dot. The silicon nano dot exists inside the nano wire except for the core portion. The diameter of the silicon nano dot is 1-10nm.

Abstract translation: 目的：提供含有硅纳米点的硅纳米线，以通过控制尺寸，密度，结晶度和间隔来制备具有改善各种材料性能的纳米线。 构成：二氧化硅纳米线含有硅纳米点作为含有二氧化硅的纳米线。 含有二氧化硅的纳米线包括核心部分。 芯部分含有富含氧的氧化物或金属纳米点。 硅纳米点存在于纳米线内，除了核心部分之外。 硅纳米点的直径为1-10nm。

公开(公告)号：KR1020080079940A

公开(公告)日：2008-09-02

申请号：KR1020070020593

申请日：2007-02-28

Applicant: 삼성전자주식회사

Inventor： 정영수 ,  정형석 ,  허성 ,  백현석

IPC: H01L27/146

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966

Abstract: A CMOS semiconductor device and a manufacturing method thereof are provided to prevent reduction of performance by eliminating a reaction between heterogeneous materials. A CMOS semiconductor device includes an nMOS region and a pMOS region. A gate including a poly-Si capping layer(5) and a metal nitride layer(3a,3b) deposited under the poly-Si capping layer are formed in the nMOS region and the pMOS region, respectively. A gate insulating layer(2) is formed in a lower part of each gate of the nMOS region and the pMOS region. The metal nitride layers of the nMOS region and the pMOS region are made of a homogeneous material. The metal nitride layers of the nMOS region and the pMOS region has different work functions according to a concentration difference of impurities.

Abstract translation: 提供CMOS半导体器件及其制造方法，以通过消除异质材料之间的反应来防止性能降低。 CMOS半导体器件包括nMOS区和pMOS区。 在nMOS区域和pMOS区域分别形成包括多晶硅覆盖层（5）和沉积在多晶硅覆盖层下方的金属氮化物层（3a，3b）的栅极。 栅极绝缘层（2）形成在nMOS区域和pMOS区域的每个栅极的下部。 nMOS区域和pMOS区域的金属氮化物层由均质材料制成。 根据杂质的浓度差，nMOS区域和pMOS区域的金属氮化物层具有不同的功函数。

公开(公告)号：KR101587550B1

公开(公告)日：2016-01-22

申请号：KR1020090101733

申请日：2009-10-26

Applicant: 삼성전자주식회사

Inventor： 권영남 ,  김도환 ,  한혁수 ,  허성 ,  정지심 ,  최윤혁

IPC: H01L21/336 ,  H01L29/78

Abstract: 트랜지스터가개시된다. 개시된트랜지스터는게이트; 상기게이트와인접배치되며, 미엘린막을포함하여이루어진게이트절연막; 상기게이트절연막에의해상기게이트와이격되는채널층; 상기채널층의양측에각각접촉형성된소스및 드레인;을포함한다.

公开(公告)号：KR1020080097006A

公开(公告)日：2008-11-04

申请号：KR1020070042057

申请日：2007-04-30

Applicant: 삼성전자주식회사

Inventor： 김선정 ,  정영수 ,  박영근 ,  이은하 ,  허성 ,  최한메 ,  오세훈 ,  김영선 ,  김성태

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L29/42332 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792 ,  B82Y10/00

Abstract: A non-volatile memory device is provided to have the excellent electron storage capability by including the nano dots. The manufacturing method of the non-volatile memory device includes the step of forming the tunnel insulating layer(110) in the top of the substrate; the step of forming the charge storage layer(127) including the lanthanide nano dots(125) on the tunnel insulating layer; the step of forming the control gate layer on the charge storage layer; the step of forming a gate stack by patterning the control gate layer and the charge storage layer.

Abstract translation: 提供非易失性存储器件以通过包括纳米点具有优异的电子存储能力。 非易失性存储器件的制造方法包括在衬底的顶部形成隧道绝缘层（110）的步骤; 在隧道绝缘层上形成包含镧系元素纳米点（125）的电荷存储层（127）的步骤; 在电荷存储层上形成控制栅极层的步骤; 通过图案化控制栅极层和电荷存储层来形成栅极堆叠的步骤。

公开(公告)号：KR1020170087049A

公开(公告)日：2017-07-27

申请号：KR1020170009162

申请日：2017-01-19

Applicant: 삼성전자주식회사

Inventor： 허성 ,  김규식 ,  김남정 ,  김성헌 ,  김용성 ,  노탁균 ,  조은애 ,  선우문욱 ,  윤동진 ,  김용수 ,  박경배 ,  박용영

IPC: H01L31/04 ,  H01L31/0224 ,  H01L31/0392 ,  H01L27/146

CPC classification number: H01L27/307 ,  H01L27/14621 ,  H01L27/14643 ,  H01L27/14665 ,  H01L27/301 ,  H01L51/42 ,  H01L51/441 ,  H01L51/448 ,  H01L51/5088 ,  H01L51/5092 ,  H01L51/5096 ,  H01L51/5203 ,  H01L51/56 ,  H01L2251/301 ,  H01L2251/552 ,  Y02E10/549

Abstract: 서로마주하는제1 전극과제2 전극상기제1 전극과제2 전극사이에위치하는광전변환층및 상기광전변환층과상기제2 전극사이에위치하는버퍼층을포함하고, 상기버퍼층은실리콘나이트라이드(SiN, 0

Abstract translation: 以及位于所述光电转换层与所述第二电极之间的缓冲层，其中所述缓冲层由选自以下的材料制成：氮化硅（SiN ，0

公开(公告)号：KR101341571B1

公开(公告)日：2013-12-16

申请号：KR1020070042057

申请日：2007-04-30

Applicant: 삼성전자주식회사

Inventor： 김선정 ,  정영수 ,  박영근 ,  이은하 ,  허성 ,  최한메 ,  오세훈 ,  김영선 ,  김성태

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L29/42332 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/792

Abstract: 비휘발성메모리소자및 그제조방법이개시된다. 상기소자는란탄계나노닷을포함하는전하저장층을갖고, 상기방법은질소분위기의열처리를통해금속나노닷을갖는전하저장층을형성할수 있다. 따라서, 용이한방법으로우수한전하저장능력을갖는소자가제공될수 있다.

公开(公告)号：KR1020110045257A

公开(公告)日：2011-05-04

申请号：KR1020090101733

申请日：2009-10-26

Applicant: 삼성전자주식회사

Inventor： 권영남 ,  김도환 ,  한혁수 ,  허성 ,  정지심 ,  최윤혁

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/4232 ,  H01L21/02225 ,  H01L21/823412 ,  H01L29/41725

Abstract: PURPOSE: A transistor using a myelin layer is provided to form a gate insulating film, thereby operating a transistor with a low voltage. CONSTITUTION: A gate insulating film(130) includes a myelin layer. The gate insulating film is adjacent to a gate(120). A channel layer(140) is separated from the gate by the gate insulating film. The channel layer is formed of an organic semiconductor. A source(150) and a drain(160) are formed on both sides of the channel layer.

Abstract translation: 目的：提供使用髓磷脂层的晶体管以形成栅极绝缘膜，从而操作具有低电压的晶体管。 构成：栅绝缘膜（130）包括髓鞘层。 栅极绝缘膜与栅极（120）相邻。 沟道层（140）通过栅极绝缘膜与栅极分离。 沟道层由有机半导体形成。 源极（150）和漏极（160）形成在沟道层的两侧。

公开(公告)号：KR1020100100550A

公开(公告)日：2010-09-15

申请号：KR1020090025989

申请日：2009-03-26

Applicant: 삼성전자주식회사

Inventor： 유동철 ,  이은하 ,  이형익 ,  황기현 ,  허성 ,  최한메 ,  경용구 ,  김병주

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/02145 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28282 ,  H01L21/3141 ,  H01L27/11521 ,  H01L21/28273

Abstract: PURPOSE: A method for manufacturing a memory device is provided to prevent the leakage current of a blocking dielectric film by suppressing the interfacial reaction of an silicon oxide in a first dielectric film and an aluminum oxide in a third dielectric film. CONSTITUTION: A tunnel dielectric film(110) is formed on a substrate(10). An electric charge trapping film(120) is formed on the tunnel dielectric film. A blocking dielectric film(130) is formed on the electric charge trapping film. A first dielectric film(131) including a silicon oxide is formed on the electric charge trapping film. A second dielectric film(133) including an aluminum silicate is formed on the first dielectric film. A third dielectric layer(135) including an aluminum oxide is formed on the second dielectric film.

Abstract translation: 目的：提供一种用于制造存储器件的方法，通过抑制第三绝缘膜中的第一电介质膜和氧化铝中的氧化硅的界面反应来防止阻挡电介质膜的漏电流。 构成：在衬底（10）上形成隧道电介质膜（110）。 在隧道电介质膜上形成电荷捕获膜（120）。 在电荷捕获膜上形成阻挡电介质膜（130）。 在电荷捕获膜上形成包括氧化硅的第一电介质膜（131）。 在第一电介质膜上形成包括硅酸铝的第二电介质膜（133）。 在第二电介质膜上形成包括氧化铝的第三电介质层（135）。

公开(公告)号：KR1020090030083A

公开(公告)日：2009-03-24

申请号：KR1020070095411

申请日：2007-09-19

Applicant: 삼성전자주식회사

Inventor： 권영남 ,  이영구 ,  박종진 ,  이형익 ,  허성

IPC: H05B33/04

CPC classification number: H05B33/22 ,  H01L23/3192 ,  H01L51/5256 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/26 ,  Y10T428/31507 ,  Y10T428/31721 ,  H01L2924/00

Abstract: A passivation film for electronic device and organic light emitting display device are provided to increase the lifetime by forming the protective film with the plastic film / myeline layer. The myeline layer(221) functions as the protective film for protecting the organic light-emitting device(210). The organic light-emitting device comprises the top emission type organic light-emitting device and bottom emission type organic light-emitting device. The organic light-emitting device is driven to the active matrix mode or the passive matrix mode. The organic light-emitting device comprises the anode electrode(211) successively laminated on the top of the substrate, and the light-emitting layer(215) and cathode electrode(219). The light-emitting layer emitting the light of the predetermined color is formed between the anode electrode and cathode electrode. The hole injection layer(213) is formed between the anode electrode and light-emitting layer.

Abstract translation: 提供电子器件用钝化膜和有机发光显示器件，通过用塑料膜/线层形成保护膜来延长使用寿命。 线层（221）用作保护有机发光器件（210）的保护膜。 有机发光器件包括顶部发射型有机发光器件和底部发射型有机发光器件。 有机发光器件被驱动到有源矩阵模式或无源矩阵模式。 有机发光装置包括依次层叠在基板顶部的阳极电极（211）和发光层（215）和阴极电极（219）。 在阳极电极和阴极之间形成发射预定颜色的光的发光层。 在阳极电极和发光层之间形成空穴注入层（213）。