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    METHOD AND MATERIAL FOR INTEGRATING FLUORINE-CONTAINING DIELECTRIC
    22.
    发明专利
    METHOD AND MATERIAL FOR INTEGRATING FLUORINE-CONTAINING DIELECTRIC 失效

    公开(公告)号：JP2000082741A

    公开(公告)日：2000-03-21

    申请号：JP22393999

    申请日：1999-08-06

    Applicant: IBM

    Inventor： GRILL ALFRED ,  CHRISTOPHER VINCENT YANES ,  PATEL VISHNUBHAI V ,  CATHERINE LYNN ZENGER

    IPC: H01L21/283 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: PROBLEM TO BE SOLVED: To provide a high performance mutual connection structure whereto one or a plurality of fluorinated dielectric insulation layers and one or a plurality of conductive wiring levels electrically connected by a conductive via are provided, and a wiring level and a via are completely insulated from a fluorinated dielectric by at least one fluorine resistance capping material and/or a fluorine resistance linear material. SOLUTION: One or a plurality of fluorinated dielectric insulation layers 250 and one or a plurality of conductive wiring pattern layers 50, 60 electrically connected by conductive vias 70, 80 are provided. A conductive wiring pattern and a via are completely insulated from a fluorinated dielectric insulation layer by at least one fluorine resistance capping material selected from a group comprising Ag, Al, Al-Ti, Co, Cr, Cu, In, Ir, Mg, Mn, Pd, Pt, Sn, and oxide, nitride and silicide thereof and a mixture thereof, Si-containing DLC and Si-O containing DLC.

    AN ULTRALOW DIELECTRIC CONSTANT MATERIAL AS AN INTRALEVEL OR INTERLEVEL DIELECTRIC IN A SEMICONDUCTOR DEVICE, A METHOD FOR FABRICATING THE SAME, AND AN ELECTRONIC DEVICE CONTAINING THE SAME
    24.
    发明申请
    AN ULTRALOW DIELECTRIC CONSTANT MATERIAL AS AN INTRALEVEL OR INTERLEVEL DIELECTRIC IN A SEMICONDUCTOR DEVICE, A METHOD FOR FABRICATING THE SAME, AND AN ELECTRONIC DEVICE CONTAINING THE SAME 审中-公开
    作为半导体器件中的介电或交互介质的超导介电常数材料，其制造方法以及包含其的电子器件

    公开(公告)号：WO0243119A3

    公开(公告)日：2003-03-13

    申请号：PCT/US0150830

    申请日：2001-10-25

    Applicant: IBM

    Inventor： GRILL ALFRED ,  MEDEIROS DAVID R ,  PATEL VISHNUBHAI V

    IPC: H01L21/768 ,  C23C16/40 ,  H01L21/312 ,  H01L21/316 ,  H01L23/522 ,  H01L23/532

    CPC classification number: H01L21/02126 ,  C23C16/401 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing plasma enhanced chemical vapor deposition ("PECVD") process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, cyclic siloxanes and organic molecules containing ring structures, for instance, tetramethylcycloterasiloxane and cyclopentene oxide. To stabilize plasma in the PECVD reactor and thereby improve uniformity of the deposited film, CO2 is added to TMCTS as a carrier gas, or CO2 or a mixture of CO2 and O2 are added to the PECVD reactor.

    Abstract translation: 公开了一种使用等离子体增强化学气相沉积（“PECVD”）工艺在平行板化学气相沉积工艺中制造包含Si，C，O和H原子的热稳定超低介电常数膜的方法。 还公开了通过该方法制备的包含热稳定的超低介电常数材料的绝缘层的电子器件。 为了制造热稳定的超低介电常数膜，使用特定的前体材料，例如环状硅氧烷和含有环结构的有机分子，例如四甲基环四硅氧烷和环戊烯氧化物。 为了稳定PECVD反应器中的等离子体，从而提高沉积膜的均匀性，将CO 2作为载气添加到TMCTS中，或者将CO 2或CO 2和O 2的混合物加入到PECVD反应器中。

    27.
    发明专利
    未知

    公开(公告)号：DE19518044A1

    公开(公告)日：1995-12-14

    申请号：DE19518044

    申请日：1995-05-17

    Applicant: IBM

    Inventor： BEACH DAVID B ,  GRILL ALFRED ,  SMART CHRISTOPHER J

    IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

    Abstract: A storage capacitor having high dielectric constant materials and a method for forming same are described. The method solves the problems associated with fabrication of planar capacitors for DRAM chips constructed from inorganic oxides with perovskite structure. These materials are not readily etched by conventional ion etching techniques. These materials also react with silicon and silicon dioxide and the disclosed process avoids these interactions.

    29.
    发明专利
    未知

    公开(公告)号：AT479729T

    公开(公告)日：2010-09-15

    申请号：AT04757577

    申请日：2004-03-17

    Applicant: IBM

    Inventor： GATES STEPHEN ,  GRILL ALFRED

    IPC: C09C1/00 ,  H01L21/312 ,  H01L21/316

    Abstract: The present invention provides a multiphase, ultra low k film which exhibits improved elastic modulus and hardness as well as various methods for forming the same. The multiphase, ultra low k dielectric film includes atoms of Si, C, O and H, has a dielectric constant of about 2.4 or less, nanosized pores or voids, an elastic modulus of about 5 or greater and a hardness of about 0.7 or greater. A preferred multiphase, ultra low k dielectric film includes atoms of Si, C, O and H, has a dielectric constant of about 2.2 or less, nanosized pores or voids, an elastic modulus of about 3 or greater and a hardness of about 0.3 or greater. The multiphase, ultra low k film is prepared by plasma enhanced chemical vapor deposition in which one of the following alternatives is utilized: at least one precursor gas comprising siloxane molecules containing at least three Si-O bonds; or at least one precursor gas comprising molecules containing reactive groups that are sensitive to e-beam radiation. Electronic structures including the multiphase, ultra low k film are also disclosed.

    30.
    发明专利
    未知

    公开(公告)号：AT364903T

    公开(公告)日：2007-07-15

    申请号：AT05723468

    申请日：2005-02-22

    Applicant: IBM

    Inventor： CHU JACK ,  DEHLINGER GABRIEL ,  GRILL ALFRED ,  KOESTER STEVEN ,  OUYANG QIGING ,  SCHAUB JEREMY

    IPC: H01L31/101

    Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

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