公开(公告)号：WO2007016047A3

公开(公告)日：2008-01-03

申请号：PCT/US2006028718

申请日：2006-07-24

Applicant: IBM ,  GAIDIS MICHAEL C ,  RADENS CARL ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS L C ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

Inventor： GAIDIS MICHAEL C ,  RADENS CARL ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS L C ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: B82Y10/00 ,  H01L27/222 ,  H01L43/12

Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.

Abstract translation: 磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。 上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。

公开(公告)号：AU2021276898A1

公开(公告)日：2022-11-10

申请号：AU2021276898

申请日：2021-04-30

Applicant: IBM

Inventor： XIE RUILONG ,  RADENS CARL ,  CHENG KANGGUO ,  LI JUNTAO ,  GUO DECHAO ,  LI TAO ,  KANG TSUNG-SHENG

IPC: H01L29/78 ,  H01L21/336

Abstract: Methods and resulting structures for nanosheet devices having asymmetric gate stacks are disclosed. A nanosheet stack (102) is formed over a substrate (104). The nanosheet stack (102) includes alternating semiconductor layers (108) and sacrificial layers (110). A sacrificial liner (202) is formed over the nanosheet stack (102) and a dielectric gate structure (204) is formed over the nanosheet stack (102) and the sacrificial liner (202). A first inner spacer (302) is formed on a sidewall of the sacrificial layers (110). A gate (112) is formed over channel regions of the nanosheet stack (102). The gate (112) includes a conductive bridge that extends over the substrate (104) in a direction orthogonal to the nanosheet stack (102). A second inner spacer (902) is formed on a sidewall of the gate (112). The first inner spacer (302) is formed prior to the gate (112) stack, while the second inner spacer (902) is formed after, and consequently, the gate (112) stack is asymmetrical.

公开(公告)号：AT503252T

公开(公告)日：2011-04-15

申请号：AT07867608

申请日：2007-12-04

Applicant: IBM

Inventor： GAIDIS MICHAEL ,  CLEVENGER LAWRENCE ,  DALTON TIMOTHY ,  DEBROSSE JOHN ,  HSU LOUIS ,  RADENS CARL ,  WONG KEITH ,  YANG CHIH-CHAO

IPC: G11C19/08 ,  G11B5/008

Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.

公开(公告)号：DE10296608B4

公开(公告)日：2010-10-14

申请号：DE10296608

申请日：2002-04-08

Applicant: IBM ,  QIMONDA AG

Inventor： DYER THOMAS W ,  KUDELKA STEPHAN ,  PRAKASH JAI V C ,  RADENS CARL

IPC: H01L21/8242 ,  H01L27/108

公开(公告)号：WO2011032741A3

公开(公告)日：2012-04-05

申请号：PCT/EP2010059849

申请日：2010-07-09

Applicant: IBM ,  KRAUSE RAINER KLAUS ,  LI ZHENGWEN O ,  QUON ROGER A ,  CLEVENGER LAWRENCE A ,  PETRARCA KEVIN S ,  RADENS CARL ,  SAPP BRIAN C

Inventor： KRAUSE RAINER KLAUS ,  LI ZHENGWEN O ,  QUON ROGER A ,  CLEVENGER LAWRENCE A ,  PETRARCA KEVIN S ,  RADENS CARL ,  SAPP BRIAN C

IPC: H01L31/05 ,  H05K1/02 ,  H05K3/22

CPC classification number: H01L31/042 ,  H01L31/0465 ,  H01L31/0504 ,  H02S50/10 ,  Y02E10/50

Abstract: The invention relates to a method for manufacturing a thin-film photovoltaic cell module (10) encompassing an array of cells (100), comprising the steps of (i) providing the array of cells (100); (ii) determining, per cell (100), an electrical performance for one or more cells (100) of the array; (iii) identifying each cell (100) by its position in the array; (iv) determining one or more electrical paths (50, 52, 54) encompassing one or more of the cells (100) according to at least one optimization criterion; and (v) combining two or more cells (100) for realizing one or more electrical paths (50, 52, 54) by maintaining or establishing electrical connections (30) between individual cells (100) of the array according to the at least one optimization criterion.

Abstract translation: 本发明涉及一种用于制造包围电池阵列（100）的薄膜光伏电池模块（10）的方法，包括以下步骤：（i）提供电池阵列（100）; （ii）每个单元（100）确定阵列的一个或多个单元（100）的电性能; （iii）通过其在阵列中的位置来识别每个单元（100）; （iv）根据至少一个优化标准确定包含一个或多个所述单元（100）的一个或多个电路径（50,52,54）; 以及（v）通过根据所述至少一个维持或建立阵列的各个单元（100）之间的电连接（30），组合用于实现一个或多个电路径（50,52,54）的两个或更多个单元（100） 优化标准。

公开(公告)号：WO0227784A3

公开(公告)日：2003-04-10

申请号：PCT/US0142293

申请日：2001-09-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMA ,  RADENS CARL ,  NESBIT LARRY ,  BERGNER WOLFGANG

IPC: H01L21/8242 ,  H01L23/525

CPC classification number: H01L27/10861 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and process for semiconductor fuses and antifuses in vertical DRAMS provides fuses and antifuses in trench openings formed within a semiconductor substrate. Vertical transistors may be formed in other of the trench openings formed within the semiconductor substrate. The fuse is formed including a semiconductor plug (108) formed within an upper portion of the trench opening (110) and includes conductive leads (252, 254) contacting the semiconductor plug. The antifuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads formed over the semiconductor plug, at least one conductive lead isolated from the semiconductor plug by an antifuse dielectric. Each of the fuse and antifuse are fabricated using a sequence of process operations also used to simultaneously fabricate vertical transistors according to vertical DRAM technology, the plug forming the gate of the vertical transistor.

Abstract translation: 垂直DRAMS中的半导体熔丝和反熔丝的结构和工艺在半导体衬底内形成的沟槽开口中提供熔丝和反熔丝。 垂直晶体管可以形成在形成在半导体衬底内的其它沟槽开口中。 熔丝形成包括形成在沟槽开口（110）的上部内的半导体插塞（108），并且包括接触半导体插头的导电引线（252,254）。 反熔丝形成包括形成在沟槽开口的上部内的半导体插塞，并且包括形成在半导体插头上的导电引线，至少一个导电引线，其通过反熔丝绝缘体与半导体插塞隔离。 熔丝和反熔丝中的每一个都使用一系列工艺操作来制造，这些工艺操作也用于根据垂直DRAM技术同时制造垂直晶体管，该插头形成垂直晶体管的栅极。

公开(公告)号：WO2004066367A3

公开(公告)日：2009-05-28

申请号：PCT/US2004000968

申请日：2004-01-15

Applicant: IBM

Inventor： RADENS CARL ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A

IPC: H01L29/76 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L29/4983 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7836 ,  Y10S257/90

Abstract: A low-GIRL current MOSFET device (90) structure and a method of fabrication thereof which provides a low-GIRL current. The MOSFET device structure contains a central gate conductor (10) whose edges may slightly overlap the source/drain diffusions (88, 88), and left and right side wing gate conductors (70,70) which are separated from the central gate conductor by a thin insulating and diffusion barrier layer (50, 52).

Abstract translation: 低GIRL电流MOSFET器件（90）结构及其制造方法，其提供低GIRL电流。 MOSFET器件结构包含中心栅极导体（10），其边缘可能与源极/漏极扩散（88,88）稍微重叠，并且左右翼栅极导体（70,70）与中心栅极导体分开， 薄的绝缘和扩散阻挡层（50,52）。

公开(公告)号：WO2007127503A8

公开(公告)日：2008-09-04

申请号：PCT/US2007060564

申请日：2007-01-16

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C ,  RADENS CARL ,  WONG KWONG-HON ,  YANG CHIH-CHAO

IPC: H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L27/1203 ,  H01L21/28114 ,  H01L21/823456 ,  H01L21/84 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

Abstract translation: 晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在衬底上的第二栅电极; 以及包括与第二栅电极重叠的一对凸缘端的着陆焊盘，其中第二栅电极的结构与着陆焊盘的结构不连续。

公开(公告)号：WO2007127503A2

公开(公告)日：2007-11-08

申请号：PCT/US2007060564

申请日：2007-01-16

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C ,  RADENS CARL ,  YANG CHIH-CHAO

IPC: H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L27/1203 ,  H01L21/28114 ,  H01L21/823456 ,  H01L21/84 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.

Abstract translation: 晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

公开(公告)号：AT519228T

公开(公告)日：2011-08-15

申请号：AT00103964

申请日：2000-02-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DIVAKARUNI RAMA ,  GRUENING ULRIKE ,  KIM BYEONG Y ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

IPC: H01L27/108 ,  H01L21/8242

Abstract: A semiconductor device including a substrate. At least one pair of deep trenches is arranged in the substrate. A collar lines at least a portion of a wall of each deep trench. A deep trench fill fills each deep trench. A buried strap extends completely across each deep trench over each deep trench fill and each collar. An isolation region is arranged between the deep trenches. A dielectric region overlies each buried strap in each deep trench.