公开(公告)号：DE69322832T2

公开(公告)日：1999-08-05

申请号：DE69322832

申请日：1993-10-04

Applicant: IBM

Inventor： BEAMAN BRIAN SAMUEL ,  DOANY FUAD ELIAS ,  FOGEL KEITH EDWARD ,  HEDRICK JR JAMES LUPTON ,  LAURO PAUL ALFRED ,  NORCOTT MAURICE HEATHCOTE ,  RITSKO JOHN JAMES ,  SHI LEATHEN ,  SHIH DA-YUAN ,  WALKER GEORGE FREDERICK

IPC: G01R1/067 ,  G01R1/073 ,  H01L23/52 ,  G01R3/00 ,  G01R31/28 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

Abstract: The present invention is directed to a structure (2) for packaging electronic devices, such as semiconductor chips (36, 38), in a three dimensional structure which permits electrical signals to propagate both horizontally and vertically. The structure is formed from a plurality of assemblies (4, 6). Each assembly is formed from a substrate (8) having disposed on at least one surface a plurality of electronic devices. Each assembly is disposed in a stack of adjacent assemblies. Between adjacent assemblies there is an electrical interconnection means (49) electrically interconnecting each assembly. The electrical interconnection means is formed from an elastomeric interposer. The elastomeric interposer is formed from an elastomeric material having a plurality of electrical conductors extending therethrough, either in a clustered or un-clustered arrangement. The electrical interconnection means is fabricated having a plurality of apertures extending therethrough. The array of apertures corresponds to the array of electronic devices on the substrates. The aperture and electrical interconnection means is disposed over the array of electronic devices so that the electrical interconnection means is between adjacent electronic devices. The stack of assemblies is compressed thereby compressing the electrical interconnection means between adjacent assemblies. The substrate of each assembly is formed from a thermally conductive material such as diamond. A heat dissipation means is thermally connected to the edges of the substrate to extract heat generated within the structure. Methods for fabricating the electrical interconnection means as a stand alone elastomeric sheet are described. The ends (50, 54) of the plurality of conductors in the electrical interconnection means (49) are fabricated so that upon compression between adjacent assemblies (4, 6) there is a wiping action between the conductor ends (e.g. 50) and contact locations (e.g. 30) on the adjacent assemblies to form a good electrical contact therewith.

公开(公告)号：DE69322832D1

公开(公告)日：1999-02-11

申请号：DE69322832

申请日：1993-10-04

Applicant: IBM

Inventor： BEAMAN BRIAN SAMUEL ,  DOANY FUAD ELIAS ,  FOGEL KEITH EDWARD ,  HEDRICK JR JAMES LUPTON ,  LAURO PAUL ALFRED ,  NORCOTT MAURICE HEATHCOTE ,  RITSKO JOHN JAMES ,  SHI LEATHEN ,  SHIH DA-YUAN ,  WALKER GEORGE FREDERICK

IPC: G01R1/067 ,  G01R1/073 ,  H01L23/52 ,  G01R3/00 ,  G01R31/28 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

Abstract: The present invention is directed to a structure (2) for packaging electronic devices, such as semiconductor chips (36, 38), in a three dimensional structure which permits electrical signals to propagate both horizontally and vertically. The structure is formed from a plurality of assemblies (4, 6). Each assembly is formed from a substrate (8) having disposed on at least one surface a plurality of electronic devices. Each assembly is disposed in a stack of adjacent assemblies. Between adjacent assemblies there is an electrical interconnection means (49) electrically interconnecting each assembly. The electrical interconnection means is formed from an elastomeric interposer. The elastomeric interposer is formed from an elastomeric material having a plurality of electrical conductors extending therethrough, either in a clustered or un-clustered arrangement. The electrical interconnection means is fabricated having a plurality of apertures extending therethrough. The array of apertures corresponds to the array of electronic devices on the substrates. The aperture and electrical interconnection means is disposed over the array of electronic devices so that the electrical interconnection means is between adjacent electronic devices. The stack of assemblies is compressed thereby compressing the electrical interconnection means between adjacent assemblies. The substrate of each assembly is formed from a thermally conductive material such as diamond. A heat dissipation means is thermally connected to the edges of the substrate to extract heat generated within the structure. Methods for fabricating the electrical interconnection means as a stand alone elastomeric sheet are described. The ends (50, 54) of the plurality of conductors in the electrical interconnection means (49) are fabricated so that upon compression between adjacent assemblies (4, 6) there is a wiping action between the conductor ends (e.g. 50) and contact locations (e.g. 30) on the adjacent assemblies to form a good electrical contact therewith.

公开(公告)号：BR0101001B1

公开(公告)日：2014-11-25

申请号：BR0101001

申请日：2001-03-16

Applicant: IBM

Inventor： CHAN KEVIN K ,  JHANES CHRISTOPHER ,  SHI LEATHEN ,  SPEIDELL JAMES L ,  ZIEGLER JAMES F

IPC: H04B1/26 ,  B81B3/00 ,  B81B7/00 ,  B81C1/00 ,  H03D7/00 ,  H03H3/007 ,  H03H9/10 ,  H03H9/24 ,  H03H9/46

Abstract: Communication signal mixing and filtering systems and methods utilizing an encapsulated micro electro-mechanical system (MEMS) device. Furthermore, disclosed is a method of fabricating a simple, unitarily constructed micro electro-mechanical system (MEMS) device which combines the steps of signal mixing and filtering, and which is smaller, less expensive and more reliable in construction and operation than existing devices currently employed in the technology.

公开(公告)号：DE112012004106T5

公开(公告)日：2014-07-10

申请号：DE112012004106

申请日：2012-08-03

Applicant: IBM

Inventor： COONEY EDWARD C ,  DUNN JAMES S ,  MARTIN DALE W ,  MUSANTE CHARLES F ,  RAINEY BETH-ANN ,  SHI LEATHEN ,  SPROGIS EDMUND J ,  TSANG CORNELIA K

IPC: H01L21/60 ,  H01L21/58 ,  H01L23/48

Abstract: Verfahren zum Bonden von Substratoberflächen, gebondete Substratanordnungen sowie Entwurfsstrukturen für eine gebondete Substratanordnung. Es werden Einheiten-Strukturen (18, 19, 20, 21) eines Produkt-Chips (25) unter Verwendung einer ersten Oberfläche (15) eines Einheiten-Substrats (10) gebildet. Auf dem Produkt-Chip wird eine Verdrahtungsschicht (26) einer Zwischenverbindungsstruktur für die Einheiten-Strukturen gebildet. Die Verdrahtungsschicht wird planarisiert. Ein provisorischer Handhabungswafer (52) wird entfernbar an die planarisierte Verdrahtungsschicht gebondet. In Reaktion auf das entfernbare Bonden des provisorischen Handhabungswafers an die planarisierte erste Verdrahtungsschicht wird eine zweite Oberfläche (54) des Einheiten-Substrats, die entgegengesetzt zu der ersten Oberfläche ist, an ein endgültiges Handhabungssubstrat (56) gebondet. Anschließend wird der provisorische Handhabungswafer von der Anordnung entfernt.

公开(公告)号：DE69633998D1

公开(公告)日：2005-01-13

申请号：DE69633998

申请日：1996-09-04

Applicant: IBM

Inventor： CIPOLLA THOMAS M ,  COLGAN EVAN ,  MELCHER ROBERT L ,  MOK LAWRENCE S ,  NARAYAN CHANDRASEKHAR ,  SHI LEATHEN ,  YANG KEI-HSIUNG

IPC: G02F1/13 ,  G02F1/133 ,  G02F1/1333 ,  G02F1/136 ,  G09F9/00 ,  H04N5/74 ,  G02F1/1335 ,  H04N9/31

Abstract: A liquid crystal element, a packaging structure providing thermal and alignment control, a display device including the same, and methods of fabrication and assembly are provided. The liquid crystal element includes: a semiconductor wafer, having microcircuitry and an array of reflective pixels; a layer of electro-optical responsive liquid crystal medium, of uniform thickness, disposed on the reflective pixels; a transparent conductive layer positioned on the liquid crystal, being substantially parallel to the reflective layers, to ensure a uniform thickness of the liquid crystal; and an insulative transparent layer provided on the conductive layer. The liquid crystal element is laminated to an optically flat substrate to limit the out-of-plane distortions thereof. The structure formed by element and substrate are disposed in a substrate holder which is mounted to a wiring board, and coupled to voltage sources for actuating the liquid crystal. During mounting, an aligning fixture is used to ensure proper orientation of the element relative to the related optical elements. Once the element is positioned, a heat sink is coupled to the rear surface of the substrate holder to dissipate heat.

公开(公告)号：IE960846A1

公开(公告)日：1997-09-24

申请号：IE960846

申请日：1996-12-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  DATTA MADAV ,  DELIGIANNI HARIKLIA ,  HORKANS WILMA JEAN ,  KANG SUNG KWON ,  KWIETNIAK KEITH THOMAS ,  MATHAD GANGADHARA SWAMI ,  PURUSHOTHAMAN SAMPATH ,  SHI LEATHEN ,  TONG HO-MING

IPC: B23K35/26 ,  B23K35/00 ,  B32B15/01 ,  C22C13/00 ,  C22C13/02 ,  H01L21/60 ,  H01L23/485 ,  H01L23/488

Abstract: An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe, and NiCoFe on the adhesion/barrier layer, and lead free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.

公开(公告)号：DE69105793D1

公开(公告)日：1995-01-26

申请号：DE69105793

申请日：1991-02-06

Applicant: IBM

Inventor： HUANG WU-SONG ,  KHANDROS IGOR YAN ,  SARAF RAVI ,  SHI LEATHEN

IPC: B23K35/22 ,  B23K35/26 ,  B23K35/36 ,  B23K35/363 ,  B23K101/36 ,  C08K3/08 ,  H05K3/32 ,  H05K3/34

Abstract: An improved solder/polymer fluxless composite paste interconnection material having a low reflow temperature to form electrical contacts having good bonding strength and low contact resistance. The present pastes comprise a major proportion of a meltable metal alloy powder filler, free of noble metals and preferably free of lead, a minor proportion of a solution of a temperature-stable thermoplastic polymer having a softening temperature above the melting temperature of the metal powder filler in a volatile solvent which evaporates during reflow, and a minor proportion of a fluxing agent having a boiling point lower than the reflow temperature of the composition and higher than the melting point of the eutectic alloy powder filler. An oxide-free, partially coalesced metal alloy connection is obtained, which is polymer strengthened and reworkable at a low reflow temperature, per se, or in the presence of polymer solvent.