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    PATTERN FORMATION EMPLOYING SELF-ASSEMBLED MATERIAL
    21.
    发明申请
    PATTERN FORMATION EMPLOYING SELF-ASSEMBLED MATERIAL 审中-公开
    使用自组装材料的图案形成

    公开(公告)号：WO2009100053A2

    公开(公告)日：2009-08-13

    申请号：PCT/US2009032936

    申请日：2009-02-03

    Applicant: IBM ,  BLACK CHARLES T ,  DALTON TIMOTHY J ,  DORIS BRUCE B ,  RADENS CARL

    Inventor： BLACK CHARLES T ,  DALTON TIMOTHY J ,  DORIS BRUCE B ,  RADENS CARL

    IPC: H01L21/20

    CPC classification number: H01L21/0338 ,  B81B2203/0369 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  H01L21/0337 ,  H01L51/0017 ,  Y10S977/882 ,  Y10S977/887 ,  Y10S977/888 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24612 ,  Y10T428/24736 ,  Y10T428/24802

    Abstract: In one embodiment, hexagonal tiles encompassing a large are divided into three groups, each containing one-third of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group (01, 02, 03) are formed in a template layer (2OA, 2OB, 20C), and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self- aligned line and space structures (4OA, 5OA; 4OB, 5OB; 4OC, 50C) are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.

    Abstract translation: 在一个实施例中，包括大的六边形瓦片被分成三组，每组包含彼此分离的所有六边形瓦片的三分之一。 每个组（01,02,03）中的六边形瓦片的开口形成在模板层（20A，20B，20C）中，并且在每个开口内施加和组合一组自组装嵌段共聚物。 该过程重复三次以包含所有三组，导致在大面积上延伸的自对准图案。 在另一个实施例中，大面积被分成两个不重叠和互补组的矩形瓦片。 每个矩形区域的宽度小于自组装嵌段共聚物的顺序范围。 在每组中以顺序的方式形成自组装自对准线和空间结构（40A，50A; 40B，50B; 40C，50C），使得线和空间图形形成在延伸超过 订购。

    Nanosheet transistor with asymmetric gate stack
    23.
    发明专利
    Nanosheet transistor with asymmetric gate stack 未知

    公开(公告)号：AU2021276898A1

    公开(公告)日：2022-11-10

    申请号：AU2021276898

    申请日：2021-04-30

    Applicant: IBM

    Inventor： XIE RUILONG ,  RADENS CARL ,  CHENG KANGGUO ,  LI JUNTAO ,  GUO DECHAO ,  LI TAO ,  KANG TSUNG-SHENG

    IPC: H01L29/78 ,  H01L21/336

    Abstract: Methods and resulting structures for nanosheet devices having asymmetric gate stacks are disclosed. A nanosheet stack (102) is formed over a substrate (104). The nanosheet stack (102) includes alternating semiconductor layers (108) and sacrificial layers (110). A sacrificial liner (202) is formed over the nanosheet stack (102) and a dielectric gate structure (204) is formed over the nanosheet stack (102) and the sacrificial liner (202). A first inner spacer (302) is formed on a sidewall of the sacrificial layers (110). A gate (112) is formed over channel regions of the nanosheet stack (102). The gate (112) includes a conductive bridge that extends over the substrate (104) in a direction orthogonal to the nanosheet stack (102). A second inner spacer (902) is formed on a sidewall of the gate (112). The first inner spacer (302) is formed prior to the gate (112) stack, while the second inner spacer (902) is formed after, and consequently, the gate (112) stack is asymmetrical.

    24.
    发明专利
    未知

    公开(公告)号：AT503252T

    公开(公告)日：2011-04-15

    申请号：AT07867608

    申请日：2007-12-04

    Applicant: IBM

    Inventor： GAIDIS MICHAEL ,  CLEVENGER LAWRENCE ,  DALTON TIMOTHY ,  DEBROSSE JOHN ,  HSU LOUIS ,  RADENS CARL ,  WONG KEITH ,  YANG CHIH-CHAO

    IPC: G11C19/08 ,  G11B5/008

    Abstract: A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.

    METHOD FOR MANUFACTURING A THIN-FILM PHOTOVOLTAIC CELL MODULE ENCOMPASSING AN ARRAY OF CELLS AND PHOTOVOLTAIC CELL MODULE
    26.
    发明申请
    METHOD FOR MANUFACTURING A THIN-FILM PHOTOVOLTAIC CELL MODULE ENCOMPASSING AN ARRAY OF CELLS AND PHOTOVOLTAIC CELL MODULE 审中-公开
    制造薄膜光伏电池模块的方法，包括电池阵列和光电池模块

    公开(公告)号：WO2011032741A3

    公开(公告)日：2012-04-05

    申请号：PCT/EP2010059849

    申请日：2010-07-09

    Applicant: IBM ,  KRAUSE RAINER KLAUS ,  LI ZHENGWEN O ,  QUON ROGER A ,  CLEVENGER LAWRENCE A ,  PETRARCA KEVIN S ,  RADENS CARL ,  SAPP BRIAN C

    Inventor： KRAUSE RAINER KLAUS ,  LI ZHENGWEN O ,  QUON ROGER A ,  CLEVENGER LAWRENCE A ,  PETRARCA KEVIN S ,  RADENS CARL ,  SAPP BRIAN C

    IPC: H01L31/05 ,  H05K1/02 ,  H05K3/22

    CPC classification number: H01L31/042 ,  H01L31/0465 ,  H01L31/0504 ,  H02S50/10 ,  Y02E10/50

    Abstract: The invention relates to a method for manufacturing a thin-film photovoltaic cell module (10) encompassing an array of cells (100), comprising the steps of (i) providing the array of cells (100); (ii) determining, per cell (100), an electrical performance for one or more cells (100) of the array; (iii) identifying each cell (100) by its position in the array; (iv) determining one or more electrical paths (50, 52, 54) encompassing one or more of the cells (100) according to at least one optimization criterion; and (v) combining two or more cells (100) for realizing one or more electrical paths (50, 52, 54) by maintaining or establishing electrical connections (30) between individual cells (100) of the array according to the at least one optimization criterion.

    Abstract translation: 本发明涉及一种用于制造包围电池阵列（100）的薄膜光伏电池模块（10）的方法，包括以下步骤：（i）提供电池阵列（100）; （ii）每个单元（100）确定阵列的一个或多个单元（100）的电性能; （iii）通过其在阵列中的位置来识别每个单元（100）; （iv）根据至少一个优化标准确定包含一个或多个所述单元（100）的一个或多个电路径（50,52,54）; 以及（v）通过根据所述至少一个维持或建立阵列的各个单元（100）之间的电连接（30），组合用于实现一个或多个电路径（50,52,54）的两个或更多个单元（100） 优化标准。

    30.
    发明专利
    未知

    公开(公告)号：AT519228T

    公开(公告)日：2011-08-15

    申请号：AT00103964

    申请日：2000-02-25

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： DIVAKARUNI RAMA ,  GRUENING ULRIKE ,  KIM BYEONG Y ,  MANDELMAN JACK ,  NESBIT LARRY ,  RADENS CARL

    IPC: H01L27/108 ,  H01L21/8242

    Abstract: A semiconductor device including a substrate. At least one pair of deep trenches is arranged in the substrate. A collar lines at least a portion of a wall of each deep trench. A deep trench fill fills each deep trench. A buried strap extends completely across each deep trench over each deep trench fill and each collar. An isolation region is arranged between the deep trenches. A dielectric region overlies each buried strap in each deep trench.

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