公开(公告)号：US20180177040A1

公开(公告)日：2018-06-21

申请号：US15840598

申请日：2017-12-13

Applicant: Onkyo Corporation

Inventor： Makoto YOSHIDA

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/0225 ,  H05K1/0259 ,  H05K9/0039 ,  H05K9/006 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09354

Abstract: A multilayer substrate includes plural layers of circuit patterns. Each circuit pattern includes a ground conductor surrounding a wiring region provided with a conductive wiring pattern. Each ground conductor includes a slit connecting between the outside of the multilayer substrate and the wiring region. In the multilayer substrate, the slit of the ground conductor provided at one of adjacent two layers of the circuit patterns and the slit of the ground conductor provided at the other circuit pattern are formed at positions not overlapping with each other. That is, these slits are formed at such positions that a view in an upper-to-lower direction is blocked. The shape of the slit of each ground conductor is in such a shape that a view from an end side of the multilayer substrate to a wiring region side is blocked.

公开(公告)号：US20180138615A1

公开(公告)日：2018-05-17

申请号：US15812765

申请日：2017-11-14

Applicant: Hirose Electric Co., Ltd.

Inventor： Teppei MATSUMOTO

IPC: H01R12/72 ,  H05K1/02 ,  H01R12/75 ,  H01R12/70 ,  H05K1/18 ,  H01R13/646 ,  H05K3/18 ,  H05K3/30 ,  H01P5/08

CPC classification number: H01R12/722 ,  H01P5/085 ,  H01R9/0515 ,  H01R12/7047 ,  H01R12/75 ,  H01R13/646 ,  H05K1/0242 ,  H05K1/0253 ,  H05K1/18 ,  H05K1/181 ,  H05K3/18 ,  H05K3/301 ,  H05K2201/0919 ,  H05K2201/093 ,  H05K2201/10189 ,  H05K2201/10409

Abstract: A structure that includes a board and a connector secured to an end portion of the board. The board has a first dielectric layer, a signal pattern that is provided on the top face of the first dielectric layer, a first ground layer that is provided under the first dielectric layer and forms part of a signal transmission circuit in conjunction with the signal pattern, and a plating film formed on an end face of the end portion of the board in an area located directly under the signal pattern and includes an end face of the first ground layer. The connector has a center conductor, an outer conductor, and securing portions that secure the connector to an end portion of the board. When the connector is secured, the center conductor comes in contact with the signal pattern and the plating film comes in contact with the outer conductor.

公开(公告)号：US09792959B2

公开(公告)日：2017-10-17

申请号：US15351580

申请日：2016-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G11C5/04 ,  G11C5/06 ,  H05K1/18 ,  G11C5/02 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H05K1/02 ,  H05K3/46

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

公开(公告)号：US09681554B2

公开(公告)日：2017-06-13

申请号：US12258594

申请日：2008-10-27

Applicant: Nan-Jang Chen

Inventor： Nan-Jang Chen

IPC: H05K1/11 ,  H05K1/14 ,  H05K3/22 ,  H05K1/02

CPC classification number: H05K3/222 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/10363 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A printed circuit board is disclosed. The printed circuit board comprises a substrate having a top surface and a bottom surface. A ground plane is on the bottom surface. A signal trace is on the top surface along a first direction. At least two isolated power planes are on the top surface adjacent to opposite sides of the signal trace, respectively. A conductive connection along a second direction couples to the two power planes, across the signal trace without electrically connecting to the signal trace, wherein the signal trace doesn't directly pass over any split of the ground plane.

公开(公告)号：US09664569B2

公开(公告)日：2017-05-30

申请号：US14714005

申请日：2015-05-15

Applicant: Google Inc.

Inventor： Adam Mittleman ,  Ian Charles Smith ,  Daniel Adam Warren ,  William Raeming Dong ,  Jeff Wheeler

IPC: G01N21/00 ,  G01J5/06 ,  H05K1/02 ,  G01J5/00 ,  G01J5/10 ,  G01J5/02 ,  G01J5/04 ,  G08B13/189

CPC classification number: G01J5/06 ,  G01J5/0014 ,  G01J5/0205 ,  G01J5/04 ,  G01J5/10 ,  G08B13/189 ,  G08B13/191 ,  H05K1/0201 ,  H05K1/0298 ,  H05K2201/09063 ,  H05K2201/093 ,  H05K2201/09363 ,  H05K2201/0969 ,  H05K2201/10106 ,  H05K2201/10151 ,  H05K2201/10522 ,  H05K2201/10575 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A multilayered circuit board having a metal-free region vertically extending through at least a portion of a conductive layer, which lies generally parallel to a horizontal plane, vertically spaced from an outer surface. Heat-emitting and heat-sensitive components are mounted on the outer surface. The heat-emitting component is vertically and laterally spaced from the metal-free region, whereas the heat-sensitive component is vertically spaced and laterally aligned within the metal-free region such that the metal-free region is a thermal barrier that shields heat-sensitive component from radial heat flowing from the heat-emitting component.

公开(公告)号：US20160268309A1

公开(公告)日：2016-09-15

申请号：US15165169

申请日：2016-05-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takeshi FUKUNAGA

IPC: H01L27/12 ,  H01L51/52 ,  H01L27/32

CPC classification number: H01L51/524 ,  G01N33/497 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/3227 ,  H01L27/3262 ,  H01L27/3276 ,  H01L27/3279 ,  H01L27/3288 ,  H01L27/329 ,  H01L31/153 ,  H01L33/62 ,  H01L51/0097 ,  H01L51/5203 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/5315 ,  H01L2251/5338 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/093 ,  H05K2201/10128 ,  H05K2201/1031 ,  Y02P70/611 ,  H01L2924/00

Abstract: A light-emitting device having the quality of an image high inhomogeneity is provided. A printed wiring board (second substrate) (107) is provided facing a substrate (first substrate) (101) that has a luminous element (102) formed thereon. A PWB side wiring (second group of wirings) (110) on the printed wiring board (107) is electrically connected to element side wirings (first group of wirings) (103, 104) by anisotropic conductive films (105a, 105b). At this point, because a low resistant copper foil is'used to form the PWB side wiring (110), a voltage drop of the element side wirings (103, 104) and a delay of a signal can be reduced. Accordingly, the homogeneity of the quality of an image is improved, and the operating speed of a driver circuit portion is enhanced.

Abstract translation: 提供了具有高不均匀性的图像质量的发光装置。 面向其上形成有发光元件（102）的基板（第一基板）（101）设置有印刷布线板（第二基板）（107）。 印刷电路板（107）上的PWB侧布线（第二组布线）（110）通过各向异性导电膜（105a，105b）与元件侧布线（第一组布线）（103,104）电连接。 此时，由于低阻铜箔用于形成PWB侧布线（110），所以能够降低元件侧布线（103,104）的电压降和信号的延迟。 因此，提高了图像质量的均匀性，并且提高了驱动器电路部分的操作速度。

公开(公告)号：US09343398B2

公开(公告)日：2016-05-17

申请号：US14497825

申请日：2014-09-26

Applicant: Invensas Corporation

Inventor： Yong Chen ,  Zhuowen Sun ,  Kyong-Mo Bang

IPC: H01L23/498 ,  H05K1/02

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/181 ,  H05K1/0262 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic package can include a substrate and a microelectronic element. The substrate can include terminals comprising at least first power terminals and other terminals in an area array at a surface of the substrate. The substrate can also include a power plane element electrically coupled to the first power terminals. The area array can have a peripheral edge and a continuous gap between the terminals extending inwardly from the peripheral edge in a direction parallel to the surface. The terminals on opposite sides of the gap can be spaced from one another by at least 1.5 times a minimum pitch of the terminals. The power plane element can extend within the gap from at least the peripheral edge at least to the first power terminals. Each first power terminal can be separated from the peripheral edge by two or more of the other terminals.

Abstract translation: 微电子封装可以包括衬底和微电子元件。 衬底可以包括在衬底的表面处的区域阵列中至少包括第一电源端子和其他端子的端子。 基板还可以包括电耦合到第一电源端子的功率平面元件。 区域阵列可以具有周边边缘和在平行于表面的方向上从周边边缘向内延伸的端子之间的连续间隙。 间隙的相对侧上的端子可以彼此间隔开至少1.5倍的端子的最小间距。 功率平面元件可以在间隙内从至少外围边缘至少延伸到第一电源端子。 每个第一电源端子可以通过两个或更多其它端子与外围边缘分离。

公开(公告)号：US09337919B2

公开(公告)日：2016-05-10

申请号：US13697210

申请日：2011-05-11

Applicant: Hidekazu Kikuchi ,  Takayuki Mogi ,  Yoshiyuki Akiyama ,  Hirofumi Kawamura

Inventor： Hidekazu Kikuchi ,  Takayuki Mogi ,  Yoshiyuki Akiyama ,  Hirofumi Kawamura

IPC: H04B7/00 ,  H04B7/24 ,  H01P3/12 ,  H01P5/107 ,  H04B3/56 ,  H01R13/66 ,  H01R103/00 ,  H01R13/6461 ,  H01R24/28 ,  H01R24/76 ,  H05K1/02

CPC classification number: H01P5/02 ,  H01P1/208 ,  H01P3/12 ,  H01P3/121 ,  H01P3/165 ,  H01P5/024 ,  H01P5/082 ,  H01P5/087 ,  H01P5/1022 ,  H01P5/107 ,  H01P5/18 ,  H01P5/182 ,  H01P5/188 ,  H01R13/6461 ,  H01R13/665 ,  H01R24/28 ,  H01R24/76 ,  H01R2103/00 ,  H04B3/56 ,  H04B7/24 ,  H05K1/0225 ,  H05K1/0239 ,  H05K2201/093 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09754

Abstract: A signal transmission system including: a first connector apparatus, and a second connector apparatus that is coupled with the first connector apparatus. The first connector apparatus and the second connector apparatus are coupled together to form an electromagnetic field coupling unit, and a transmission object signal is converted into a radio signal, which is then transmitted through the electromagnetic field coupling unit, between the first connector apparatus and the second connector apparatus.

Abstract translation: 一种信号传输系统，包括：第一连接器装置和与第一连接器装置耦合的第二连接器装置。 第一连接器装置和第二连接器装置耦合在一起以形成电磁场耦合单元，并且传输对象信号被转换成无线电信号，然后通过电磁场耦合单元在第一连接器装置和 第二连接器装置。

公开(公告)号：US09326370B2

公开(公告)日：2016-04-26

申请号：US13852630

申请日：2013-03-28

Applicant: CANON KABUSHIKI KAISHA

Inventor： Yusuke Murai ,  Sou Hoshi ,  Nobuaki Yamashita

IPC: H01L23/48 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/025 ,  H01L2224/16225 ,  H05K1/0225 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/09709

Abstract: Provided is a printed circuit board capable of increasing an inductance value of a power pattern and a ground pattern while keeping a low electric resistance value of the power pattern and the ground pattern. The printed circuit board includes a printed wiring board including: a power layer having a power pattern formed therein; and a ground layer having a ground pattern formed therein. On the printed wiring board, an LSI as a semiconductor device and an LSI as a power supply member are mounted. The ground pattern has a first ground region that overlaps the power pattern as viewed from the direction perpendicular to the surface of the printed wiring board. In the first ground region, at least one defect portion is formed. In the first ground region, the defect portion forms a region that is narrower than the power pattern.

Abstract translation: 提供了能够在保持功率图案和接地图案的低电阻值的同时增加功率图案和接地图案的电感值的印刷电路板。 印刷电路板包括：印刷电路板，包括：功率层，其中形成有功率图案; 以及其中形成有接地图案的接地层。 在印刷电路板上安装作为半导体器件的LSI和作为电源部件的LSI。 接地图形具有与从印刷电路板的表面垂直的方向观察时与功率图案重叠的第一接地区域。 在第一接地区域中形成至少一个缺陷部分。 在第一接地区域中，缺陷部分形成比功率图形更窄的区域。

公开(公告)号：US20150282323A1

公开(公告)日：2015-10-01

申请号：US14663921

申请日：2015-03-20

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi Shimizu ,  Wataru Kaneda ,  Akio Rokugawa

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/0222 ,  H05K1/0225 ,  H05K1/0298 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/116 ,  H05K3/26 ,  H05K3/381 ,  H05K3/4673 ,  H05K3/4676 ,  H05K2201/0191 ,  H05K2201/0281 ,  H05K2201/029 ,  H05K2201/0293 ,  H05K2201/0347 ,  H05K2201/068 ,  H05K2201/09227 ,  H05K2201/093 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2203/0514

Abstract: A wiring board includes a first wiring layer formed on one surface of a core layer, a first insulating layer formed on the one surface of the core layer so as to cover the first wiring layer, a via wiring embedded in the first insulating layer, a second wiring layer formed on a first surface of the first insulating layer, and a second insulating layer thinner than the first insulating layer formed on the first surface of the first insulating layer so as to cover the second wiring layer. The first wiring layer comprises a pad and a plane layer provided around the pad. One end surface of the via wiring is exposed from the first surface of the first insulating layer and directly bonded to the second wiring layer. The other end surface of the via wiring is directly bonded to the pad in the first insulating layer.

Abstract translation: 布线基板包括形成在芯层的一个表面上的第一布线层，形成在芯层的一个表面上以覆盖第一布线层的第一绝缘层，嵌入第一绝缘层中的通孔布线， 第二布线层，形成在第一绝缘层的第一表面上，以及比形成在第一绝缘层的第一表面上的第一绝缘层更薄的第二绝缘层，以覆盖第二布线层。 第一布线层包括焊盘和设置在焊盘周围的平面层。 通孔布线的一个端面从第一绝缘层的第一表面露出并直接接合到第二布线层。 通孔布线的另一个端面直接接合到第一绝缘层中的焊盘。