公开(公告)号：EP2286444A4

公开(公告)日：2012-11-21

申请号：EP09747138

申请日：2009-04-28

Applicant: IBM

Inventor： ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

IPC: H01L23/525 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：WO2004053922A3

公开(公告)日：2004-09-10

申请号：PCT/GB0305265

申请日：2003-12-02

Applicant: IBM ,  IBM UK

Inventor： WISE RICHARD ,  YAN HONGWEN ,  JI BRIAN ,  PANDA SIDDHARTHA ,  CHEN BOMY

IPC: H01J37/32

CPC classification number: H01J37/32623 ,  H01J37/3266

Abstract: A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles

Abstract translation: 一种等离子体蚀刻系统，其具有带磁体的晶圆吸盘，该磁体在晶圆上施加磁场以将晶圆从带电粒子屏蔽。 磁场与晶圆平行，在晶圆表面附近最强。 磁场可以是直的，也可以是圆形的。 在操作中，电子通过洛伦兹力从晶片偏转，晶片获得正电荷，并且离子通过静电排斥偏转。 允许中性物质通过磁场，并与晶圆碰撞。 中性物质通常提供比带电粒子更多的各向同性和材料选择性蚀刻，因此目前的磁场倾向于增加蚀刻各向同性和材料选择性。 而且，磁场可以保护晶片避免设计成从腔室表面清洗不需要的膜的调味过程，因为调味过程通常依赖于带电粒子的蚀刻

公开(公告)号：EP1743366A4

公开(公告)日：2009-11-11

申请号：EP05746299

申请日：2005-04-21

Applicant: IBM

Inventor： WISE RICHARD S ,  CHEN BOMY A ,  HAKEY MARK C ,  YAN HONGWEN

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53295 ,  H01L2221/1057 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2377148A4

公开(公告)日：2016-03-16

申请号：EP09836605

申请日：2009-11-19

Applicant: IBM ,  FREESCALE SEMICONDUCTOR INC

Inventor： RAMACHANDRAN RAVIKUMAR ,  YAN HONGWEN ,  MOUMEN NAIM ,  SCHAEFFER JAMES KENYON ,  KRISHNAN SIDDARTH A ,  WONG KEITH KWONG HON ,  KWON UNOH ,  BELYANSKY MICHAEL P ,  WISE RICHARD

IPC: H01L21/3205 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823857

公开(公告)号：EP2145349A4

公开(公告)日：2012-03-28

申请号：EP08754077

申请日：2008-04-08

Applicant: IBM

Inventor： CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  HENSON WILLIAM K ,  YAN HONGWEN ,  ZHANG YING

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04

CPC classification number: H01L29/045 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84

公开(公告)号：JP2010251799A

公开(公告)日：2010-11-04

申请号：JP2010167117

申请日：2010-07-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WISE RICHARD ,  YAN HONGWEN ,  JI BRIAN ,  PANDA SIDDHARTHA ,  CHEN BOMY

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/304

CPC classification number: H01J37/32623 ,  H01J37/3266

Abstract: PROBLEM TO BE SOLVED: To provide a plasma etching system having a wafer chuck including a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles.
SOLUTION: The magnetic field is parallel to the wafer, and the intensity thereof is highest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer is positively charged, and ions are deflected by electrostatic repulsion. Neutral chemical species are allowed to pass through the magnetic field, and collide with the wafer. Neutral chemical species generally provide higher isotropic and material-selective etching than charged particles, so that this magnetic field tends to increase etching isotropy and material selectivity. The magnetic field can protect the wafer from seasoning processes designed to remove unwanted films from the chamber surface because seasoning processes generally rely on etching by charged particles.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有晶片卡盘的等离子体蚀刻系统，该晶片卡盘包括在晶片上施加磁场以使晶片免受带电粒子的磁体。

解决方案：磁场平行于晶片，其强度在晶片表面附近最高。 磁场可以是直的或圆形的。 在操作中，电子通过洛仑兹力从晶片偏转，晶片带正电，离子被静电排斥偏转。 允许中性化学物质通过磁场，并与晶片碰撞。 中性化学物质通常提供比带电粒子更高的各向同性和材料选择性蚀刻，使得该磁场倾向于增加蚀刻各向同性和材料选择性。 磁场可以保护晶片免受设计用于从腔室表面去除不需要的膜的调味过程，因为调味过程通常依赖于带电粒子的蚀刻。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2001023957A

公开(公告)日：2001-01-26

申请号：JP2000131682

申请日：2000-04-28

Applicant: IBM

Inventor： BENNETT DELORES A ,  NORUM JAMES P ,  YAN HONGWEN ,  CHENFAN YUU

IPC: H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/318

Abstract: PROBLEM TO BE SOLVED: To obtain a method of etching an oxide layer on a nitride layer provided on a substrate at a high selective ratio. SOLUTION: This method includes a process, where the oxide layer on a substrate is plasma-etched with mixed gas which contains carbon and fluorine gas, and a nitrogen-containing gas. For nitride layer formed under the oxide layer, SixNy seeds are formed and deposited on the nitride layer, to substantially balance the etching of the nitride layer, so that the oxide layer can be etched at a high selective ratio on the nitride layer.

公开(公告)号：WO2005104212A3

公开(公告)日：2006-07-20

申请号：PCT/US2005013601

申请日：2005-04-21

Applicant: IBM ,  WISE RICHARD S ,  CHEN BOMY A ,  HAKEY MARK C ,  YAN HONGWEN

Inventor： WISE RICHARD S ,  CHEN BOMY A ,  HAKEY MARK C ,  YAN HONGWEN

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53295 ,  H01L2221/1057 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features (16) in a layer of dielectric material (13), and forming spacers (20) on sidewalls (16s) of the features. Conductors (25) are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps (40) at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers (42, 12) above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors (25) has a bottom in contact with a low-k dielectric layer (12), a top in contact with another low-k dielectric (42), and sides in contact only with the air gaps (40). The air gaps serve to reduce the intralevel capacitance.

Abstract translation: 形成用于集成电路的布线结构的方法包括以下步骤：在介电材料层（13）中形成多个特征（16），以及在特征的侧壁（16s）上形成间隔物（20）。 然后，导体（25）形成在特征中，通过间隔件与侧壁分离。 然后去除间隔物，在侧壁处形成气隙（40），使得导体通过气隙与侧壁分离。 在导体上方和下方的介电层（42,12）可以是介电常数小于导体之间的电介质的介电常数的低k电介质。 每个导体（25）的横截面具有与低k电介质层（12）接触的底部，与另一低k电介质（42）接触的顶部和仅与空气接触的侧面 间隙（40）。 气隙用于降低电容值。

公开(公告)号：WO2009140052A3

公开(公告)日：2010-01-21

申请号：PCT/US2009041861

申请日：2009-04-28

Applicant: IBM ,  ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

Inventor： ESHUN EBENEZER E ,  HE ZHONG-XIANG ,  RASSEL ROBERT M ,  COOLBAUGH DOUGLAS ,  GEBRESELASIE EPHREM G ,  WANG PING-CHUAN ,  KIM DEOK-KEE ,  KOTHANDARAMAN CHANDRASEKHARAN ,  ROBSON NORMAN W ,  MOY DAN ,  SAFRAN JOHN M ,  STEIN KENNETH J ,  HO HERBERT L ,  YAN HONGWEN

IPC: H01L21/335

CPC classification number: H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

Abstract translation: 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。

公开(公告)号：AT504079T

公开(公告)日：2011-04-15

申请号：AT05746299

申请日：2005-04-21

Applicant: IBM

Inventor： WISE RICHARD ,  CHEN BOMY ,  HAKEY MARK ,  YAN HONGWEN

IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.