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    THIN-BOX METAL BACKGATE EXTREMELY THIN SOI DEVICE
    11.
    发明申请
    THIN-BOX METAL BACKGATE EXTREMELY THIN SOI DEVICE 审中-公开
    薄金属背板极薄的SOI器件

    公开(公告)号：WO2011115773A3

    公开(公告)日：2011-12-29

    申请号：PCT/US2011027461

    申请日：2011-03-08

    Applicant: IBM ,  CHAN KEVIN K ,  REN ZHIBIN ,  WANG XINHUI

    Inventor： CHAN KEVIN K ,  REN ZHIBIN ,  WANG XINHUI

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7827 ,  H01L21/7624 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78696

    Abstract: Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm thick are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate 101 encapsulated by thin nitride layers 100, 102 to prevent metal oxidation, the tungsten backgate 103 being characterized by its low resistivity. The structure further includes at least one FET having a gate stack 131, 132, 133 formed by a high-K metal gate 132 and a tungsten region 133 superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer 100 as a channel. The SOI structure thus formed controls Vt variations from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and significantly lowers the drain induced bias and sub-threshold swings. The present structure supports the evidence of the stability of the wafer having a tungsten film during thermal processing, and especially during STI and contact formation.

    Abstract translation: 使用具有小于20nm厚的硅层的绝缘体上硅（SOI）结构来形成极薄的绝缘体上硅（ETSOI）半导体器件。 ETSOI器件使用由薄氮化物层100,102包封的薄钨背板101制造以防止金属氧化，钨背板103的特征在于其低电阻率。 该结构还包括至少一个FET，其具有由高K金属栅极132和叠加在其上的钨区域133形成的栅极堆叠131,132,133，栅极堆叠的占用面积利用薄SOI层100作为沟道。 如此形成的SOI结构控制了来自薄SOI厚度和其中掺杂剂的Vt变化。 ETSOI高K金属背栅完全耗尽器件与薄型BOX一起提供出色的短通道控制，并显着降低漏极引起的偏置和亚阈值波动。 本结构支持在热处理期间具有钨膜的晶片稳定性的证据，并且特别是在STI和接触形成期间。

    COMPRESSIVE SIGE <110> GROWTH MOSFET DEVICES
    12.
    发明申请
    COMPRESSIVE SIGE <110> GROWTH MOSFET DEVICES 审中-公开
    压缩信号<110>增长型MOSFET器件

    公开(公告)号：WO2006002410A3

    公开(公告)日：2007-12-06

    申请号：PCT/US2005022643

    申请日：2005-06-21

    Applicant: IBM ,  CHAN KEVIN K ,  GUARINI KATHRYN W ,  IEONG MEIKEL ,  RIM KERN ,  YANG MIN

    Inventor： CHAN KEVIN K ,  GUARINI KATHRYN W ,  IEONG MEIKEL ,  RIM KERN ,  YANG MIN

    IPC: H01L29/04 ,  H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/036 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: H01L29/045 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/823807 ,  H01L29/1054

    Abstract: A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psuedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600ºC and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described comprising the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HC1 acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a RMS roughness of less than 0.1 nm.

    Abstract translation: 描述了用于导电载体的结构和形成方法，其结合了在<110>中具有上表面的Si或SiGe的单晶衬底和SiGe的形貌或外延层，其Ge浓度与衬底的Ge不同，由此使形成层 正在紧张。 描述了一种用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中通过将工具中的温度增加到约600℃并形成含硅气体和锗的Ge形成或外延层的步骤 含气。 描述了一种用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底浸入含有臭氧，稀HF，去离子水，HCl酸和去离子水的一系列浴中，然后在惰性气氛中干燥衬底 以获得不含杂质且RMS小于0.1nm的衬底表面。

    SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK
    13.
    发明申请
    SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK 审中-公开
    分散多晶硅/多晶硅合金栅极堆叠

    公开(公告)号：WO2005041252A2

    公开(公告)日：2005-05-06

    申请号：PCT/US2004020907

    申请日：2004-06-30

    Applicant: IBM ,  CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

    Inventor： CHEN JIA ,  CHAN KEVIN K ,  HUANG SHIH-FEN ,  NOWAK EDWARD J

    IPC: H01L20060101 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/24 ,  H01L29/49 ,  H01L29/76 ,  H01L31/072 ,  H01L31/119 ,  H01L

    CPC classification number: H01L21/2807 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/665

    Abstract: A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer (41) on the gate dielectric (43). The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe (45) with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer (47), (3) to 4A thick. The thin SiO2 or SixGeyOZ interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of a subsequently deposited layer of cobalt. This gate electrode stack structure is used for both nFETs.and pFETs.

    Abstract translation: 在栅极电介质（43）上的硅纳米晶种子层（41）上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积具有高达至少70％的[Ge]的均匀且连续的多晶硅（45）层。 在快速降低的温度下，氧气环境中沉积室的原位吹扫导致薄的SiO 2或SixGeyOz界面层（47），（3）至4A厚。 薄的SiO 2或SixGeyOZ界面层是足够薄且不连续的，以提供对栅极电流的很小的阻力，但是具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许随后沉积的钴的硅化物。 该栅电极堆叠结构用于nFET和pFET。

    Asymmetric epitaxy and application thereof
    14.
    发明专利
    Asymmetric epitaxy and application thereof 未知

    公开(公告)号：GB2487870A

    公开(公告)日：2012-08-08

    申请号：GB201207819

    申请日：2010-10-05

    Applicant: IBM

    Inventor： YIN HAIZHOU ,  WANG XINHUI ,  CHAN KEVIN K ,  REN ZHIBIN

    IPC: H01L21/265 ,  H01L29/66 ,  H01L29/78

    Abstract: The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.

    15.
    发明专利
    未知

    公开(公告)号：AT516600T

    公开(公告)日：2011-07-15

    申请号：AT06120727

    申请日：2003-02-19

    Applicant: IBM

    Inventor： APPENZELLER JOERG ,  AVOURIS PHAEDON ,  CHAN KEVIN K ,  COLLINS PHILIP G ,  MARTEL RICHARD ,  WONG HON-SUM

    IPC: H01L51/10 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30

    Abstract: A carbon-nanotube field transistor semiconductor device, comprising: a vertical carbon-nanotube (508) wrapped in a dielectric material (511); a source formed at a first side of the carbon-nanotube; a drain (515) formed on a second side of the carbon-nanotube; a bilayer nitride complex through which a band strap of each of the source and the drain is formed connecting the carbon-nanotube wrapped in the dielectric material to the source and the drain; and a gate (512) formed substantially over a portion of the carbon-nanotube. Further disclosed are methods for forming the following self-aligned carbon-nanotube field effect transistor: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

    Verfahren mit asymmetrischer Epitaxie zur Herstellung von Feldeffekttransistoren
    18.
    发明专利
    Verfahren mit asymmetrischer Epitaxie zur Herstellung von Feldeffekttransistoren 未知

    公开(公告)号：DE112010004330B4

    公开(公告)日：2014-03-06

    申请号：DE112010004330

    申请日：2010-10-05

    Applicant: IBM

    Inventor： YIN HAIZHOU ,  WANG XINHUI ,  CHAN KEVIN K ,  REN ZHIBIN

    IPC: H01L21/336 ,  H01L29/78

    Abstract: Die vorliegende Erfindung stellt ein Verfahren zum Bilden asymmetrischer Feldeffekttransistoren bereit. Das Verfahren umfasst das Bilden einer Gate-Struktur auf einem Halbleitersubstrat, wobei die Gate-Struktur einen Gate-Stapel und Abstandhalter in Nachbarschaft zu Seitenwänden des Gate-Stapels umfasst und eine erste Seite und eine zweite Seite gegenüber der ersten Seite aufweist; das Durchführen einer schrägen Ionenimplantation von der ersten Seite der Gate-Struktur in dem Substrat, wodurch eine Zone mit Ionenimplantation in Nachbarschaft zu der ersten Seite gebildet wird, wobei die Gate-Struktur verhindert, dass die schräge Ionenimplantation das Substrat in Nachbarschaft zu der zweiten Seite der Gate-Struktur erreicht; und das Durchführen eines epitaxialen Anwachsens auf dem Substrat auf der ersten und zweiten Seite der Gate-Struktur. Als Ergebnis ist das epitaxiale Anwachsen auf dem Bereich mit Ionenimplantation viel langsamer als auf einem Bereich, welcher keine Ionenimplantation erfährt. Eine Source-Zone, welche durch das epitaxiale Anwachsen auf der zweiten Seite der Gate-Struktur gebildet wird, weist eine Höhe auf, die größer ist als die einer Drain-Zone, welche durch das epitaxiale Anwachsen auf der ersten Seite der Gate-Struktur gebildet wird. Eine dadurch gebildete Halbleiterstruktur wird ebenfalls bereitgestellt.

    Delta monolayer dopants epitaxy for embedded source/drain silicide
    19.
    发明专利
    Delta monolayer dopants epitaxy for embedded source/drain silicide 未知

    公开(公告)号：GB2494608B

    公开(公告)日：2013-09-04

    申请号：GB201300789

    申请日：2011-06-10

    Applicant: IBM

    Inventor： CHAN KEVIN K ,  DUBE ABHISHEK ,  HOLT JUDSON R ,  JOHNSON JEFFREY B ,  LI JINGHONG ,  PARK DAE-GYU ,  ZHU ZHENGMAO

    IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

    Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.

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