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    Optimizations for an unbounded transactional memory (UTM) system
    22.
    发明专利
    Optimizations for an unbounded transactional memory (UTM) system 未知

    公开(公告)号：GB2519877A

    公开(公告)日：2015-05-06

    申请号：GB201500492

    申请日：2009-06-26

    Applicant: INTEL CORP

    Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

    IPC: G06F9/30 ,  G06F9/318 ,  G06F12/10

    Abstract: Disclosed is a apparatus with logic that decodes metadata access instructions, the instructions referencing the data address of a data item, and metadata logic that translates the data address to a distinct metadata address. Metadata logic also accesses the metadata referenced by the distinct metadata address in response to the decoding logic decoding the metadata instruction. Also disclosed is a program that responsive to a data access operation, which references a data address, generates a metadata access operation to reference the data address of the data address operation. The metadata access operation translating the data address to a disjoint metadata address, and accessing the metadata for the data item at the data address based on the metadata address. The metadata access instruction may be a metadata bit test and set instruction, metadata store and set instruction, a metadata store and reset instruction, a compressed metadata test instruction, a compressed metadata store instruction or a compresses metadata clear instruction.

    Creating an isolated execution environment in a co-designed processor
    24.
    发明专利
    Creating an isolated execution environment in a co-designed processor 未知

    公开(公告)号：GB2514221A

    公开(公告)日：2014-11-19

    申请号：GB201404228

    申请日：2014-03-11

    Applicant: INTEL CORP

    Inventor： YAMADA KOICHI ,  SHANMUGAVELAYUTHAM PALANIVEL RAJAN ,  RODGERS SCOTT D ,  HUNTLEY BARRY E ,  BEANEY JAMES D JR ,  TAMIR BOAZ

    IPC: G06F9/455

    Abstract: A co-designed processor 605, such as a heterogeneous multi-core processor, includes, isolated from a software stack and transparent thereto by way of means such as concealed memory 640, a binary translation (BT) engine 645 having code to generate a binary translation of a first code segment and to store the binary translation in a translation cache 648. The binary translated code may include a routine to emulate an instruction not provided in the target ISA such as an instruction with a vector operand wherein a width of a datapath of the target core is less than a width of the vector operand. The heterogeneous multi-core processor may include a first and second core for executing instructions of a first ISA and a second ISA respectively wherein the second ISA may be different to the first ISA or a subset thereof. The second core may have lower power consumption than the first core and the binary translation may be from the first ISA to the second ISA.

    Optimizations for an unbounded transactional memory (utm) system
    26.
    发明专利
    Optimizations for an unbounded transactional memory (utm) system 未知

    公开(公告)号：GB2484416A

    公开(公告)日：2012-04-11

    申请号：GB201119084

    申请日：2009-06-26

    Applicant: INTEL CORP

    Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109

    Abstract: A method and apparatus for optimizing an Unbounded Transactional Memory (UTM) system is herein described. Hardware support for monitors, buffering, and metadata is provided, where orthogonal metaphysical address spaces for metadata may be separate associated with threads and/or software subsystems within threads. In addition, the metadata may be held with hardware in a compressed manner with regard to data transparently to software. Furthermore, in response to metadata access instruction/operations the hardware is capable of supporting a forced metadata value to enable multiple modes of transactional execution. However, if monitors, buffered data, metadata, or other information is lost or conflicts are detected hardware provides for variations of a loss instruction that is able to poll a transaction status register for such loss or conflict and jump execution to a label in response to detecting the loss or conflict. Similarly, multiple variations of a commit instruction are provided for to allow software to define commit conditions and information to clear upon commit. Furthermore, hardware provides support to enable suspension and resume of transactions upon ring level transitions.

    Method and system for extending a plurality of command streams/a plurality of data streams on microprocessor
    27.
    发明专利
    Method and system for extending a plurality of command streams/a plurality of data streams on microprocessor 有权
    方法和系统，用于扩展多项指令流/微处理器数据流的多样性

    公开(公告)号：JP2009104259A

    公开(公告)日：2009-05-14

    申请号：JP2007273186

    申请日：2007-10-19

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： JAIMISON COLLINS ,  PERRY WANG ,  BERNARD LINT ,  YAMADA KOICHI ,  ASIT MALLICK ,  RICHARD HANKINS ,  GAUTHAM CHINYA

    IPC: G06F9/48 ,  G06F15/78

    Abstract: PROBLEM TO BE SOLVED: To provide a system for enabling emulation of a multiple instruction stream/multiple data stream (MIMD) extension that supports user-level sequencer management and control, and a set of privileged code executed by both operating system managed sequencers and application managed sequencers, including different sets of persistent per-CPU and per-thread data. SOLUTION: A lightweight code layer executes beneath the operating system. This code layer is invoked in response to particular monitored events, such as the need for communication between an operating system managed sequencer and an application managed sequencer. Control is transferred to this code layer, for execution of special operations, after which control returns back to originally executing code. The code layer is normally dormant and can be invoked at any time when either a user application or the operating system is executing. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种能够模拟支持用户级定序器管理和控制的多指令流/多数据流（MIMD）扩展的系统，以及由操作系统管理的两组执行的一组特权代码 顺控程序和应用程序管理的顺控程序，包括不同的持久性每CPU和每个线程数据。 解决方案：在操作系统下执行轻量级代码层。 响应于特定的监视事件，例如对操作系统管理的定序器和应用程序管理的定序器之间的通信的需要，该代码层被调用。 控制被传送到该代码层，用于执行特殊操作，之后控制返回到原始执行的代码。 代码层通常处于休眠状态，可以在用户应用程序或操作系统正在执行时随时调用。 版权所有（C）2009，JPO＆INPIT

    無制限トランザクショナルメモリ（ＵＴＭ）システムの最適化
    28.
    发明专利
    無制限トランザクショナルメモリ（ＵＴＭ）システムの最適化 有权
    优化无限交易记录（UTM）系统

    公开(公告)号：JP2015008008A

    公开(公告)日：2015-01-15

    申请号：JP2014177475

    申请日：2014-09-01

    Applicant: インテル・コーポレーション ,  Intel Corp

    Inventor： GAD SHAEFFER ,  JAN GRAY ,  BURTON SMITH ,  ADL-TABATABAI ALI-REZA ,  ROBERT GEVA ,  VADIM BASSIN ,  DAVID CALLAHAN ,  NI YANG ,  SAHA BRATIN ,  MARTIN TAILLEFER ,  SHLOMO RAIKIN ,  YAMADA KOICHI ,  WANG LANDY ,  ARUN KISHAN

    IPC: G06F12/08

    Abstract: 【課題】無制限トランザクショナルメモリ(UTM)システムを最適化する方法および装置を提供する。【解決手段】キャッシュエントリを保持するデータキャッシュアレイと、データキャッシュアレイに結合されているキャッシュ制御ロジックとを備え、キャッシュ制御ロジックは、キャッシュエントリに対するバッファ済み更新に応じて、キャッシュエントリを、監視されていない状態からバッファ済みコヒーレンシ状態および読出監視状態へと遷移させて、その後に、バッファ済み更新をコミットするためにキャッシュエントリを修正済み状態に遷移させる前に、キャッシュエントリを、バッファ済みコヒーレンシ状態および書込監視状態に遷移させる。【選択図】図1

    Abstract translation: 要解决的问题：提供一种用于优化无限交易内存（UTM）系统的方法和设备。解决方案：该设备包括用于保存高速缓存条目的数据高速缓存阵列和耦合到数据高速缓存阵列的高速缓存控制逻辑，高速缓存 控制逻辑根据高速缓存条目的缓冲更新将缓存条目从非监视状态转移到缓冲的一致性状态和读取监视状态，之后，将高速缓存条目转换为缓冲的一致性状态和写入监视状态 之后将高速缓存条目转换到用于提交缓冲更新的校正状态。

    Transition from source instruction set architecture (isa) code to translated code in partial emulation environment
    29.
    发明专利
    Transition from source instruction set architecture (isa) code to translated code in partial emulation environment 有权
    源代码指令集架构（ISA）转换部分模拟环境中的翻译代码

    公开(公告)号：JP2011134315A

    公开(公告)日：2011-07-07

    申请号：JP2010262793

    申请日：2010-11-25

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： WINKEL SEBASTIAN ,  YAMADA KOICHI ,  SRINIVAS SURESH ,  SMITH JAMES E

    IPC: G06F9/455

    CPC classification number: G06F9/3017 ,  G06F9/455 ,  G06F12/0873 ,  G06F12/0875

    Abstract: PROBLEM TO BE SOLVED: To provide an instruction set architecture that achieves a software emulation environment with high performance.
    SOLUTION: A processor operates in multiple modes, including a direct execution mode and an emulation execution mode. The processor operates in a partial emulation model in which source instruction set architecture (ISA) instructions are directly processed in the direct execution mode and translated code generated by an emulation engine is processed in the emulation execution mode. Furthermore, use of information that can be stored in one or more storages of the processor and elsewhere in a system enables efficient transitions between the modes.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供实现具有高性能的软件仿真环境的指令集架构。 解决方案：处理器以多种模式运行，包括直接执行模式和仿真执行模式。 处理器在部分仿真模型中操作，其中源指令集架构（ISA）指令以直接执行模式直接处理，并且仿真引擎生成的转换代码在仿真执行模式下被处理。 此外，使用可以存储在处理器的一个或多个存储器中以及系统中的其他地方的信息使得能够在这些模式之间有效地转换。 版权所有（C）2011，JPO＆INPIT

    METHOD AND DEVICE FOR PRELOADING VARIOUS DEFAULT ADDRESS CONVERSION ATTRIBUTES
    30.
    发明专利
    METHOD AND DEVICE FOR PRELOADING VARIOUS DEFAULT ADDRESS CONVERSION ATTRIBUTES 失效

    公开(公告)号：JPH10228419A

    公开(公告)日：1998-08-25

    申请号：JP35482697

    申请日：1997-12-24

    Applicant: INTEL CORP

    Inventor： YAMADA KOICHI ,  HAMMOND GARY N

    IPC: G06F12/10

    Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for simplifying the introduction of conversion from a virtual address into a physical address to a conversion unit. SOLUTION: A device to be used for a computer system is generally provided in a state including a conversion unit, a default attribute storage area and a preloading unit. The conversion unit stores conversion for converting a virtual address into a physical address and each conversion includes an attribute field. A default conversion attribute storing area stores several default conversion attributes. The preloading unit is connected to the default conversion unit and the conversion unit. When a signal indicating that the conversion of a virtual address is not stored in the conversion unit is received from the conversion unit, the preloading unit transmits a suitable default conversion attribute to the conversion unit in response to the received signal.

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