公开(公告)号：DE102005052563A1

公开(公告)日：2007-05-03

申请号：DE102005052563

申请日：2005-11-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OTREMBA RALF ,  KRAFT DANIEL ,  KOMPOSCH ALEXANDER ,  EDER HANNES ,  GANITZER PAUL ,  WOEHLERT STEFAN

IPC: H01L23/48 ,  H01L21/60

Abstract: A semiconductor chip (1) comprises an adhesion layer -free three layer metallization comprising an aluminum layer (4) directly on the chip, followed by a diffusion-blocking layer (5) and directly, by a solder layer (6). The diffusion-blocking layer comprises titanium, nickel, platinum or chromium and the solder layer comprises diffusion solder. All three layers are applied by sputtering. Independent claims are also included for production processes for the above chip.

公开(公告)号：DE102005031836A1

公开(公告)日：2007-01-18

申请号：DE102005031836

申请日：2005-07-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OTREMBA RALF

IPC: H01L25/07 ,  H01L23/488 ,  H01L29/78 ,  H01L29/861

Abstract: A semiconductor power module has at least one power semiconductor chip (2) which can be controlled by the field effect and has a plurality of fail-safe, small-area SiC power diodes (D1 to D8). The function of a large-area SiC power diode chip which is susceptible to failure is distributed over these small-area, parallel-connected SiC power diode chips (D1 to D8) in such a way that their total area of active SiC diode areas (F1 to F8) corresponds to an area extent of a large-area non-fail-safe SiC power diode chip.

公开(公告)号：DE102005001151A1

公开(公告)日：2006-07-20

申请号：DE102005001151

申请日：2005-01-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OTREMBA RALF ,  HOSSEINI KHALIL ,  STRACK HELMUT

IPC: H01L23/28 ,  H01L23/48 ,  H01L29/78

Abstract: Component arrangement has semiconductor chip (10), load connections, and control port whereby first and second load connection are arranged on opposite sides of semiconductor chip. Chip carrier (21), on which semiconductor chip is arranged, is connected electrically and thermally leading with first load connection of semiconductor body. Contact part (22) is arranged which is connected to second load connection and is electrically and thermally leading. Dielectric mass is surrounded by semiconductor chip, carrier chip and contact part and form a housing. Chip carrier lies exposed at first side (31) of housing and contact part lies exposed on second side (32) of housing opposite to first side. Control port is connected electrically leading with a connection leg (23), which is led out from the housing. An independent claim is also included for the component cascade with two pile-like component arrangement arranged one on another.

公开(公告)号：DE10323007B4

公开(公告)日：2005-10-20

申请号：DE10323007

申请日：2003-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOTT NIKOLAUS ,  HAEBERLEN OLIVER ,  KOTEK MANFRED ,  LARIK JOOST ,  MAERZ JOSEF ,  OTREMBA RALF

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/58 ,  H01L21/56 ,  H01L23/28

Abstract: The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

公开(公告)号：DE10335111A1

公开(公告)日：2005-03-10

申请号：DE10335111

申请日：2003-07-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LENZ MICHAEL ,  OTREMBA RALF ,  ROEDIG HERBERT

IPC: H01H47/18 ,  H01L21/58 ,  H01L21/60

Abstract: A mounting process for a semiconductor component comprises applying solder to the component (3) or mount (11,12), bringing the two parts together and heating at least one part of the component above the solder melting point by applying electrical power to the component to bond the parts and then cooling.

公开(公告)号：DE10333800B3

公开(公告)日：2004-10-28

申请号：DE10333800

申请日：2003-07-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OTREMBA RALF

IPC: H01L23/433 ,  H01L23/495 ,  H01L25/065 ,  H01L25/18 ,  H01L25/07 ,  H01L21/50

Abstract: The semiconductor component (1) has a lower semiconductor element (5) and an upper semiconductor element (6,7), with a contact region between them, providing a contact between the upper side of the lower semiconductor component and the lower side of the upper semiconductor element. The contact region is provided by the end sections of the bonding wires (12a,13a) acting as the electrical terminals for the contact regions. An independent claim for a manufacturing method for a semiconductor component is also included.

公开(公告)号：DE10303933A1

公开(公告)日：2004-08-19

申请号：DE10303933

申请日：2003-01-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OTREMBA RALF

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/488

Abstract: The device has a chip with contact areas on front and rear sides, a plate on which the rear side of the chip is mounted and with which a first contact area is in electrical contact, a housing exposing a side of the plate facing away from the chip and connecting legs protruding out of it. At least one leg is part of the plate. At least one contact area is connected to connecting legs unconnected to the plate but connected together in the housing. The device has a semiconducting chip (10) with first and second (13,14) contact areas on the front and rear sides, a mounting plate (30) on which the rear side of the chip is mounted and with which the first contact area is in electrical contact and a housing (20), whereby a side of the plate facing away from the chip is exposed and connecting legs (31,41,42, 52) protruding out of the housing, whereby at least one legs is part of the plate. At least one contact area is electrically connected to at least two connecting legs that are not connected to the mounting plate and are connected together in the housing.

公开(公告)号：DE102014107909B4

公开(公告)日：2024-12-12

申请号：DE102014107909

申请日：2014-06-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MAHLER JOACHIM ,  OTREMBA RALF

IPC: H05K1/03 ,  H05K7/20

Abstract: Leiterplatte, umfassend:eine elektrisch leitende Schicht (12); undeine dielektrische Schicht (14), die ein Polymer (16) umfasst, wobei das Polymer metallische Partikel (18) umfasst, wobei die metallischen Partikel (18) selektiv an einer Hauptoberfläche der Leiterplatte angeordnet sind.

公开(公告)号：DE102013112143B4

公开(公告)日：2022-12-22

申请号：DE102013112143

申请日：2013-11-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MOHAMED ABDUL RAHMAN ,  SENIVASAN SUBARAMANIYM ,  ABDULLAH ZAKARIA ,  OTREMBA RALF

IPC: H01L21/50 ,  H01L21/56 ,  H01L21/677 ,  H01L21/683 ,  H05K13/02

Abstract: Aufnehmerkopf, umfassend:ein Schaftstück (210) mit einem Halter (220),einen Zwischenkörper (230), der durch ein erstes Gelenk (280) mit dem Halter (220) verbunden ist, wobei das erste Gelenk (280) den Zwischenkörper (230) und den Arme (222, 223) aufweisenden Halter (220) umfasst, und wobei der Zwischenkörper (230) dazu ausgelegt ist, um eine erste Achse (228) orthogonal zu den Armen (222, 223) drehbar zu sein, undeinen Klemmkopf (270), der durch ein zweites Gelenk (290) mit dem Zwischenkörper (230) verbunden ist.

公开(公告)号：DE102014111420B4

公开(公告)日：2022-03-17

申请号：DE102014111420

申请日：2014-08-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WACHTER ULRICH ,  HUBER VERONIKA ,  KILGER THOMAS ,  OTREMBA RALF ,  STADLER BERND ,  MAIER DOMINIC ,  SCHIESS KLAUS ,  SCHLOEGL ANDREAS ,  WAHL UWE

IPC: H01L21/50 ,  H01L21/283 ,  H01L21/768 ,  H01L23/28 ,  H01L23/36 ,  H01L23/485 ,  H01L33/48

Abstract: Verfahren zur Herstellung eines Halbleitergehäuses, wobei das Verfahren umfasst:Bereitstellen eines Halbleiter-Nacktchips mit einem Anschluss an einer ersten Seite des Nacktchips;Plattieren einer Kupferschicht an einer der ersten Seite gegenüberliegenden zweiten Seite des Nacktchips, wobei das Plattieren auf Wafer-Ebene erfolgt;Einbetten des Nacktchips in eine Formmasse, so dass der Nacktchip an allen Seiten, mit Ausnahme der ersten Seite, von der Formmasse bedeckt ist;Dünnen der Formmasse an einer zu der zweiten Seite des Nacktchips benachbarten Seite der Formmasse, um die Kupferschicht an der zweiten Seite des Nacktchips freizulegen, ohne dabei die zweite Seite des Nacktchips freizulegen; undAusbilden einer elektrischen Verbindung mit dem Anschluss an der ersten Seite des Nacktchips.