公开(公告)号：GB2577417A

公开(公告)日：2020-03-25

申请号：GB201917399

申请日：2018-05-10

Applicant: IBM

Inventor： MARC BERGENDAHL ,  ERIC MILLER ,  FEE LI LIE ,  SEAN TEEHAN ,  KANGGUO CHENG ,  JOHN RYAN SPORRE ,  GAURI KARVE

IPC: H01L27/04

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：GB2550740A

公开(公告)日：2017-11-29

申请号：GB201712260

申请日：2016-01-04

Applicant: IBM

Inventor： BRUCE DORIS ,  KERN RIM ,  ALEXANDER REZNICEK ,  DARSEN DUANE LU ,  ALI KHAKIFIROOZ ,  KANGGUO CHENG

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer(20) disposed on a substrate(10), a silicon germanium layer(30) disposed on the dielectric layer(20), and a strained semiconductor material layer(40) disposed directly on the silicon germanium layer(30), forming a plurality of fins(43, 45) on the SSOI structure, forming a gate structure(50) over a portion of at least one fin in a nFET region, forming a gate structure(60) over a portion of at least one fin in a pFET region, removing the gate structure(60) over the portion of the at least one fin in the pFET region, removing the silicon germanium layer(30) exposed by the removing, and forming a new gate structure(90) over the portion of the at least one fin in the pFET region, such that the new gate structure(90) surrounds the portion on all four sides.

公开(公告)号：DE112011100948T5

公开(公告)日：2013-01-24

申请号：DE112011100948

申请日：2011-03-31

Applicant: IBM

Inventor： BOOTH ROGER A ,  KANGGUO CHENG ,  PEI CHENGWEN ,  FURUKAWA TOSHIHARU

IPC: H01L27/06 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L29/94

Abstract: Eine integrierte Schaltung mit FinFETs (60a, b) und einem Metall-Isolator-Metall(MIM)-Fin-Kondensator (65) und Fertigungsverfahren werden offenbart. Das Verfahren beinhaltet das Bilden eines ersten FinFET (60a), der ein erstes Dielektrikum (25) und einen ersten Leiter (30) umfasst; das Bilden eines zweiten FinFET (60b), der ein zweites Dielektrikum (40) und einen zweiten Leiter (45) umfasst; und das Bilden eines Fin-Kondensators (65), der den ersten Leiter (25), das zweite Dielektrikum (40) und den zweiten Leiter (45) umfasst.

公开(公告)号：GB2631071B

公开(公告)日：2025-04-16

申请号：GB202414743

申请日：2023-03-23

Applicant: IBM

Inventor： JULIEN FROUGIER ,  RUILONG XIE ,  KANGGUO CHENG ,  CHANRO PARK ,  OLEG GLUSCHENKOV

IPC: H10D62/13 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D84/01 ,  H10D84/03 ,  H10D84/83

Abstract: A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region. The at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth. The semiconductor structure further includes a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space and a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.

公开(公告)号：GB2607481A

公开(公告)日：2022-12-07

申请号：GB202211293

申请日：2020-12-23

Applicant: IBM

Inventor： RUILONG XIE ,  KANGGUO CHENG ,  JULIEN FROUGIER

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/088

Abstract: A semiconductor structure and a method for forming a semiconductor structure having a self-aligned dielectric pillar for reducing trench silicide-to-gate parasitic capacitance are provided. A nanosheet stack (206) is formed over a substrate (204). A dielectric pillar (402) is positioned adjacent to the nanosheet stack (206) and on a shallow trench isolation region (212) of the substrate (204). The nanosheet stack (206) is recessed to expose a surface of the shallow trench isolation region (212) and a source or drain (S/D) region (602) is formed on the exposed surface of the shallow trench isolation region (212). A contact trench (802) is formed that exposes a surface of the S/D region (602) and a surface of the dielectric pillar (402).

公开(公告)号：DE112020005385T5

公开(公告)日：2022-08-11

申请号：DE112020005385

申请日：2020-10-12

Applicant: IBM

Inventor： PARK CHANRO ,  KANGGUO CHENG ,  XIE RUILONG ,  LEE CHOONGHYUN

IPC: H01L27/24 ,  H01L21/28 ,  H01L21/31

Abstract: Eine Halbleiterstruktur, die eine vertikale resistive Speicherzelle enthält, und ein Herstellungsverfahren dafür. Das Verfahren enthält Bilden einer Opferschicht über einem Transistor-Drain-Kontakt; Bilden einer ersten dielektrischen Schicht über der Opferschicht; Bilden eines Zellenkontaktlochs durch die erste dielektrische Schicht; Bilden eines Zugangskontaktlochs durch die erste dielektrische Schicht und Freilegen der Opferschicht; Entfernen der Opferschicht, um einen Hohlraum zu bilden, der eine untere Öffnung des Zellenkontaktlochs und eine untere Öffnung des Zugangskontaktlochs verbindet; durch Atomlagenabscheidung in dem Zellenkontaktloch Bilden einer zweiten dielektrischen Schicht, die einen Saum enthält; Bilden einer unteren Elektrode innerhalb des Hohlraums und in Kontakt mit dem Drain-Kontakt, der zweiten dielektrischen Schicht und dem Saum; und Bilden einer oberen Elektrode über der ersten dielektrischen Schicht und in Kontakt mit der zweiten dielektrischen Schicht und dem Saum.

公开(公告)号：GB2581893B

公开(公告)日：2022-04-13

申请号：GB202006464

申请日：2018-11-01

Applicant: IBM

Inventor： CHEN ZHANG ,  KANGGUO CHENG ,  TENKO YAMASHITA ,  XIN MIAO ,  WENYU XU

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/308 ,  H01L29/06

Abstract: Techniques for increasing Weff VFET devices are provided. In one aspect, a method of forming a fin structure includes: depositing a hardmask onto a substrate; depositing a mandrel material onto the hardmask; patterning the mandrel material along a first direction to form first mandrels; forming first spacers alongside the first mandrels; forming second mandrels in between the first mandrels; pattering the first/second mandrels along a second direction perpendicular to the first direction; forming second spacers, perpendicular to the first spacers, alongside the first/second mandrels; selectively removing the first/second mandrels leaving behind a ladder-shaped pattern formed by the first/second spacers; transferring the ladder-shaped pattern to the hardmask and then to the substrate. A method of forming a VFET device, a VFET fin structure, and a VFET device are also provided.

公开(公告)号：GB2595160A

公开(公告)日：2021-11-17

申请号：GB202111646

申请日：2020-02-24

Applicant: IBM

Inventor： RUILONG XIE ,  JULIEN FROUGIER ,  CHANRO PARK ,  EDWARD NOWAK ,  YI QI ,  KANGGUO CHENG ,  NICOLAS LOUBET

IPC: H01L21/02 ,  H01L29/786

Abstract: A technique for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. A non-planar channel region is formed having a first semiconductor layer (208), a second semiconductor layer (206), and a fin-shaped bridge layer between the first semiconductor layer (208) and the second semiconductor layer (206). Forming the non-planar channel region can include forming a nanosheet stack over a substrate (204), forming a trench (502) by removing a portion of the nanosheet stack, and forming a third semiconductor layer (602) in the trench (502). Outer surfaces of the first semiconductor layer (208), the second semiconductor layer (206), and the fin-shaped bridge region define an effective channel width of the non-planar channel region.

公开(公告)号：GB2579533B

公开(公告)日：2020-11-04

申请号：GB202005675

申请日：2018-10-16

Applicant: IBM

Inventor： KANGGUO CHENG ,  JUNTAO LI ,  CHOONGHYUN LEE ,  PENG XU

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092

Abstract: Integrated chips include vertically stacked channel layers, with a first stack in a first device region and a second stack in a second device region. A first dielectric layer is formed conformally on the vertically stacked channel layers in the first device region. A second dielectric layer is formed conformally on the vertically stacked channel layers in the second device region. Gate conductors are formed around the vertically stacked channel layers in both the first device region and the second device region, filling a space between surfaces of the respective first dielectric layer and second dielectric layer.

公开(公告)号：GB2560480A

公开(公告)日：2018-09-12

申请号：GB201810430

申请日：2016-11-22

Applicant: IBM

Inventor： FEI LIU ,  QING CAO ,  KANGGUO CHENG ,  ZHENGWEN LI

IPC: G06N3/063 ,  G06N3/04

Abstract: A three-dimensional integration of synapse circuitry is formed. One or more neuron layers each comprises a plurality of computing elements, and one or more synapse layers each comprising an array of memory elements are formed on top of the one or more neuron layers. A plurality of staggered through-silicon vias (TSVs) connect the one or more neuron layers to the one or more synapse layers and operate as communication links between one or more computing elements in the one or more neuron layers and one or more memory elements in the one or more synapse layers.