US09859554B2
A negative electrode material includes an active material. The active material includes a silicon core selected from the group consisting of Si, SiO2, SiOx (0
US09859552B2
An electrode material for nonaqueous electrolyte secondary battery of an embodiment includes a silicon nanoparticle, and a coating layer coating the silicon nanoparticle. The coating layer includes an amorphous silicon oxide and a silicon carbide phase. At least a part of the silicon carbide phase exists on a surface of the silicon nanoparticle.
US09859546B2
A method for producing an electrochemical bundle of a lithium battery, such as an Li-ion battery, with a view to electrically connecting same to the output terminals of the battery, wherein it includes the combination of two steps of folding an electrochemical bundle of a lithium battery which are carried out separately, i.e. a radial folding with plastic deformation and an axial compacting, which make it possible to obtain two separate areas on at least one, and preferably both, of the lateral ends of the bundle. The invention also concerns a method for producing an electrical connection part between the electrochemical bundle and one of the output terminals of the battery, and an associated current collector.
US09859544B2
A battery module includes a plurality of battery cells aligned in one direction, each battery cell of the plurality of battery cells including a terminal portion on a first surface of a respective battery cell, a bus-bar electrically connect between the terminal portions of the plurality of battery cells, and a bus-bar holder positioned on the first surfaces of the plurality of battery cells, the bus-bar holder including support portions configured to support two different surfaces of the bus-bar, respectively.
US09859534B2
A thermal expansion coefficient of a battery case may be lower than those of an insulating film and a separator. Portions of the insulating film, which are held in contact with the electrode body and the battery case, may be adhered to the separator, which is positioned on the outermost surface of the electrode body, and the battery case, respectively. A first 90 degree peeling strength of an adhesion portion between the insulating film and the battery case is higher than a second 90 degree peeling strength of an adhesion portion between the insulating film and the separator. The first 90 degree peeling strength may be 15 mN/cm or higher, and the second 90 degree peeling strength may be 5 mN/cm or higher.
US09859525B2
Disclosed is a flexible display substrate and a method for manufacturing the same which can avoid break and peeling of film layers disposed on a flexible base and further reduce degree of a warpage occurred in the flexible base when separating the support substrate from the flexible base located above the support substrate. The flexible display substrate comprises the flexible base, a first buffer layer and a second buffer layer disposed on an upper surface and a lower surface of the flexible base, respectively, a plurality of display modules disposed on the first buffer layer, each display module includes at least one thin film transistor and at least one electrode corresponding to the thin film transistor, and a plurality of auxiliary thin film transistors disposed on one side of the second buffer layer which is away from the flexible base, the auxiliary thin film transistors corresponding to the thin film transistors one by one, respectively.
US09859524B2
Various embodiments may relate to an optoelectronic component, including an optically active region formed for taking up and/or for providing electromagnetic radiation, at least one first contact structure, wherein the optically active region is electrically conductively coupled to the first contact structure, and an encapsulation structure with a second contact structure, wherein the encapsulation structure is formed on or above the optically active region and the first contact structure, and an electrically conductive structure formed for electrically conductively connecting the first contact structure to the second contact structure, wherein the encapsulation structure is at least partly formed by an electrically insulating molding compound, wherein the electrically insulating molding compound at least partly surrounds the electrically conductive structure.
US09859519B2
An organic light emitting display device comprises first and second electrodes facing each other on a substrate; and three emission portions arranged between the first electrode and the second electrode, wherein at least one among the three emission portions includes two emitting layers, and the first, second and third emission portions being collectively configured as a TOL-FESE (Thickness of Organic Layers between the First Electrode and the Second Electrode) structure in which thicknesses of organic layers between the first electrode and the second electrode are different from one another, each organic layer having a specified thickness that provides the organic light emitting display device having the TOL-FESE structure with improved red efficiency or blue efficiency and minimized color shift rate with respect to a viewing angle, when compared to an organic light emitting display device that lacks the TOL-FESE structure.
US09859514B1
The present disclosure relates to a method for making nanoscale heterostructure. The method includes: forming a first carbon nanotube layer on a support, the first carbon nanotube layer includes a number of first carbon nanotubes; forming a semiconductor layer on a surface of the first carbon nanotube layer; covering a second carbon nanotube layer on the semiconductor layer, the second carbon nanotube layer includes a number of second carbon nanotubes; finding and labeling a first metal carbon nanotube and a semiconductor carbon nanotube parallel to and spaced away from the first metal carbon nanotube; finding and labeling a second metal carbon nanotube, an extending direction of the second metal carbon nanotube is crossed with an extending direction of the first metal carbon nanotube and the semiconductor carbon nanotube; removing the other carbon nanotubes; and annealing the above structure.
US09859510B2
Novel ligands for metal complexes containing five-membered ring fused on pyridine or pyrimidine ring combined with partially fluorinated side chains exhibiting improved external quantum efficiency and lifetime are disclosed.
US09859506B2
A nitrogen-containing heterocyclic compound having a general formula (I) and an organic photoelectric apparatus are provided. The compound of general formula (I) is: wherein A1 to A4 are independently selected from a hydrogen atom, a function group having a general formula (II); A1 to A4 include at least one function group having the general formula (II); R1 and R2 are independently selected from one of hydrogen, deuterium, C1-30 alkyl group, C6-30 aromatic group and C2-30 heterocyclic aromatic group; Y1 and Y2 are independently selected from substituted or non-substituted C and N, the general formula (II) being: wherein X is selected from one of oxyl group (—O—), sulfhydryl group (—S—), substituted or non-substituted imino group, substituted or non-substituted methylene group, and substituted or non-substituted silicylene group; and R3 to R10 are independently selected from one of hydrogen, deuterium, C1-30 alkyl group, C6-30 aromatic group, and C2-30 heterocyclic aromatic group.
US09859504B2
The present disclosure generally relates to diamine compounds, which may be used as precursors in preparing diazaborole compounds and phosphorescent diazaborole metal complexes. The present disclosure also relates to diazaborole compounds, diazaborole metal complexes, and electroluminescent emission materials and electronic devices thereof. The present disclosure further relates to processes for preparing the diamine compounds and diazaborole metal complexes.
US09859503B2
According to one or more embodiments, an organic light-emitting device includes: a first electrode; a second electrode facing the first electrode; an emission layer between the first electrode and the second electrode; and a hole transport region between the first electrode and the emission layer. The hole transport region includes a first compound represented by Formula 1A and a second compound represented by Formula 1B:
US09859500B2
A method of fabricating a carbon nanotube based device, including forming a trench having a bottom surface and sidewalls on a substrate, selectively depositing a bi-functional compound having two reactive moieties in the trench, wherein a first of the two reactive moieties selectively binds to the bottom surface, converting a second of the two reactive moieties to a diazonium salt; and reacting the diazonium salt with a dispersion of carbon nanotubes to form a carbon nanotube layer bound to the bottom surface of the trench.
US09859497B2
he present invention relates to a method for manufacturing thin films consisting of SiO2 spheres of 250 nm in diameter, packed in a simple cubic structure and infiltrated with the organic luminescent polymer Poly[2-methoxy-5-(3′,7′-dimethyloctyloxy)-1,4-phenylene-vinylene] (MDMO-PPV). The thin film can be deposited onto a substrate of soda lime or indium oxide doped with tin (ITO). The manufacturing method includes the synthesis of a colloidal solution with the correct proportions of SiO2 spheres and a high-viscosity organic solvent and the subsequent treatment thereof by spin coating. The provided method makes it possible to obtain films having a controllable thickness and a good structural quality that can easily be attached as an active region in an organic light-emitting diode where, due to the film described herein, the emission of light produced by the active region is considerably improved.
US09859488B2
A magnetic memory device includes a reference magnetic pattern having a magnetization direction fixed in one direction, a free magnetic pattern having a changeable magnetization direction, and a tunnel barrier pattern disposed between the free and reference magnetic patterns. The free magnetic pattern has a first surface being in contact with the tunnel barrier pattern and a second surface opposite to the first surface. The magnetic memory device further includes a sub-oxide pattern disposed on the second surface of the free magnetic pattern, and a metal boride pattern disposed between the sub-oxide pattern and the second surface of the free magnetic pattern. The magnetization directions of the free and reference magnetic patterns are substantially perpendicular to the first surface of the free magnetic pattern.
US09859485B1
A method for packaging a thermoelectric module may include thermoelectric module accommodation, of accommodating at least one thermoelectric module in a housing having a base and a sidewall, electric wire sealing, of sealing an electric wire of the thermoelectric module with a sealing tube, bonding member interposing, of placing a cover having a top portion and a sidewall on top of the housing and interposing a bonding member between the sidewall of the housing and the sidewall of the cover, and bonding, of bonding the sidewall of the housing and the sidewall of the cover that are hermetically sealed by the bonding member, in which the bonding member may be formed of a resin material.
US09859484B2
A ceramic insulating film (150) having a heat conducting property and a light reflecting property is formed on a front surface of a substrate (100), and a light emitting element (110) is provided on the ceramic insulating film. This makes it possible to improve a heat dissipation characteristic and a light utilization efficiency of a light emitting apparatus (10) having the light emitting element (101) provided on the substrate (110).
US09859480B2
A light emitting device includes a package, at least one light emitting element, a light-transmissive resin, and a light reflecting resin. The package has a recess which includes a bottom surface and an inner peripheral surface. The bottom surface includes a light emitting element mounting region and a groove. The groove has an inner peripheral edge and an outer peripheral edge on the bottom surface to define the groove between the inner peripheral edge and the outer peripheral edge. The at least one light emitting element is mounted on the light emitting element mounting region. The light-transmissive resin is provided in the recess to cover the at least one light emitting element and to be in contact with the groove. The light reflecting resin is provided between the inner peripheral surface of the recess and the light-transmissive resin to reach the outer peripheral edge of the groove.
US09859472B2
A method of manufacturing a light emitting device includes: mounting at least one light emitting element on a support member with a first surface of the light emitting element facing upward; applying an adhesive to the first surface of the light emitting element by holding the support member and dipping the first surface of the light emitting element in the adhesive; and disposing a light-transmissive member on the first surface of the light emitting element via the adhesive.
US09859470B2
A light-emitting device is provided. The light-emitting device comprises: a light-emitting stack having an active layer emitting first light having a peak wavelength λ nm; and an adjusting element stacked electrically connected to the active layer in series for tuning a forward voltage of the light-emitting device; wherein the forward voltage of the light-emitting device is between (1240/0.8λ) volt and (1240/0.5λ) volt.
US09859466B2
Disclosed are a light emitting diode and a light emitting diode module. The light emitting diode module includes a printed circuit board and a light emitting diode joined thereto through a solder paste. The light emitting diode includes a first electrode pad electrically connected to a first conductive type semiconductor layer and a second electrode pad connected to a second conductive type semiconductor layer, wherein each of the first electrode pad and the second electrode pad includes at least five pairs of Ti/Ni layers or at least five pairs of Ti/Cr layers and the uppermost layer of Au. Thus a metal element such as Sn in the solder paste is prevented from diffusion so as to provide a reliable light emitting diode module.
US09859462B2
A semiconductor structure includes a silicon substrate, an aluminum nitride layer and a plurality of grading stress buffer layers. The aluminum nitride layer is disposed on the silicon substrate. The grading stress buffer layers are disposed on the aluminum nitride layer. Each grading stress buffer layer includes a grading layer and a transition layer stacked up sequentially. A chemical formula of the grading layer is Al1-xGaxN, wherein the x value is increased from one side near the silicon substrate to a side away from the silicon substrate, and 0≦x≦1. A chemical formula of the transition layer is the same as the chemical formula of a side surface of the grading layer away from the silicon substrate. The chemical formula of the transition layer of the grading stress buffer layer furthest from the silicon substrate is GaN.
US09859460B2
The present disclosure provides a light-emitting device. The light-emitting device comprises a substrate; a light-emitting stack which emits infrared (IR) light on the substrate; and a semiconductor window layer comprising AlGaInP series material disposed between the substrate and the light-emitting stack.
US09859454B2
In a thin film photoelectric conversion device fabricated by addition of a catalyst element with the use of a solid phase growth method, defects such as a short circuit or leakage of current are suppressed. A catalyst material which promotes crystallization of silicon is selectively added to a second silicon semiconductor layer formed over a first silicon semiconductor layer having one conductivity type, the second silicon semiconductor layer is partly crystallized by a heat treatment, a third silicon semiconductor layer having a conductivity type opposite to the one conductivity type is stacked, and element isolation is performed at a region in the second silicon semiconductor layer to which a catalyst material is not added, so that a left catalyst material is prevented from being diffused again, and defects such as a short circuit or leakage of current are suppressed.
US09859451B2
Photovoltaic cells, photovoltaic devices, and methods of fabrication are provided. The photovoltaic cells include a transparent substrate to allow light to enter the photovoltaic cell through the substrate, and a light absorption layer associated with the substrate. The light absorption layer has opposite first and second surfaces, with the first surface being closer to the transparent substrate than the second surface. A passivation layer is disposed over the second surface of the light absorption layer, and a plurality of first discrete contacts and a plurality of second discrete contacts are provided within the passivation layer to facilitate electrical coupling to the light absorption layer. A first electrode and a second electrode are disposed over the passivation layer to contact the plurality of first discrete contacts and the plurality of second discrete contacts, respectively. The first and second electrodes include a photon-reflective material.
US09859450B2
A method of making a CIGS/inorganic thin film tandem semiconductor device including the steps of depositing a textured buffer layer on an inexpensive substrate, depositing a metal-inorganic film from a eutectic alloy on the buffer layer, the metal being selected from a group of CIGS elements, and adding the remaining CIGS elements to the metal, thereby growing a CIGS film on the inorganic film for the tandem semiconductor device.
US09859447B2
A diode device and manufacturing method thereof are provided. The diode device includes a substrate, an epitaxial layer, a trench gate structure, a Schottky diode structure and a termination structure. An active region and a termination region are defined in the epitaxial layer. The Schottky diode structure and the trench gate structure are located in the active region and the termination structure is located in the termination region. The termination structure includes a termination trench formed in the epitaxial layer, a termination insulating layer, a first spacer, a second spacer and a first doped region. The termination insulating layer is conformingly formed on inner walls of the termination trench. The first and second spacers are disposed on two sidewalls of the termination trench. The first doped region formed beneath the termination trench has a conductive type reverse to that of the epitaxial layer.
US09859442B2
The invention provides a metal oxide semiconductor layer forming composition containing a solvent represented by formula [1]: (wherein R1 represents a C2 to C3 linear or branched alkylene group, and R2 represents a C1 to C3 linear or branched alkyl group) and an inorganic metal salt.
US09859441B2
In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.
US09859435B2
A display substrate includes a base substrate, a semiconductor active layer disposed on the base substrate, a gate insulating layer disposed on the semiconductor active layer, a first conductive pattern group disposed on the gate insulating layer and including at least a gate electrode, a second conductive pattern group insulated from the first conductive pattern group and including at least a source electrode, a drain electrode, and a data pad. The second conductive pattern group includes a first conductive layer and a second conductive layer disposed on the first conductive layer to prevent the first conductive layer from being corroded and oxidized.
US09859433B1
An advanced metal conductor structure is described. An integrated circuit device including a substrate having a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A metal layer fills a first portion of the set of features and is disposed over the adhesion promoting layer. A ruthenium layer is disposed over the metal layer. A cobalt layer is disposed over the ruthenium layer fills a second portion of the set of features. The cobalt layer is formed using a physical vapor deposition process.
US09859430B2
A semiconductor wafer is provided, where the semiconductor wafer includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. Fins are formed in the semiconductor substrate and the hard mask layer. A spacer is formed on an exposed sidewall of the hard mask layer and the semiconductor substrate. The exposed portion of the semiconductor substrate is etched. A silicon-germanium layer is epitaxially formed on the exposed portions of the semiconductor substrate. An annealed silicon-germanium region is formed by a thermal annealing process within the semiconductor substrate adjacent to the silicon-germanium layer. The silicon-germanium region and the silicon-germanium layer are removed. The hard mask layer and the spacer are removed.
US09859427B2
A semiconductor device includes a substrate, a fin structure disposed over the substrate and including a channel region and a source/drain region, a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure, a strain material layer disposed over the source/drain region, the strain material layer providing stress to the first channel region, and a contact layer wrapping around the first strain material layer. A width of the source/drain region is smaller than a width of the channel region.
US09859426B1
According to yet another non-limiting embodiment, a fin-type field effect transistor (finFET) including a strained channel region includes a semiconductor substrate extending along a first axis to define a length, a second axis perpendicular to the first axis to width, and a third direction perpendicular to the first and second axes to define a height. At least one semiconductor fin on an upper surface of the semiconductor substrate includes a semiconductor substrate portion on an upper surface of the semiconductor substrate, a strain-inducing portion on an upper surface of the semiconductor substrate portion, and an active semiconductor portion defining a strained channel region on an upper surface of the strain-inducing portion. A first height of the semiconductor substrate portion is greater than a second height of the strain-inducing portion.
US09859422B2
A field effect transistor having a higher breakdown voltage can be provided by forming a contiguous dielectric material layer over gate stacks, forming via cavities laterally spaced from the gate stacks, selectively depositing a single crystalline semiconductor material, and converting upper portions of the deposited single crystalline semiconductor material into elevated source/drain regions. Lower portions of the selectively deposited single crystalline semiconductor material in the via cavities can have a doping of a lesser concentration, thereby effectively increasing the distance between two steep junctions at edges of a source region and a drain region. Optionally, embedded active regions for additional devices can be formed prior to formation of the contiguous dielectric material layer. Raised active regions contacting a top surface of a substrate can be formed simultaneously with formation of the elevated active regions that are vertically spaced from the top surface.
US09859419B1
A MOSFET having a stacked-gate super-junction design and novel termination structure. At least some illustrative embodiments of the device include a conductive (highly-doped with dopants of a first conductivity type) substrate with a lightly-doped epitaxial layer. The volume of the epitaxial layer is substantially filled with a charge compensation structure having vertical trenches forming intermediate mesas. The mesas are moderately doped via the trench sidewalls to have a second conductivity type, while the mesa tops are heavily-doped to have the first conductivity type. Sidewall layers are provided in the vertical trenches, the sidewall layers being a moderately-doped semiconductor of the first conductivity type. The shoulders of the sidewall layers are recessed below the mesa top to receive an overlying gate for controlling a channel between the mesa top and the sidewall layer. The mesa tops are coupled to a source electrode, while a drain electrode is provided on the back side of the substrate.
US09859409B2
Transistors and methods of forming the same include forming a fin having an active layer between two sacrificial layers. A dummy gate is formed over the fin. Spacers are formed around the dummy gate. The dummy gate is etched away to form a gap over the fin. Material from the two sacrificial layers is etched away in the gap. A gate stack is formed around the active layer in the gap. Source and drain regions are formed in contact with the active layer.
US09859405B1
An HBT includes a semiconductor substrate having first and second principal surfaces opposite each other; and a collector layer, a base layer, and an emitter layer stacked in this order on the first principal surface side of the semiconductor substrate. The collector layer includes a first semiconductor layer with metal particles dispersed therein, the metal particles each formed by a plurality of metal atoms bonded with each other.
US09859398B2
A method for fabricating a semiconductor device is provided. The method includes forming a first fin-shaped pattern including an upper part and a lower part on a substrate, forming a second fin-shaped pattern by removing a part of the upper part of the first fin-shaped pattern, forming a dummy gate electrode intersecting with the second fin-shaped pattern on the second fin-shaped pattern, and forming a third fin-shaped pattern by removing a part of an upper part of the second fin-shaped pattern after forming the dummy gate electrode, wherein a width of the upper part of the second fin-shaped pattern is smaller than a width of the upper part of the first fin-shaped pattern and is greater than a width of an upper portion of the third fin-shaped pattern.
US09859395B2
A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.
US09859394B2
Provided herein are devices, systems, and methods of employing the same for the performance of bioinformatics analysis. The apparatuses and methods of the disclosure are directed in part to large scale graphene FET sensors, arrays, and integrated circuits employing the same for analyte measurements. The present GFET sensors, arrays, and integrated circuits may be fabricated using conventional CMOS processing techniques based on improved GFET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense GFET sensor based arrays. Improved fabrication techniques employing graphene as a reaction layer provide for rapid data acquisition from small sensors to large and dense arrays of sensors. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes, including DNA hybridization and/or sequencing reactions. Accordingly, GFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis within a gated reaction chamber of the GFET based sensor.
US09859390B2
Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.
US09859389B1
A method for forming a semiconductor device comprises forming a sacrificial gate stack on a substrate, spacers adjacent to the sacrificial gate stack, and a source/drain region on the substrate. A first insulator layer is formed on the source/drain region. A portion of the first insulator layer is removed to expose portions of the spacers. Exposed sidewall portions of the spacers are removed to reduce a thickness of the exposed portions of the spacers. A protective layer is deposited over the exposed sidewalls of the spacers and a second insulator layer is deposited over the protective layer. The sacrificial gate is removed to expose a channel region of the substrate. A gate stack is formed over the channel region of the substrate. Exposed portions of the first insulator layer and the second insulator layer are removed to expose the source/drain region, and a conductive is formed on the source/drain region.
US09859386B2
An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer, forming a first dielectric layer adjacent and over the first gate, etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer.
US09859381B2
A method of forming a semiconductor structure includes forming an opening in a dielectric layer, forming a recess in an exposed part of a substrate, and forming a lattice-mismatched crystalline semiconductor material in the recess and opening.
US09859379B2
A method to transfer a layer of graphene from one substrate to another substrate is provided. The method includes providing a first layered structure including, from bottom to top, a copper foil, a layer of graphene, an adhesive layer and a carrier substrate. The copper foil is removed exposing a surface of the layer of graphene. Next, an oxide bonding enhancement dielectric layer is formed on the exposed surface of the layer of graphene. A second layered structure including a receiver substrate and a dielectric oxide layer is provided. Next, an exposed surface of the dielectric oxide layer is bonded to an exposed surface of the oxide bonding enhancement dielectric layer. The carrier substrate and the adhesive layer are removed exposing the layer of graphene.
US09859376B2
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a multi-channel active pattern including germanium and an inner region and an outer region, the outer region formed along a profile of the inner region, and a germanium fraction of the outer region being smaller than a germanium fraction of the inner region. A gate electrode intersects the multi-channel active pattern.
US09859373B2
After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain for a transistor.
US09859369B2
A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate, and a p-type field effect transistor including a plurality of vertically stacked silicon germanium alloy nanowires located in another region of a semiconductor substrate. Each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a different shape than the shape of each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor.
US09859353B2
Semiconductor elements deteriorate or are destroyed due to electrostatic discharge damage. The present invention provides a semiconductor device in which a protecting means is formed in each pixel. The protecting means is provided with one or a plurality of elements selected from the group consisting of resistor elements, capacitor elements, and rectifying elements. Sudden changes in the electric potential of a source electrode or a drain electrode of a transistor due to electric charge that builds up in a pixel electrode is relieved by disposing the protecting means between the pixel electrode of the light-emitting element and the source electrode or the drain electrode of the transistor. Deterioration or destruction of the semiconductor element due to electrostatic discharge damage is thus prevented.
US09859351B2
An organic light-emitting diode display is disclosed. In one aspect, the display includes a substrate and a plurality of pixels formed over the substrate, each pixel including a first region from which light is emitted and a second region through which external light is transmitted. The display also includes a plurality of pixel circuit units each formed in the first region and including at least one thin-film transistor, an inorganic insulating film formed in the second region, a transparent conductive film formed over at least a portion of the inorganic insulating film, and an organic insulating film covering the pixel circuit units and at least a portion of the transparent conductive film. The display further includes a plurality of first electrodes formed over the organic insulating film and in the first regions of the pixels.
US09859350B2
An array substrate of an organic light-emitting display device, a fabrication method thereof and an organic light-emitting display device are provided. The array substrate comprises a plurality of pixel units arranged in array, wherein, at least one of the pixel units includes: an organic light-emitting diode (40) and a first thin film transistor (20) for controlling the organic light-emitting diode (40) which are formed on a base substrate (10), wherein, the organic light-emitting diode (40) includes a first electrode (107), a second electrode (110) and a light-emitting layer (109) located between the first electrode (107) and the second electrode (110), the first electrode (107) of the organic light-emitting diode (40) being connected with a drain electrode (104) of the first thin film transistor (20); and a conductive layer (111) and an insulating layer (112) formed between the first thin film transistor (20) and the organic light-emitting diode (40), wherein, the first electrode (107) of the organic light-emitting diode (40), the insulating layer (111) and the conductive layer (112) form a capacitor, and the conductive layer (111) is connected with a first gate electrode (100) of the first thin film transistor (20). The array substrate of the organic light-emitting display device, the fabrication method thereof and the organic light-emitting display device can effectively increase a storage capacitance value of a pixel unit, so as to improve display quality.
US09859344B2
An organic light-emitting display device, including a substrate that includes a plurality of first emission portions that realize a first color and a plurality of second emission portions that realize a second color; a pixel-defining film that defines the plurality of first emission portions and the plurality of second emission portions; a plurality of pixel electrodes that are separate from each other and respectively correspond to the plurality of first emission portions; and a first stacked structure that includes an intermediate layer and a counter electrode on the intermediate layer, the intermediate layer including an organic emission layer emitting light of the first color, the first stacked structure further including first emission pattern portions respectively corresponding to the plurality of first emission portions, and first connection pattern portions on the pixel-defining film, the first connection pattern portions connecting the first emission pattern portions.
US09859342B2
An organic light emitting diode display that maintains a luminance distribution characteristic of each pixel at the side substantially similar to a luminance distribution characteristic of each pixel at the front of the OLED display by improving a twist of a lateral color with respect to a front color. The organic light emitting diode display includes a substrate, a driving wire disposed on the substrate, a color filter disposed on the driving wire. The color filter includes a blue color filter, a red color filter, and a green color filter formed on the driving wire; and an organic light emitting diode disposed on the color filter, where a width of the blue color filter is greater than a width of the red color filter or the green color filter.
US09859338B2
Provided is a three-dimensional resistive memory including a channel pillar, a first gate pillar, a first gate dielectric layer, first and second stacked structures, a variable resistance pillar and an electrode pillar. The channel pillar is on a substrate. The first gate pillar is on the substrate and at a first side of the channel pillar. The first gate dielectric layer is between the channel pillar and the first gate pillar. The first and second stacked structures are on the substrate and respectively at opposite second and third sides of the channel pillar. Each of the first and second stacked structures includes conductive material layers and insulating material layers alternately stacked. The variable resistance pillar is on the substrate and at a side of the first stacked structure opposite to the channel pillar. The electrode pillar is on the substrate and inside of the variable resistance pillar.
US09859328B2
A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region. A blocking layer is formed on the substrate, and the blocking layer includes a first opening exposing a portion of the substrate in the pixel region and a second opening exposing a portion of the transistor. A first conductive body is formed in the first opening and a second conductive body is formed in the second opening, respectively. The first conductive body protrudes from the substrate and the second conductive body protrudes from the transistor. A portion of the blocking layer is removed. A first salicide layer is formed on the first conductive body and a second salicide layer is formed on the second conductive body, respectively.
US09859320B2
A chip package includes a chip, an insulating layer and a conductive layer. The chip includes a substrate, an epitaxy layer, a device region and a conductive pad. The epitaxy layer is disposed on the substrate, and the device region and the conductive pad are disposed on the epitaxy layer. The conductive pad is at a side of the device region and connected to the device region. The conductive pad protrudes out of a side surface of the epitaxy layer. The insulating layer is disposed below the substrate and extended to cover the side surface of the epitaxy layer. The conductive layer is disposed below the insulating layer and extended to contact the conductive pad. The conductive layer and the side surface of the epitaxy layer are separated by a first distance.
US09859317B2
An optical apparatus including an optical functional layer having a high refractive index and a method of manufacturing the optical apparatus are provided. The optical functional layer includes a phase change material that has a first refractive index during heat treatment in a first temperature range and has a second refractive index, which is higher than the first refractive index, during heat treatment in a second temperature range that is higher than the first temperature range. The optical functional layer may be configured to have the second refractive index by using a micro-heater without having to be deposited at a high temperature.
US09859315B2
A radiation image-pickup device includes: a plurality of pixels configured to generate signal charge based on radiation; and a field effect transistor used to read out the signal charge from the plurality of pixels. The transistor includes a first silicon oxide film, a semiconductor layer, and a second silicon oxide film laminated in order from a substrate side, the semiconductor layer including an active layer, and a first gate electrode disposed to face the semiconductor layer, with the first or the second silicon oxide film interposed therebetween, and the first or the second silicon oxide film or both include an impurity element.
US09859307B2
A display panel and manufacturing method. The method includes: forming a source electrode, a drain electrode and a channel on a substrate; depositing a first insulation layer; forming multiple color photoresists on the first insulation layer, and the source electrode, the drain electrode and the channel are located between two adjacent color photoresists; forming a gate electrode and a common electrode by a same process, and the gate electrode is located on the first insulation layer, and the common electrode is located on the photoresist; forming a second insulation layer having a through hole communicated with the source electrode on the gate electrode and the common electrode; forming a pixel electrode on the second insulation layer. The pixel electrode contacts with the source electrode through the through hole, and a storage capacitor is formed. The storage capacitor can be increased and the current leakage of the pixel electrode improved.
US09859305B2
Provided are liquid crystal display and the method for manufacturing the same. According to an aspect of the present invention, there is provided a liquid crystal display device, including a first substrate; a gate electrode disposed on the first substrate; a semiconductor pattern layer disposed on the gate electrode; and a source electrode and a drain electrode disposed on the semiconductor pattern layer and facing each other, wherein a diffusion prevention pattern is disposed on the semiconductor pattern layer to prevent diffusion into the semiconductor pattern layer or to maintain uniform thickness of the semiconductor pattern layer.
US09859301B1
A method for forming a hybrid semiconductor device includes growing a stack of layers on a semiconductor substrate. The stack of layers includes a bottom layer in contact with the substrate, a middle layer on the bottom layer and a top layer on the middle layer. First and second transistors are formed on the top layer. A protective dielectric is deposited over the first and second transistors. A trench is formed adjacent to the first transistors to expose the middle layer. The middle layer is removed from below the first transistors to form a cavity. A dielectric material is deposited in the cavity to provide a transistor on insulator structure for the first transistors and a bulk substrate structure for the second transistors.
US09859300B2
To provide a light-emitting device or an input/output device with little unevenness in display luminance or high reliability and to provide an input/output device with high detection sensitivity, a light-emitting device is configured to include a first substrate, a light-emitting element over the first substrate, a first conductive layer over the light-emitting element, a first insulating layer over the first conductive layer, a second conductive layer over the first insulating layer, and a second substrate over the second conductive layer. The light-emitting element includes a first electrode over the first substrate, a layer containing a light-emitting organic compound over the first electrode, and a second electrode over the layer containing a light-emitting organic compound. The second electrode is electrically connected to the first and second conductive layers. The first conductive layer and the second electrode transmit light emitted from the light-emitting element. The resistance of the second conductive layer is lower than that of the second electrode.
US09859297B2
A semiconductor device includes a substrate including cell and dummy regions, first channel structures on the cell region and extending in a first direction vertical with respect to the substrate, gate lines surrounding outer sidewalls of the first channel structures and extending in a second direction parallel to the substrate, the gate lines being spaced apart from each other along the first direction, cutting lines between the gate lines on the cell region and extending in the second direction, dummy patterns spaced apart from each other along the first direction on the dummy region, the dummy patterns having a stepped shape along a third direction parallel to the top surface of the substrate and perpendicular to the second direction, at least a portion of the dummy patterns including a same conductive material as that in the gate lines, and dummy lines through the dummy patterns.
US09859296B2
A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.
US09859283B1
A semiconductor memory structure includes a substrate including a memory cell region, a peripheral circuit region and a cell edge region defined thereon, and the cell edge region is defined in between the memory cell region and the peripheral circuit region. The semiconductor memory structure includes a plurality of active regions formed in the memory cell region, the cell edge region and the peripheral circuit region, and at least a dummy bit line formed on the active regions in the cell edge region. The dummy bit line is extended along a first direction and overlaps at least two active regions in a second direction. And the first direction and the second direction are perpendicular to each other. The dummy bit line includes a first inner line portion and an outer line portion, and the first inner line portion and the outer line portion include different widths and different spacers.
US09859276B2
A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.
US09859271B2
An ESD protection semiconductor device includes a substrate, a buried layer buried in the substrate, a first well formed in the substrate, a first doped region formed in the first well, a second doped region formed in the first well and adjacent to the first doped region, a second well formed in the first well, and a third doped region formed in the second well. The buried layer, the first well, the first doped region, and the third doped region include a first conductivity type while the second doped region and the second well include a second conductivity type complementary to the first conductivity type. The second well is spaced apart from the first doped region and the second doped region by the first well.
US09859266B2
Presented herein is a package comprising a carrier device of a device stack and at least one top device of the device stack mounted on a first side of the carrier device. A lid is mounted on the first side of the carrier device, with a first portion of the lid attached to the carrier device and a second portion of the lid extending past and overhanging a respective edge of the carrier device. The lid comprises a recess disposed in a first side, and the at least one top device is disposed within the recess. A thermal interface material disposed on the top device and contacts a surface of the recess.
US09859251B2
A semiconductor device package includes an electronic component and an electrical interconnect. The electronic component is attached to the electrical interconnect. The electrical interconnect is configured to electrically couple the electronic component to external terminals of the semiconductor device package. The electrical interconnect has a first main face facing the electronic component and a second main face opposite the first main face. The semiconductor device package further includes a first semiconductor chip facing the second main face of the electrical interconnect.
US09859247B2
A method is provided for assembly of a micro-electronic component, in which a conductive die bonding material is used. This material includes a conductive thermosettable resin material or flux based solder and a dynamic release layer adjacent to the conductive thermoplastic material die bonding material layer A laser beam is impinged on the dynamic release layer, adjacent to the die bonding material layer, in such a way that the dynamic release layer is activated to direct conductive die bonding material matter towards the pad structure to be treated, to cover a selected part of the pad structure with a transferred conductive die bonding material. The laser beam is restricted in timing and energy, in such a way that the die bonding material matter remains thermosetting. Accordingly, adhesive matter can be transferred while preventing that the adhesive is rendered ineffective by thermal overexposure in the transferring process.
US09859233B1
A semiconductor device package includes an encapsulation layer, a die, at least one trace stiffener, and a redistribution layer. The encapsulation layer has an opening. The die is disposed in the opening of the encapsulation layer. The redistribution layer is formed above the die and the encapsulation layer. The least one trace stiffener are formed on the redistribution layer above boundaries of the encapsulation layer and the die for reinforcing a structure of the redistribution layer above the boundaries of the encapsulation layer and the die.
US09859232B1
The present disclosure provides a semiconductor package device comprising a substrate, a semiconductor device, a first electronic component, an antenna pattern and a first package body. The substrate has a first area and a second area. The semiconductor device is disposed on the first area of the substrate. The first electronic component is disposed on the second area of the substrate. The antenna pattern is disposed on the second area of the substrate and electrically connected to the first electronic component. The first package body encapsulates the first area of the substrate and the semiconductor device and exposes the antenna pattern, the first electronic component and the second area of the substrate.
US09859228B2
Provided is a device for generating an identification key using a process variation during a manufacturing process of a conductive layer. The device for generating an identification key may include a conductive layer, which is disposed between a first node and a second node in a semiconductor chip, and which has a width that is at least a first threshold value but not more than a second threshold value, the first threshold value and the second threshold value being less than the minimum width according to the design rules that can ensure that the conductive layer is patterned such that the first node and the second node are electrically short-circuited, and a reader which provides an identification key by identifying if there is a short circuit between the first node and the second node.
US09859225B2
Fabrication of radio-frequency (RF) devices involves providing a field-effect transistor (FET) formed over an oxide layer formed on a semiconductor substrate, removing at least part of the semiconductor substrate to expose at least a portion of a backside of the oxide layer, applying an interface material to at least a portion of the backside of the oxide layer, removing at least a portion of the interface material to form a trench, and covering at least a portion of the interface material and the trench with a substrate layer to form a cavity.
US09859211B2
In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.
US09859203B2
A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for manufacturing thereof, that comprise interposer, interlayer, and/or heat dissipater configurations that provide for low cost, increased manufacturability, and high reliability.
US09859196B2
An electronic device may include leads, an IC having first and second bond pads, and an encapsulation material adjacent the leads and the IC so the leads extend to a bottom surface of the encapsulation material defining first contact pads. The electronic device may include bond wires between the first bond pads and corresponding ones of the leads, and conductors extending from corresponding ones of the second bond pads to the bottom surface of the encapsulation material defining second contact pads.
US09859194B2
A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating material 112 attached to side surfaces of the semiconductor chip 106, the first insulating material 110 and an island 102. The semiconductor chip 106 is fixed to the island 102 via the first insulating material 110 and the second insulating material 112. The first insulating material 110 ensures a high dielectric strength between the semiconductor chip 106 and the island 102. Though the second insulating material 112 having a modulus of elasticity greater than that of the first insulating material 110, the semiconductor chip 106 is firmly attached to the island 102.
US09859190B2
Provided herein is a resin structure having high heat dissipation, and desirable adhesion at the interface with a heat generating device. The resin structure is provided on a substrate to dissipates heat of the substrate to outside, and includes: a water-based coating material layer provided on the substrate and including a water-based coating material, and fillers having an average particle size of 30 μm to 150 μm; and a resin layer provided on the water-based coating material layer and containing a thermosetting resin. The fillers have a far-infrared emissivity of 0.8 or more, and an average aspect ratio of 1 to 12 as measured as a ratio of lengths along the long axis and the short axis through the center of gravity of the fillers. At least 80% of the total number of fillers has a length that is at least 1.7 times longer than the total thickness of the water-based coating material of the water-based coating material layer and the thermosetting resin of the resin layer, as measured along the long axis through the center of gravity of the fillers.
US09859188B2
A die interconnect system having a plurality of connection pads, a heat generating element thermally isolated from the die, one or more leads extending from the die to the heat generating element, each lead having a metal core with a core diameter, a dielectric layer surrounding the metal core with a dielectric thickness, and an outer metal layer attached to ground, wherein one or more leads are exposed to ambient conditions and/or are convectively or contact cooled for at least a portion of their length to minimize heat transfer from the heat generating element to the die.
US09859186B2
A heat sink for a semiconductor chip device includes cavities in a lower surface thereof for receiving electrical components on a top surface of the semiconductor chip, and a pedestal extending through an opening in the semiconductor chip for contacting electrical components on a bottom surface of the semiconductor chip. A lid may also be provided on the bottom surface of the semiconductor chip for protecting the electrical components and for heat sinking the electrical components to an adjacent device or printed circuit board.
US09859178B2
A microwave module is described. The microwave module includes a base bracket, a window plate and a lid. The base bracket is configured to contain a photoconductive switch, a radio-frequency transformer and dielectric oil. The window plate, which is transparent to optical light, covers a first portion of the base bracket in which the photoconductive switch is located. The window plate is sealed to the base bracket. The lid, which includes a cutout to allow the radio-frequency transformer to pass through the lid, covers a second portion of the base bracket in which the radio-frequency transformer is located. The window plate is sealed to the base bracket, and the lid is sealed to the window plate, the base bracket and the radio-frequency transformer to contain the dielectric oil within the microwave module.
US09859176B1
A semiconductor device is disclosed. The semiconductor device includes: a System on Chip (SoC) die; an integrated passive device (IPD); and a first switch, coupled between the SoC die and the IPD; wherein the IPD and the SoC die are disposed in different wafers and bonded together, and the first switch is controlled to disconnect the IPD from the SoC die when the IPD is under a test; and the first switch is controlled to connect the IPD with the SoC die when the IPD is not under the test. A test system for testing an IPD of a semiconductor device and an associated method are also disclosed.
US09859171B2
A semiconductor device includes a first active region including at least one first recess; a second active region including at least one second recess; an isolation region including a diffusion barrier that laterally surrounds at least any one active region of the first active region and the second active region; a first recess gate filled in the first recess; and a second recess gate filled in the second recess, wherein the diffusion barrier contacts ends of at least any one of the first recess gate and the second recess gate.
US09859169B2
A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.
US09859166B1
A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins over a source/drain region, forming a first spacer within troughs defined by the plurality of fins and depositing a high-k dielectric layer, a work function material layer, and a conducting layer. The method further includes etching the high-k dielectric layer, the work function material layer, and the conducting layer to form recesses between the plurality of fins, depositing a liner dielectric, and etching portions of the liner dielectric to form a plurality of second spacers having a U-shaped configuration. The method further includes forming an epitaxial layer over the plurality of fins such that a gap region is defined between the plurality of second spacers and the epitaxial layer.
US09859161B2
An interconnect structure and a method for forming it is disclosed. In one aspect, the method includes the steps of providing a first entity. The first entity includes a first set of line structures. The first set of line structures include a first set of conductive lines, and a first set of dielectric lines made of a first dielectric material and aligned with and overlaying the first set of conductive lines. The first entity also includes gaps separating the line structures and filled with a second dielectric material of such a nature that the first dielectric material can be selectively etched with respect to the second dielectric material. The method also includes providing a patterned mask on the first entity. The method further includes etching selectively the first dielectric material through the patterned mask so as to form one or more vias in the first dielectric material. The method also includes removing the patterned mask.
US09859158B2
A method for manufacturing a semiconductor device includes forming a device isolation layer in a substrate to define an active region, forming a gate insulating layer covering at least a portion of the active region, forming a gate electrode on the gate insulating layer, and forming an interlayer insulating layer on the gate electrode. The gate insulating layer includes a first portion overlapping with the active region and a second portion overlapping with the device isolation layer. The forming of the gate insulating layer includes etching at least a part of the second portion of the gate insulating layer to thin the part of the second portion of the gate insulating layer.
US09859155B1
An advanced metal conductor structure is described. An integrated circuit device includes a substrate having a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A ruthenium layer is disposed over the adhesion promoting layer. A cobalt layer is disposed over the ruthenium layer filling a first portion of the set of features. The cobalt layer is formed using a physical vapor deposition process. A metal layer is disposed over the cobalt layer filling a second portion of the set of features.
US09859144B2
In a plasma processing process used for a method of manufacturing element chips by which a plurality of element chips are manufactured by dividing a substrate having a plurality of element regions, the substrate is exposed to first plasma, and thereby the substrate is divided into element chips, and the element chips having first surfaces, second surfaces, and side surfaces connecting the first surfaces to the second surfaces are held with an interval between the element chips on the carrier. The element chips are exposed to second plasma which uses a mixed gas of fluorocarbon and helium as a raw material gas, and thereby a protection film covering the side surfaces is formed, and a conductive material is prevented from creeping up to the side surfaces during a mounting process.
US09859138B2
Apparatuses and methods for improved substrate defect detection is provided. Substrate defects may be detected, possibly with defect detection equipment such as laser metrology equipment. Defects smaller than the detection limit of the detection equipment may be decorated with a layer of material to increase the effective sizes of the defects. The thickness and composition of the material deposited may be tuned depending on the composition of the substrate and the defects. The composition of the detected defects may be identified with defect identification equipment. The defect identification equipment may be an electron generating apparatus and the composition of the defects may be identified from the interaction of the electrons with the defect. The deposited material may be removed either before or during the defect identification phase to aid in the identification of the defect composition.
US09859130B2
A manufacturing method of an interposed substrate is provided. A photoresist layer is formed on a metal carrier. The photoresist layer has plural of openings exposing a portion of the metal carrier. Plural of metal passivation pads and plural of conductive pillars are formed in the openings. The metal passivation pads cover a portion of the metal carrier exposed by openings. The conductive pillars are respectively stacked on the metal passivation pads. The photoresist layer is removed to expose another portion of the metal carrier. An insulating material layer is formed on the metal cattier. The insulating material layer covers the another portion of the metal carrier and encapsulates the conductive pillars and the metal passivation pads. An upper surface of the insulating material layer and a top surface of each conductive pillar are coplanar. The metal carrier is removed to expose a lower surface of the insulating material layer.
US09859128B2
Methods of etching silicon nitride faster than silicon or silicon oxide are described. Methods of selectively depositing additional material onto the silicon nitride are also described. Exposed portions of silicon nitride and silicon oxide may both be present on a patterned substrate. A self-assembled monolayer (SAM) is selectively deposited over the silicon oxide but not on the exposed silicon nitride. Molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety forming a bond with the OH group on the exposed silicon oxide portion and the tail moiety extending away from the patterned substrate. A subsequent exposure to an etchant or a deposition precursor may then be used to selectively remove silicon nitride or to selectively deposit additional material on the silicon nitride.
US09859123B1
A method for fabricating a semiconductor device is disclosed. A substrate having a conductive region is provided. A metal layer is deposited on the conductive region. The metal layer reacts with the conductive region to form a first metal silicide layer. A TiN layer is deposited on the metal layer. A SiN layer is deposited on the TiN layer. An annealing process is performed to convert the first metal silicide layer into a second metal silicide layer.
US09859120B1
A method includes providing a structure having a dielectric layer, a 1st hardmask layer, a 2nd hardmask layer and a 1st mandrel layer disposed respectively thereon. A 1st mandrel plug is disposed in the 1st mandrel layer. A 2nd mandrel layer is disposed over the 1st mandrel layer. The 1st and 2nd mandrel layers are etched to form a plurality 1st mandrels, wherein the 1st mandrel plug extends entirely through a single 1st mandrel. The 1st mandrel plug is etched such that it is self-aligned with sidewalls of the single 1st mandrel. The 1st mandrels are utilized to form mandrel metal lines in the dielectric layer. The 1st mandrel plug is utilized to form a self-aligned mandrel continuity cut in a single mandrel metal line formed by the single 1st mandrel.
US09859118B2
The present invention, when forming a pattern on a substrate, forms a film of a block copolymer containing at least two polymers on the substrate, heats the film of the block copolymer under a solvent vapor atmosphere to subject the block copolymer to phase separation, and removes one of the polymers in the film of the phase-separated block copolymer, thereby accelerating fluidization of the polymers of the block copolymer to enable acceleration of the phase separation.
US09859116B2
A method for preparing a sol-gel film is disclosed. The method comprises providing a sol-gel composition comprising one or more sol-gel film precursors and a crystallization aid, and processing the sol-gel composition by solution processing to form the sol-gel film. In certain embodiments, the sol-gel film comprises one or more metal oxides. A preferred crystallization aid includes triphenylphosphine oxide. A composition for making a sol-gel film, a sol-gel film, a device including a sol-gel film and a method for making such device are also disclosed.
US09859110B2
An ultrasonic wave applying liquid is supplied to one principal surface of a substrate while a liquid film of a first liquid being formed on another principal surface of the substrate. The ultrasonic wave applying liquid is obtained by applying ultrasonic waves to a second liquid. Ultrasonic vibration is transmitted to the other principal surface and the liquid film, thereby ultrasonically cleaning the other principal surface. The first liquid has a higher cavitation intensity, which is a stress per unit area acting on the substrate by cavitation caused in the liquid when ultrasonic waves are transmitted to the liquid present on the principal surface of the substrate, than the second liquid.
US09859109B2
Disclosed is a substrate processing apparatus, a substrate processing method and a computer-readable medium capable of recovering an extended amount of discharged solution from a processing unit thereby reducing the amount of deionized water for the processing and the cost. The substrate processing apparatus includes, inter alia, a first and second discharge solution lines each connected to a downstream side of a discharge unit, and the discharged solution from each of the first and second discharge solution lines is independently delivered to the processing solution supply unit as a recovered solution. Also, the substrate processing apparatus includes a converting unit that converts flow of the discharged solution from the discharge unit either to the first discharge solution line or to the second discharge solution line. The processing solution supply unit selectively delivers the recovered solution from the first and second discharge solution lines to the processing unit.
US09859097B2
A permanently sealed vacuum tube is used to provide the electrons for an electron microscope. This advantageously allows use of low vacuum at the sample, which greatly simplifies the overall design of the system. There are two main variations. In the first variation, imaging is provided by mechanically scanning the sample. In the second variation, imaging is provided by point projection. In both cases, the electron beam is fixed and does not need to be scanned during operation of the microscope. This also greatly simplifies the overall system.
US09859091B1
An automatic method is provided to align a semiconductor crystalline substrate for electron channeling contrast imaging (ECCI) in regions where an electron channeling pattern cannot be reliably obtained but crystalline defects need to be imaged. The automatic semiconductor crystalline substrate alignment method is more reproducible and faster than the current operator intensive process for ECCI alignment routines. Also, the automatic semiconductor crystalline substrate alignment method increases the throughput of ECCI.
US09859090B2
A self-cleaning linear ionizer with at least one ionizing electrode, at least one electrode-cleaner, and at least two spool assemblies is disclosed. The electrode has opposing ends and defines an axial working length with a surface that produces an ion cloud and develops degradation products with use. Although the working length of the electrode is stationary, the electrode is movable. The electrode-cleaner is also stationary and selectively engages the electrode along its working length. The opposing ends of the electrode are fixed to the opposing spool assemblies which selectively move the ionizing electrode such that the electrode-cleaner removes at least some of the surface degradation products from the electrode during movement. Methods of using the disclosed ionizer have self-cleaning and ionization modes of operation, which may occur cyclically, alternately, or simultaneously, are also disclosed.
US09859089B2
A structure for grounding an extreme ultraviolet mask (EUV mask) is provided to discharge the EUV mask during the inspection by an electron beam inspection tool. The structure for grounding an EUV mask includes at least one grounding pin to contact conductive areas on the EUV mask, wherein the EUV mask may have further conductive layer on sidewalls or/and back side. The inspection quality of the EUV mask is enhanced by using the electron beam inspection system because the accumulated charging on the EUV mask is grounded. The reflective surface of the EUV mask on a continuously moving stage is scanned by using the electron beam simultaneously. The moving direction of the stage is perpendicular to the scanning direction of the electron beam.
US09859078B2
An electromagnetic relay includes a fixed contact having a fixed contact plate and a fixed contact point mounted to the fixed contact plate, a movable contact having a movable contact plate and a movable contact point mounted to the movable contact plate, and an electromagnet device configured to move the movable contact so as to bring the movable contact point in contact with the fixed contact point, wherein a contact plate that is at least one of the fixed contact plate and the movable contact plate has a contact area, the contact area being thinner than other areas of the contact plate and having a penetrating hole formed therethrough, and the contact point of the contact plate has a head and a shaft, and wherein while the shaft is placed in the penetrating hole such that the head is mounted on a first surface of the contact area, an end of the shaft is deformed with a force at a second surface opposite the first surface to mount the contact point to the contact plate.
US09859069B2
A handle assembly and related methods for actuating a mechanism such as a disconnect switch.
US09859068B2
Circuit breakers with a rotary handle attached to an inwardly oriented shaft that connects to a gear assembly that translates rotational input to linear input also include a trip assist spring in communication with the rack gear so that, in operation, the trip assist spring applies a force to the operator slider and forces the handle to a consistent trip position.
US09859064B2
A method for producing an activated carbon sheet having high electrolyte impregnation capacity and high mechanical strength is provided. The method for producing an activated carbon sheet includes a sheet preparation step of preparing a sheet including an activated carbon, an electrically conductive carbon material, and a fibrous fluorocarbon resin binder, which fluorocarbon resin is polytetrafluoroethylene and/or modified polytetrafluoroethylene; and a light irradiation step of performing light irradiation of at least one side of the sheet such that the cumulative irradiation dose on the sheet surface is 50 to 1000 mJ/cm2.
US09859061B2
[Theme] To provide a chip capacitor capable of easily and rapidly accommodating a plurality of types of capacitance values using a common design and a method for manufacturing the chip capacitor. [Solution] A chip capacitor 1 includes a substrate 2, a first external electrode 3, a second external electrode 4, capacitor elements C1 to C19, and fuses F1 to F9 disposed on the substrate 2. The capacitor elements C1 to C19 respectively include a first electrode film 11, a first capacitance film 12 on the first electrode film 11, a second electrode film 13 disposed on the first capacitance film 12 and facing the first electrode film 11, a second capacitance film 17 on the second electrode film 13, and a third electrode film 16 disposed on the second capacitance film 17 and facing the second electrode film 13 and are connected between the first external electrode 3 and the second external electrode 4. The fuses F1 to F9 are each interposed between the capacitor elements C1 to C19 and the first external electrode 3 or the second external electrode 4 and are capable of disconnecting each of the capacitor elements C1 to C19.
US09859055B2
Provided is a method for manufacturing a rare-earth magnet capable of manufacturing a rare-earth magnet with high degree of orientation by sufficient plastic deformation while suppressing cracks at the side faces of a compact that is plastic-deformed during the hot deformation processing. The method includes a step of preparing a compact S, preparing a plastic processing mold including a die D in which a cavity Ca is provided, and punches P that are slidable in the cavity Ca, the cavity Ca having a cross section that is larger in cross-sectional dimensions than a cross section of the compact S that is orthogonal to a pressing direction by the punches P; and a step of placing the compact S in the cavity Ca and performing hot deformation processing, thus manufacturing an orientational magnet C. Let that W1 denotes a length of a short side of the cross section of the cavity Ca and t1 denotes a length of a side of the cross section of the compact S that is placed in the cavity Ca, the side corresponding to the short side of the cavity Ca, t1/W1 is within a range of 0.55 to 0.85, and from some stage during the hot deformation processing, a part of the compact S is constrained at a side face of the cavity Ca so that deformation of the compact is suppressed, but another part of the compact is in a non-constraint state.
US09859053B2
An electronic device is provided. The electronic device includes a battery; a non-contact near field communication antenna; a wireless charging coil; and a case covering the battery, wherein the wireless charging coil is positioned between the battery and the case, and wherein one of the non-contact near field communication antenna and the wireless charging coil is positioned to surround the other one of the non-contact near field communication antenna and the wireless charging coil.
US09859050B2
A magnetic element includes a first magnetic core, a second magnetic core and a plurality of conducting wires. The first magnetic core includes a first coiling body, a first protruding portion and a second protruding portion. The second magnetic core includes a second coiling body, a third protruding portion and a fourth protruding portion. A soldering surface of the first protruding portion is parallel and next to a soldering surface of the fourth soldering surface. Since an extension direction of the first magnetic core is extended from the soldering surface of the first protruding portion, an extension direction of the second magnetic core is extended from the soldering surface of the second protruding portion, and the plurality of conducting wires can be coiled on the first and the second coiling bodies respectively, the transformer can provide more space for coiling than the prior art.
US09859043B2
Magnetic component assemblies including moldable magnetic materials formed into magnetic bodies, at least one conductive coil, and termination features are disclosed that are advantageously utilized in providing surface mount magnetic components such as inductors and transformers.
US09859040B2
A cable includes a jacket, a shielding tape, a pair of wires, an inner and outer jacket layer, and a separator. The shielding tape includes a substrate and a plurality of conductive shield segments disposed on the substrate. The pair of wires form a twisted pair. The inner and outer jacket layers are extruded onto inner and outer surfaces, respectively, of the substrate. The substrate, the inner jacket layer and the outer jacket layer are bonded together into a single layer that defines a circumference. Each of the conductive shield segments: extends only partially around the circumference of the single layer; is longitudinally spaced from each longitudinally adjacent one of the conductive shield segments; is radially spaced from, and overlaps a portion of, each immediately circumferentially adjacent one of the conductive shield segments; and is embedded in at least one of the inner jacket layer and the outer jacket layer.
US09859037B2
A downhole cable that has a cable core with an inner jacket located about it. The inner jacket has a shell located thereabout, and a pair of strength member layers surrounds the inner shell. Interstitial spaces of the strength member layers are filled with bonding layers. One of the strength member layers is at a contra-helical lay angle to the other. An outer jacket is located about one of the strength member layers, and the outer jacket is bonded with the bonding layers.
US09859030B2
A method of manufacturing a composite powder using wire explosion and a composite powder prepared by such a method are provided. The method of manufacturing a composite powder may involve coating a metal wire with a carbon-based material, and performing wire explosion on the metal wire coated with the carbon-based material in a solution. The prepared composite powder may include a metal core and a multilayer graphene film that coats a surface of the metal core.
US09859028B2
The invention concerns to a method of producing a Fresnel Zone Plate (1) for applications in high energy radiation including the following steps: supply of a substrate (2) transparent for high energy radiation, deposition of a layer (3) of a metal, a metal alloy or a metal compound on a planar surface (4) of the substrate (2), calculating a three dimensional geometrical profile (5) with a mathematical model, setting up a dosage profile (6) for an ion beam of the ion beam lithography inverse to the calculated three dimensional geometrical profile (5) and milling a three dimensional geometrical profile (5) with concentric zones into the layer (3) with ion beam lithography by means of focused ion beam.
US09859026B2
An austenitic alloy tube subjected to a cold working and an annealing heat treatment contains C: 0.01% to 0.15%, Cr: 10.0% to 40.0%, Ni: 8.0% to 80.0%, in mass %, and has a metallographic structure satisfying the following Expressions (i) to (iii). R≦f1 (i) R=I220/I111 (ii) f1=0.28×(F1118.0/(F1118.0+0.358.0)) (iii) Where, in the above Expressions, R is a ratio of an integrated intensity of {220} to an integrated intensity of {111} on a surface layer which is measured by a grazing incidence X-ray diffraction method, I220 is the integrated intensity of {220}, I111 is the integrated intensity of {111}, and F111 is full width of half maximum of {111} on the surface layer which is measured by the grazing incidence X-ray diffraction method.
US09859022B2
A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array.
US09859011B1
A semiconductor memory device includes first and second memory cells, first and second word lines that are respectively connected to gates of the first and second memory cells, and a control circuit that executes first and second read operations in response to first and second command sets, respectively. The first read operation includes a first read sequence, in which the control circuit reads data by applying first to third voltages to the first word line, and a second read sequence, in which the control circuit reads data by applying a first read voltage that is set based on the result of the first read sequence, to the first word line. In the second read operation, the control circuit reads data by applying a second read voltage that is set based on the result of the first read sequence of the first read operation, to the second word line.
US09859009B2
There are provided a high voltage switch circuit and a semiconductor memory device including the same. A high voltage switch circuit may include a switching circuit including a first depletion transistor and a first high voltage transistor, which are coupled in series between an input terminal and an output terminal, and a control signal generator for applying, to the first depletion transistor, a control signal having the same potential level as an input voltage applied to the input terminal, in response to a first enable signal and a second enable signal.
US09858998B2
According to one embodiment, there is provided a semiconductor storage device including N word lines, M bit lines, multiple memory cells, and a read circuit. N is an integer of four or greater. M is an integer of two or greater. The M bit lines intersect with the word lines. The multiple memory cells are placed at positions where the word lines and the bit lines intersect. The memory cell stores binary data. The read circuit is connected to the M bit lines. The read circuit is able to detect levels of a multi-ary signal.
US09858992B2
A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.
US09858979B1
Methods, systems, and apparatuses related to a reprogrammable non-volatile latch are described. A latch may include ferroelectric cells, ferroelectric capacitors, a sense component, and other circuitry and components related to ferroelectric memory technology. The ferroelectric latch may be independent from (or exclusive of) a main ferroelectric memory array. The ferroelectric latch may be positioned anywhere in the memory device. In some instances, a ferroelectric latch may be positioned and configured to be dedicated to single piece of circuitry in the memory device.
US09858974B1
According to embodiments, a magnetic memory includes a structure including a first magnetic layer and a conductive layer, a second magnetic layer, a first electrode electrically 5 connected to a first portion of the structure, a second electrode provided between the first magnetic layer and the second, magnetic layer, a third magnetic layer provided insulatingly from a third portion of the structure, a third electrode electrically connected to a second portion of the 10 structure and a sixth magnetic layer provided between the first electrode and the second electrode is provided. In addition, the magnetic memory includes a first semiconductor layer having a first conductivity type electrically connected to the first electrode, a second semiconductor layer having the first conductivity type electrically connected to the third magnetic layer, and a third semiconductor layer having a second conductivity type electrically connected to the first semiconductor layer and the second semiconductor layer.
US09858973B2
According to one embodiment, a variable change memory includes a bit line, a word line, a memory cell array, a resonance line, a clock generator, and a write driver. The bit line extends in a first direction. The word line extends in a second direction. The memory cell array includes blocks. The each block includes memory cells including a transistor and a variable resistive element. The resonance line connects to a bit line. The clock generator is arranged in the memory cell array and applies a voltage to the resonance line. The write driver supplies a write current to the bit line. The voltage oscillates at the predetermined period and the write current are supplied to the bit line.
US09858970B2
A power supply circuit includes a first transistor and a second transistor electrically coupled between a power supply terminal and an output terminal. When a first current path, in which output terminal through the first transistor, is formed, a voltage level of the output terminal may be controlled to be greater than or equal to a predetermined level. When a second current path, in which a current flows from the power supply terminal to the output terminal through the second transistor, is formed, the voltage level of the output terminal may be controlled to be less than or equal to the predetermined level.
US09858969B2
A video recording system including: a camera sensor and a controller configured to: continuously store video in a temporary file storage arrangement from the camera sensor, display a user interface including displaying the video and a record button, upon receiving an activation of the record button at a first time, recording the first time as a start location, updating the user interface to include a stop recording button, upon receiving an activation of the stop recording button, at a second time, marking the second time as a stop location, display a user interface including one or more selectable start time points that precede the first time, receive a selection of a start time point of the start time points, generate a video file from a subset of the temporary file storage arrangement, the video file beginning at a video frame associated with the start time point.
US09858968B2
A mobile terminal, including a touchscreen and a controller configured to display a playing image of a first video as a main image in a first region of the touch screen, display a video list in a second region of the touchscreen different than the first region while the playing image of the first video is displayed in the first region, the video list including a first thumbnail image representing the first video and a second thumbnail image representing a second video, display a playing image of the second video in a first size as a preview image in the second region while the playing image of the first video is displayed in the first region, such that the playing image of the first video in the first region and the playing image of the second video in the second region are simultaneously displayed, in response to a first proximity touch input to the second thumbnail image, and display the playing image of the second video in a second size larger than the first size, in response to a first contact touch input to the second thumbnail image. In addition, the preview image of the second video is larger than the second thumbnail image.
US09858967B1
Video content can be analyzed to identify particular sections of the video content. Speech to text or similar techniques can be used to obtain a transcription of the video content. The transcription can be indexed (e.g., timestamped) to the video content. Information describing how users are interacting with or consuming the video content (e.g., social media information, viewing history data, etc.) can be collected and used to identify the particular sections. Once the particular sections have been identified, other services can be provided. For example, custom trailers and summaries of the video content can be generated based on the identified sections. Additionally, the video content can be augmented to include additional information relevant to the particular sections, such as production information, actor information, or other information. The additional information can be added so as not to interfere with the important sections.
US09858955B1
An apparatus includes a microactuator controller configured to generate a microactuator control signal, a feedforward microactuator compensator configured to generate a microactuator compensation signal, and a microactuator model filter configured to filter a modified microactuator control signal. The microactuator compensation signal is configured to be injected into the microactuator control signal to generate the modified microactuator control signal. The microactuator model filter generates a filtered modified microactuator control signal and injects the filtered modified microactuator control signal into a position error signal to generate a modified position error signal.
US09858945B2
The present document relates to audio source coding systems which make use of a harmonic transposition method for high frequency reconstruction (HFR), as well as to digital effect processors, e.g. exciters, where generation of harmonic distortion add brightness to the processed signal, and to time stretchers where a signal duration is prolonged with maintained spectral content. A system and method configured to generate a time stretched and/or frequency transposed signal from an input signal is described. The system comprises an analysis filterbank configured to provide an analysis subband signal from the input signal; wherein the analysis subband signal comprises a plurality of complex valued analysis samples, each having a phase and a magnitude. Furthermore, the system comprises a subband processing unit configured to determine a synthesis subband signal from the analysis subband signal using a subband transposition factor Q and a subband stretch factor S. The subband processing unit performs a block based nonlinear processing wherein the magnitude of samples of the synthesis subband signal are determined from the magnitude of corresponding samples of the analysis subband signal and a predetermined sample of the analysis subband signal. In addition, the system comprises a synthesis filterbank configured to generate the time stretched and/or frequency transposed signal from the synthesis subband signal.
US09858940B2
In some embodiments, a pitch filter for filtering a preliminary audio signal generated from an audio bitstream is disclosed. The pitch filter has an operating mode selected from one of either: (i) an active mode where the preliminary audio signal is filtered using filtering information to obtain a filtered audio signal, and (ii) an inactive mode where the pitch filter is disabled. The preliminary audio signal is generated in an audio encoder or audio decoder having a coding mode selected from at least two distinct coding modes, and the pitch filter is capable of being selectively operated in either the active mode or the inactive mode while operating in the coding mode based on control information.
US09858939B2
Method and decoder for processing of audio signals. The method and decoder relate to deriving a processed vector {circumflex over (d)} by applying a post-filter directly on a vector d comprising quantized MDCT domain coefficients of a time segment of an audio signal. The post-filter is configured to have a transfer function H which is a compressed version of the envelope of the vector d. A signal waveform is reconstructed by performing an inverse MDCT transform on the processed vector {circumflex over (d)}.
US09858937B2
A method for transmitting sound waves using a time-varying frequency-based symbol includes the steps of: storing waveform data in a digital form; converting the waveform data in the digital form into an analog signal; and outputting the analog signal as sound waves through a speaker. Herein, the waveform data in the digital form includes a symbol the frequency of which changes with time within a sound wave band.
US09858932B2
Embodiments are directed to a method of representing spatial rendering metadata for processing in an object-based audio system that allows for lossless interpolation and/or re-sampling of the metadata. The method comprises time stamping the metadata to create metadata instances, and encoding an interpolation duration to with each metadata instance that specifies the time to reach a desired rendering state for the respective metadata instance. The re-sampling of metadata is useful for re-clocking metadata to an audio coder and for the editing audio content.
US09858929B2
A computer-implemented system and method for transcription error reduction is provided. A transcribed value is assigned to each utterance obtained from a user during a call and a confidence score is assigned to each transcribed value. An accuracy threshold is applied to the confidence scores and the transcribed values that satisfy the accuracy threshold are incorporated in a message. A grouping is generated for at least one of the utterances associated with one such transcribed value that fails to satisfy the accuracy threshold. The grouping includes the at least one utterance and related utterances from other calls. Further transcribed values for at least a portion of the utterances in the grouping are received from human transcribers. The remaining utterances in the grouping are provided to the human transcribers when the further transcribed values differ. The further transcribed value for the at least one utterance is incorporated in the message.
US09858926B2
A control device includes: a storage that stores a dialog model in which a question to a user, a reply candidate to the question from the user and a control content of each electronic device are associated with an input query from the user; an acquirer that acquires environmental data in a surrounding of the user; a calculator that, based on the environmental data, calculates environment predicted data to predict environment in the surrounding of the user after elapse of a predetermined period of time in cases where each control content corresponding to the input query is executed; and a question selector that selects a question corresponding to the control content that maximizes data indicative of a degree of comfort of the surrounding environment of the user in cases where each control is executed based on the environment predicted data.
US09858922B2
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for caching speech recognition scores. In some implementations, one or more values comprising data about an utterance are received. An index value is determined for the one or more values. An acoustic model score for the one or more received values is selected, from a cache of acoustic model scores that were computed before receiving the one or more values, based on the index value. A transcription for the utterance is determined using the selected acoustic model score.
US09858921B2
The subject matter of this specification can be embodied in, among other things, a method that includes receiving geographical information derived from a non-verbal user action associated with a first computing device. The non-verbal user action implies an interest of a user in a geographic location. The method also includes identifying a grammar associated with the geographic location using the derived geographical information and outputting a grammar indicator for use in selecting the identified grammar for voice recognition processing of vocal input from the user.
US09858916B2
A method comprising acquiring an analog first sound signal, performing analog-to-digital conversion on the first sound signal to generate a digital second sound signal, performing reverberation processing, at a system bottom layer, on the second sound signal to generate a digital third sound signal, performing digital sound mixing processing on the third sound signal and a background sound signal sent from an application layer to generate a digital fourth sound signal, performing digital-to-analog conversion on the fourth sound signal to generate an analog fifth sound signal, performing analog sound mixing processing on the first sound signal and the fifth sound signal to generate an analog sixth sound signal, and playing the sixth sound signal.
US09858911B2
The present disclosure provides a transducer support, ultrasound probe, and ultrasound imaging apparatus. The ultrasound transducer support includes a first layer having first areas in which heat transfer materials are arranged and second areas in which sound absorbent materials are arranged, the first and second areas being arranged alternately; and a second layer having third areas located below the first areas in which sound absorbent materials are arranged and fourth areas located below the second areas in which heat transfer materials are arranged.
US09858891B2
There is a display control apparatus including a dummy pixel region provided in a region different from a display region in which various images are displayed, and a temperature detector detecting a temperature of the dummy pixel region.
US09858885B2
The present disclosure discloses a method and device for reducing display brightness, and belongs to the technical field of display. Aspects of the disclosure provide a method for reducing display brightness. The method includes acquiring a first corresponding relationship between pixel values and voltages for reducing display brightness. The first corresponding relationship is determined based on a second corresponding relationship between pixel values and voltages and a ratio for brightness reduction. Further, the method includes determining a voltage corresponding to a pixel value of a pixel to be displayed based on the first corresponding relationship and at a scanning moment corresponding to the pixel, outputting the determined voltage to a data line corresponding to the pixel in a liquid crystal display screen.
US09858884B2
Disclosed is a display driver including an input pad configured to receive a supply voltage, a wiring line connected to the input pad, a digital-to-analog converter configured to output analog signals based on digital-to-analog conversion results of data, a plurality of output buffer units configured to buffer the analog signals, and a plurality of bias controllers connected to different positions of the wiring line. Each of the bias controllers independently controls a bias voltage of a corresponding one of the output buffer units based on the supply voltage supplied through the wiring line.
US09858867B2
A method for controlling a scale factor includes generating a load value corresponding to accumulated input data, providing a target scale factor corresponding to the load value, and providing a scale factor based on the target scale factor, a limit scale factor, and a moving step. The limit scale factor and the moving step are determined based on power consumption of a display panel.
US09858866B2
An organic light-emitting display device includes: an organic light-emitting panel comprising a plurality of pixel regions, each pixel region comprising a scan line and a data line crossing each other, each pixel region further comprising an organic light-emission element and a drive transistor configured to drive the organic light emission element; and a circuit configured to sense a threshold voltage of the drive transistor in a sensing interval and control a light emission of the organic light emission element within the pixel region in a display interval.
US09858858B2
A unit pixel driver circuit includes a capacitor configured to store a voltage corresponding to a desired pixel brightness and a control block. The control block may include a first, second third and fourth transistors, all of which are connected together, both in parallel and in series. The control block controls, based on the voltage stored in the capacitor, the amount of current flowing through a pixel LED. The first transistor, second transistor, third transistor and fourth transistor all share a common gate geometry size.
US09858855B2
A wearable display device comprises: a set of position sensors, wherein the position sensors provide positioning data that describe a physical three-dimensional orientation of the wearable display device in real time; an exterior display surface that comprises a continuous display with a dynamically adjusted display region; and a video display controller, wherein the video display controller displays a video content on the region directed to the user's eyes on the dynamically adjusted display region based on the physical three-dimensional orientation of the wearable display device.
US09858842B2
A display device is provided. A display device comprising, a gate voltage generator outputting a gate-on voltage and a gate-off voltage, a clock generator receiving the gate-on voltage and the gate-off voltage and outputting a clock signal, a gate driver receiving the clock signal and outputting a gate signal, the gate driver including a plurality of stages which are connected to a plurality of gate lines respectively, and a pixel unit comprising a plurality of pixels which are turned on or turned off by the gate signal to display an image, wherein the gate voltage generator comprises, a direct current (DC) converter connected to a sub-gate node and receiving a sub-gate signal which is one of outputs of the plurality of stages gate driver and outputting a compensation voltage using the received sub-gate signal.
US09858835B2
The inventive technology relates to an improved display support system that may be used to support elevated displays, and other promotional/marketing materials. The invention may be used to support, for example, helium-free balloons and/or other displays to one or more display fittings. Such display fittings may further be secured to an adjustable support such that an operator may position one or more fittings in a desired position, such as from a ceiling or other elevated surface. Additional embodiments may include an improved dual display support system that may support a plurality of support adapters each having one or more fitting supports coupled with fitting displays to more efficiently place, support, and/or retrieve elevated displays, and other promotional/marketing materials having multiple anchor positions.
US09858833B2
A real-time virtual reality welding system including a programmable processor-based subsystem, a spatial tracker operatively connected to the programmable processor-based subsystem, at least one mock welding tool capable of being spatially tracked by the spatial tracker, and at least one display device operatively connected to the programmable processor-based subsystem. The system is capable of simulating, in virtual reality space, a weld puddle having real-time molten metal fluidity and heat dissipation characteristics. The system is further capable of importing data into the virtual reality welding system and analyzing the data to characterize a student welder's progress and to provide training.
US09858828B1
Embodiments can provide dynamic assessment by an expert system software (ESS) module. The ESS module may determine a minimum set of diagnostic questions to identify a student's strengths and/or weaknesses for a given subject matter. Each diagnostic question may be a unique question variant generated from a dynamic question template. The ESS module may automatically and dynamically build a personal lesson plan that includes lessons on topics of the subject matter that the student has not mastered. The ESS module may dynamically modify the personal lesson plan to change a lesson and/or add lesson(s) considered by the ESS module as necessary for the student to master the subject matter. Given the ESS module's knowledge on various components of a question such as equation(s) used to produce a correct answer to the question, the ESS module may generate image(s), customized hint(s), customized explanation(s), and/or examine student solutions in step-by-step fashion.
US09858810B2
An arrangement for controlling and/or monitoring at least one subsea device may include: a first level node communicatively, in particular electrically and/or fiberoptically connectable to an equipment above a sea surface of a sea; at least one second level node communicatively, e.g., electrically and/or fiberoptically connected to the first level node and electrically connectable to the at least one subsea device, wherein the first level node and the at least one second level node are arrangeable at a sea bottom of the sea. A corresponding method is also disclosed.
US09858808B2
A method for automatically transmitting an activation signal from a trainable transceiver to a remote electronic system, includes receiving, at a control circuit of the trainable transceiver, image data from an image data source; determining, using the control circuit, if the received image data matches one or more reference images stored in memory and associated with the remote electronic system; and determining, in response to a match between the received image data and the one or more reference images, if the trainable transceiver is approaching the remote electronic system. The method includes, in response to determining that the trainable transceiver is approaching the remote electronic system, formatting an activation signal to control the remote electronic system and transmitting, using a transceiver circuit, the activation signal formatted to control the remote electronic system.
US09858796B2
A mountable wall receptacle including one or more current sensors and power-line communications circuitry is described herein. In one exemplary, non-limiting embodiment, the mountable wall receptacle includes power-line communications circuitry, one or more current sensors, a power source, and one or more internal contacts. The wall receptacle is capable of monitoring and recording, using the current sensor(s), an amount of current or energy provided to an accessory device plugged into one or more outlets in communication with the one or more internal contacts. A user device is able to obtain the recorded amount of current or energy from various access points within a residence using one or more power lines located at the residence. The power lines enable the user device to communicate with the wall receptacle using the power-line communications circuitry therein.
US09858792B2
A smart pool maintenance monitor and alert system configured to communicate with an internet-connected device is described. The system employs a floating buoy for use within the water of a swimming pool or hot tub, and a gateway. The buoy is equipped with a variety of environmental sensors configured to accurately and expediently measure water temperature, pH, salinity, water level, air temperature, UV index, the ORP index of the water, and other environmental data. The data is conveyed via a wireless radio to the gateway, which interprets the data, stores the data in cloud storage, and relays it to a user's mobile device where it will be displayed by the applications downloaded to the respective user devices (smartphones, tablets, laptops and PCs, as well TV Set Top Boxes and wearable devices). The gateway is configured to convey alerts to the user when measurements are not consistent with those of a safe and hygienic pool.
US09858789B2
The present disclosure is directed to systems and methods for security and/or automation systems. The methods may include detecting an event in a home associated with a first occupant of the home, and identifying a presence of a second occupant in the home. In any embodiment, the second occupant may be different from the first occupant. The method may further include providing an alert to the second occupant of the home based at least in part on the detected event and the identifying.
US09858788B2
A method for security and/or automation systems is described. In one embodiment, the method may include receiving occupancy data, identifying characteristics of the occupancy data, determining an occupant's location relative to the premises at a predetermined time, and generating a notification based at least in part on the determining.
US09858787B2
A portable device is equipped with a signaling circuit that responds to a searching signal (e.g., hand clap, light flash, RF signal, infrared light) generated to locate the portable device when it is misplaced or lost. The device generates a location signal to enable the user to find the device. The location signal may be an audible, light, vibration, or other signal that calls attention to the device to enable the user to find it. The device may also sense events which cause it to disable the sensor, render it less sensitive, or suppress the generation of the location signal. The sensed event is any event, e.g., heat, motion, which indicates that the device is not, in fact, lost.
US09858784B2
A communication device comprises a processing circuit having at least two modes, a sleep mode and an awake mode, a wireless communications circuit that can wirelessly send a message as to whether an alarm has been triggered, and a passive sensor, powered by audio signals impinging on the passive sensor, that provides at least an approximation of an audio signal to the processing circuit so as to cause the processing circuit to switch between the at least two modes. The communication device can be housed in a housing sized to fit into a battery compartment.
US09858776B1
Tamper-respondent assemblies and methods of fabrication are provided which include at least one tamper-respondent sensor and a detector. The at least one tamper-respondent sensor includes conductive lines which form, at least in part, at least one tamper-detect network of the tamper-respondent sensor(s). The detector monitors the tamper-respondent sensor(s) by applying an electrical signal to the conductive lines of the at least one tamper-respondent sensor to monitor for a non-linear conductivity change indicative of a tamper event at the tamper-respondent sensor(s). For instance, the detector may monitor a second harmonic of the electrical signal applied to the conductive lines for the non-linear conductivity change indicative of the tamper event, such as an attempted shunt of one or more conductive lines of the tamper-respondent sensor(s).
US09858770B2
A doorbell switch including a projector is described. The doorbell switch can be configured to provide a first or automated display state of the projector based on one or more rules or predefined conditions defined at a client device, state conditions of a security system, or another backend the computing system, as well as various time of day, sensor, and other conditions. The automated display state can change over time in response to changes in the operation and/or status of various systems. Additionally, the doorbell switch can be configured to provide a second or actuated display state in response to the actuation of the doorbell switch.
US09858758B2
An interleaved wagering system is disclosed. The system includes an interactive controller constructed to communicate application telemetry associated with an interactive application provided by the interactive controller. The system also includes a wager controller constructed to communicate a wager result associated with a received wager request. The system also includes the application controller operatively connected to the interactive controller and the wager controller, and constructed to: receive application telemetry; upon receiving application telemetry, determine whether to trigger a supplementary mode; when triggering the supplementary mode is determined, communicate a notification to provide a supplementary mode session. The interactive controller is further constructed to: provide the supplementary mode session upon receiving the supplementary mode notification; communicate results of the supplementary mode session. The application controller is further constructed to: receive the results of the supplementary mode session; and when the received results are successful, communicate a request for benefits.
US09858757B2
A method and device for conducting a wagering game includes receiving an ante wager. A player hand of game pieces is dealt and a final player hand is formed by selecting the game pieces with matching rank indicia from the player hand. The final player hand is evaluated by comparing the final player hand to a standard, such as a pay table, a final dealer hand, and/or final player hands of other players. Payouts are issued if the final player hand is a winning hand based on the evaluation. Optionally, side wagers may be offered on the constitution of the final player hand.
US09858753B2
Techniques for reducing electromagnetic (EM) emission in a wager-based gaming machine. A gaming machine includes one or more processors configured to generate a bus clock signal having a fundamental frequency and fundamental spectral components at harmonics of the fundamental frequency. The fundamental spectral components each have a fundamental amplitude. A signal processor is configured to generate a spread spectrum clock signal having a nominal frequency substantially equivalent to the fundamental frequency of the bus clock signal as well as nominal spectral components at harmonics of the nominal frequency. However, the nominal spectral components each have a nominal amplitude less than the fundamental amplitude of a fundamental spectral component at the same harmonic. A bus connects the signal processor with one or more elements and carries the spread spectrum clock signal to the one or more elements, thereby reducing EM emissions from the bus.
US09858752B2
A side wagering system for table games includes a table controller, a dealer interface and at least one player interface, the at least one player interface including a first wager area and at least one second wager area, which permit a player to place first, second or one or more third supplemental wagers for the opportunity to win corresponding first, second or one or more third awards, such as a first, a second or a third progressive jackpot. The table controllers or multiple tables may be linked to a common award server.
US09858749B2
A method for allowing a player to play a slot game with a gaming device is described herein. The method includes randomly generating an outcome of the game, wherein the outcome includes a first outcome and a second outcome. The method includes spinning and stopping the plurality of reels to display the first outcome, detecting an appearance of a symbol selection area in the first outcome, and responsively selecting at least one symbol for display in the symbol selection area. The method also includes displaying the second outcome including the first outcome and the selected at least one symbol being displayed in the symbol selection area and providing an award to the player as a function of the second outcome.
US09858743B2
A medium housing device includes: a frame including an internal space; a partitioning plate that partitions the internal space so as to intersect with a specific collection direction, and that forms a collection space in which the medium is collected along the collection direction; a partitioning plate moving section that moves the partitioning plate along the collection direction; a side guide that is attached inside the frame and that determines the size of the collection space in an intersecting direction intersecting with the collection direction; a positioning portion that positions an end portion of the side guide at one attachment position selected from a plurality of attachment positions; and a retention switching portion that switches between a retained state in which the end portion of the side guide is positioned, and a retention-released state in which the end portion of the side guide is not positioned.
US09858740B2
It is presented an access control communication device comprising: a short distance radio communication module; a cellular radio communication module; and a controller arranged to communicate access rights associated with a key device, using the cellular radio communication module, with an access control device over a cellular communication network, the communicating comprising sending a request for access management data associated with the lock device, and receiving access management data associated with the lock device; and the controller further being arranged to transmit the access management data to the key device for transfer to the lock device, the communicating and transmitting being arranged to be performed upon the access control device being in communication with the key device using the short distance radio communication module. A corresponding method, computer program and computer program product area also presented.
US09858731B2
A graphical user interface is provided that can be used on a diagnostic tool. The graphical user interface allows a technician to operate various functions of the diagnostic tool including searching for additional information on the Internet, receiving weather information that is relevant to certain diagnostic tests, and displaying in certain formats the retrieved vehicle data and when certain vehicles were last scanned or diagnosed.
US09858730B2
In a method of determining a remaining capacity for use of a vehicle part of a motor vehicle, a state of wear of the vehicle part is determined, a remaining distance that can be covered before the vehicle part becomes completely worn is calculated as a function of a type of the vehicle part and the state of wear of the vehicle part, and a remaining service life before the vehicle part must be changed is calculated as a function of an average distance covered by the motor vehicle annually and the remaining distance that can be covered before the vehicle part becomes completely worn.
US09858729B2
A pipette check station for checking the calibration or service status of a pipette includes an RFID reader, a user interface with a display and buttons, and a digital interface to connect the check station to additional equipment; the check station optionally further includes provisions to hold pipettes for storage and to charge electronic pipettes held thereupon.
US09858717B2
Disclosed are a system and method for creating multi-angle views of an object-of-interest from images stored in a dataset. A user specifies the location of an object-of-interest. As the user virtually navigates through the locality represented by the image dataset, his current virtual position is determined. Using the user's virtual position and the location of the object-of-interest, images in the image dataset are selected and interpolated or stitched together, if necessary, to present to the user a view from his current virtual position looking toward the object-of-interest. The object-of-interest remains in the view no matter where the user virtually travels. From the same image dataset, another user can select a different object-of-interest and virtually navigate in a similar manner, with his own object-of-interest always in view. The object-of-interest also can be “virtual,” added by computer-animation techniques to the image dataset. For some image datasets, the user can virtually navigate through time as well as through space.
US09858709B2
An apparatus and method for processing a primitive in a three-dimensional (3D) graphics rendering system is provided. The primitive processing apparatus may discard a primitive or store the primitive in a memory, depending on whether a sampling point overlapping the primitive is present among sampling points in a pixel area.
US09858706B2
Systems, methods, and non-transitory computer-readable media can obtain a spherical media content item that captures at least one scene from a plurality of different positions. A three-dimensional shape having a plurality of faces is determined, each face being associated with a respective set of original boundaries. A respective set of expanded boundaries for one or more of the plurality of faces is determined. Respective portions of the spherical media content item are mapped to each of the one or more faces, wherein a first portion of the spherical media content item is mapped to a first face having a set of expanded boundaries.
US09858704B2
A computation for a parent node may be reused in a child node in a reduced precision bounding volume hierarchy ray traversal for graphics processing.
US09858695B2
A system and method for improving the readability of content wherein content is organized into segments which are each displayed on a respective row on the display device. Each of the segments are made up of characters such as letters and punctuation. The text in a particular row, the reading row, on the display device is displayed differently than the text in the other rows. Each row is consecutively displayed in the reading row until the user has seen each segment of the content presented in the reading row. User are able to configure the display of the reading row text and text in other rows independently.
US09858689B1
A computer-implemented method of performing image reconstruction with sequential cycle-spinning includes a computer system acquiring an input signal comprising k-space data using a magnetic resonance imaging (MRI) device and initializing an estimate of a sparse signal associated with the input signal. The computer system selects one or more orthogonal wavelet transforms corresponding to a wavelet family and performs an iterative reconstruction process to update the estimate of the sparse signal over a plurality of iterations. During each iteration, one or more orthogonal wavelet transforms are applied to the estimate of the sparse signal to yield one or more orthogonal domain signals, the estimate of the sparse signal is updated by applying a non-convex shrinkage function to the one or more orthogonal domain signals, and a shift to the orthogonal wavelet transforms. Following the iterative reconstruction process, the computer system generates an image based on the estimate of the sparse signal.
US09858687B2
Systems, methods and computer-readable storage mediums relate to generating an image that includes functional, anatomical, and physiological images. The generated image may be an integrated image based on the functional image on which the anatomical and physiological images are mapped. The generated image may indicate more than one location of optimal lead placement. The generated image may be useful in pre-planning cardiac intervention procedures.
US09858685B2
A system and method determine color of skin of a subject and produce a customized cosmetic based at least in part on the determined color of skin. A region of skin is covered with a chamber having an open area facing the skin. The skin is illuminated with light caused to enter the chamber. The light is caused to be dispersed within the chamber. A camera is used to record an image of a portion of the dispersed light in the chamber and the recorded image is processed to characterize the color of the skin. The recorded image includes a plurality of colors which are mapped to the closest color recipe. The color recipe is used to calculate actuator displacements for a portioning machine that includes a cartridge having cosmetic additives that produce the customized cosmetic.
US09858684B2
An image processing apparatus and method for calibrating a depth of a depth sensor. The image processing method may include obtaining a depth image of a target object captured by a depth sensor and a color image of the target object captured by a color camera; and calibrating a depth of the depth sensor by calibrating a geometrical relation between a projector and a depth camera, which are included in the depth sensor, based the obtained depth and color images and calculating a correct feature point on an image plane of the depth camera that corresponds to a feature point of an image plane of the projector.
US09858678B2
A system and method for human motion recognition are provided. The system includes a video sequence decomposer, a feature extractor, and a motion recognition module. The video sequence decomposer decomposes a video sequence into a plurality of atomic actions. The feature extractor extracts features from each of the plurality of atomic actions, the features including at least a motion feature and a shape feature. And the motion recognition module performs motion recognition for each of the plurality of atomic actions in response to the features.
US09858672B2
A depth camera assembly (DCA) determines distances between the DCA and objects in a local area within a field of view of the DCA. The DCA includes an illumination source that projects a known spatial pattern modulated with a temporal carrier signal into the local area. An imaging device capture the modulated pattern projected into the local area. The imaging device includes a detector that comprises different pixel groups that are each activated to captured light at different times. Hence, different pixel groups capture different phases of the temporally modulated pattern from the local area. The DCA determines times for light from the illumination source to be reflected and captured by the imaging device from the phases captured by the different pixel groups and also determines distances between the DCA and objects in the local area based on deformation of the spatial pattern captured by the imaging device.
US09858666B2
A medical skin examination device configured to diagnose a skin lesion includes: a first storage unit configured to store an original first skin image related to a dermoscopy structure imaged via a dermoscope; an image conversion unit configured to apply High Dynamic Range (HDR) conversion processing to the first skin image and obtain a second skin image in which the dermoscopy structure is made clear and salient; a second storage unit configured to store the second skin image; and a display control unit configured execute control so as to display at least one of the first skin image and the second skin image.
US09858664B2
Automated islet measurement systems (AIMS) in combination with tissue volume analysis (TVA) software effectively gauges volumetric and size-based data to generate heretofore unavailable information regarding, for example, populations of islet cells, stem cells and related desiderata.
US09858655B2
Embodiments of the present invention relate to method and apparatus for video anti-shaking. There is disclosed a method for use in a video anti-shaking, especially for real-time digital image stabilization, the method comprises: dividing at least one part of a current frame of a video into a plurality of regions (S301); performing a progressive local motion detection for each of the plurality of regions to determine a local motion vector for the region (S302, S303, S304); and determining a global motion vector for the current frame based on the local motion vectors for the plurality of regions (S305). There is also described a corresponding apparatus and user equipment. With embodiments of the present invention, the video anti-shaking processing can be done without any additional hardware. Moreover, embodiments of the present invention may quickly and effectively determine a motion vector and corresponding compensation.
US09858653B2
For deblurring an image, a method records both short-exposed pixels at a higher frame rate for a short-exposure region and normal-exposed pixels at a normal frame rate for full resolution. In addition, the method deblurs a normal-exposed image as a function of the short-exposed pixels and the normal-exposed pixels.
US09858651B2
The invention relates to an electronic device for performing imaging, including a camera for creating image data (ID) from an imaging target (IT), the imaging target (IT) including at least one primary image object (I1) and at least one secondary image object (I2), an image-processing chain arranged in connection with the camera, for processing the image data created from the imaging target, and a focussing unit for focussing the camera on at least the primary image object. In addition, a blurring unit is arranged in the image-processing chain, to blur at least some of the said secondary image objects in the image data, and arranged to use the information produced by the focussing unit.
US09858647B2
In one embodiment, a computing device identifies a portion of a display object to pre-generate. The device may monitor a thread to identify the next upcoming window of idle time (i.e., the next opportunity when the thread will be idle for a minimum period of time). The device may add one or more selected pre-generation tasks to a message queue for execution by the thread during the window. The device may execute the one or more selected pre-generation tasks in the message queue by pre-generating at least one selected element of a display object with content for a portion of the content layout, and then return the display object.
US09858642B2
Techniques herein are for generating geometric models. A method involves receiving a raw data set. Generation parameters include an abstraction function, a raw data set, a plurality of size pairs, and a quality interval. Each size pair comprises a view size and a portion size. The view size comprises an amount of display area. The portion size comprises an amount of raw data. For each size pair, associate a set of grid square sizes with the size pair. Each grid square size comprises a multiple of natural units. The quality interval contains a multiplicative product of the grid square size times a ratio of the view size to the portion size. Generate a set of geometric models based on the raw data set, the plurality of size pairs, the abstraction function, and the set of grid square sizes associated with the plurality of size pairs.
US09858640B1
A method for merging 3D point clouds from sparsely distributed viewpoints includes collecting a plurality of 3D point cloud data sets using a 3D sensor, each 3D point cloud data set in a local reference frame of a viewpoint of the 3D sensor, downsampling the 3D point cloud data sets, registering the downsampled 3D point cloud data sets to a global reference frame using an initial transform Tv for rotating and translating each downsampled 3D point cloud data set from the local reference frame to the global reference frame, deriving estimated transforms Tv until the last derived transform Tv converges to a stable transform Tv, registering the plurality of 3D point cloud data sets to the global reference frame using the stable transform Tv, and deriving second estimated transforms Tv until the last derived transform Tv converges to a second stable transform Tv.
US09858632B1
Systems and methods for automated check-in of controlled-environment facility residents, such as correctional facility inmates, employs at least one biometric capture device or mechanism disposed within a controlled-environment area configured to capture biometrics of residents of the controlled-environment facility within the controlled-environment area. A controlled-environment facility administration and management system, or the like, is configured to enroll key biometric identification biometric features of residents of the controlled-environment facility and compare captured biometrics of the residents to enrolled key biometric features of residents of the controlled-environment facility to identify the resident. Whereupon, the controlled-environment facility administration and management system, or the like, logs the presence of an identified resident as in the controlled-environment area at a time the biometrics of the identified resident were captured.
US09858625B2
The present disclosure provides for leveraging knowledge of one or more skipped relationships in a social network. In one example, the knowledge of the one or more skipped relationships may be utilized to change an action that would otherwise have been taken by the social network (that is, to change an action that would otherwise have been taken by the computer system maintaining the social network).
US09858622B1
A system and method to facilitate providing vehicle insurance services includes correlating vehicle information with a specialty vehicle data identifier, storing the correlated vehicle information in a memory, and associating the correlated vehicle information with one or more discrete vehicle data identifiers, wherein in response to a search request of the memory, discrete vehicle data identifiers including vehicle information that substantially matches at least a portion of a search term are identified and compiled into an output provided in an accessible format.
US09858620B2
Various embodiments of a trading screen allow a market value indicator to go out of view without necessarily triggering a command to reposition a value axis. The value axis may be repositioned to bring the market value indicator back in view when the market value indicator satisfies a threshold condition. The threshold condition is defined such that it is possible for the market value indicator to go out of view and not trigger a command to reposition the value axis. Various embodiments automatically reposition the value axis in a way that can provide the user with more overall control of the trading screen than previous trading screens. Further, the user may gain increased confidence in using the trading display, particularly with respect to single action order entry, because there is less risk of the value changing on the display during order entry. These advantages and others will be evident to a person of ordinary skill in the art of the embodiments described herein.
US09858613B2
A server device includes a communication unit, a storage unit, and a control unit. The control unit is configured to perform determining whether or not the residual amount of recording material in a cartridge is equal to or less than a first threshold, and determining whether or not the estimated number of cartridges is equal to or less than a second threshold. In response to determining that the recording material is not more than the first threshold and the number of cartridges is not more than the second threshold, the control unit transmits to an external device via the communication unit an order instruction to deliver a cartridge to the user of the image forming apparatus.
US09858603B2
A card reader is provided with a read head with a slot and is configured to be coupled to a mobile device and has a slot for swiping a magnetic stripe of a card. The read head reads data on the magnetic stripe and produces a raw magnetic signal indicative of data stored on the magnetic stripe. A power supply is coupled to wake-up electronics and a microcontroller. An output jack is adapted to be inserted in a port of the mobile device and deliver an output jack signal to the mobile device. The wake-up electronics is powered by a microphone bias of a mobile device.
US09858602B2
A modular learning system provides billing for learning users who have engaged in a variety of learning services in the modular learning system. For example the learning user may engage in learning application purchases, performances, learning facility access, tutor access, and learning tool access. The purchase of these varieties of learning services are used to provide various billing items for each type of learning service. The learning service purchases are consolidated and offset by prepaid learning services as well as modified by any applicable taxes.
US09858600B2
A system for creating and using a universal tag to gather consumer data from a website for the purposes of targeted advertising is provided. The universal tag system has two main subsystems. The first subsystem is a configuration system that is used to define the consumer data to be collected from the website and to define taxonomy and transformation rules to be applied to the collected consumer data. The second subsystem is a runtime system that runs a universal tag client-side script, which is triggered when a consumer lands on a webpage of the website, for collecting the defined consumer data. The runtime system then applies the transformation rules to the collected data and updates a user profile corresponding to the consumer with the transformed data. As well, the runtime system applies the taxonomy rules to the collected data and categorizes the consumer for the purposes of subsequent targeted advertising.
US09858598B1
Disclosed herein are systems, computer-implemented methods, and non-transitory computer-readable media for media content management and deployment. A data store stores available timeslot information data and signage device information data. A demographic information server obtains observation demographic data; generates, based on the observation demographic data, prediction demographic data; receives a demographic request; examines the prediction demographic data; and returns locations and future timeslots that have the predicted demographics satisfying the demographic request. A deployment module obtains campaign parameters for building a campaign and including time parameters, location parameters, and demographic parameters; requests the demographic information server to obtain locations and future timeslots satisfying the demographic parameters; and examines the signage device information data and the available timeslot information data to select candidate timeslots and signage devices.
US09858595B2
According to one method, a mobile communication device determines its location and compares its location to a location associated with an automation system. If the location of the mobile communication device matches the location associated with the automation system, the mobile communication device transmits a command to the automation system. According to another method, a mobile communication device determines if it has entered wireless communication range of an automation system and determines if it has exited wireless communication range of an automation system. In response to determining if the mobile communication device has entered wireless communication range of an automation system, the mobile communication device transmits a first command from to the automation system. In response to determining if the mobile communication device has exited wireless communication range of an automation system, mobile communication device transmits a second command to the automation system.
US09858589B2
Methods, systems, and apparatus include computer programs encoded on a computer-readable storage medium for measuring lift. A method includes: receiving requests for content for which a first content item is an eligible content item; delivering the first content item along with a first pixel that identifies the delivery of the first content item to a first portion of the received requests; delivering a second, different content item along with a second pixel that identifies the non-delivery of the first content item to a second portion of the received plurality of requests rather than the first content item; evaluating searches performed by users that received the first content item as compared to users that received the second content item including using the first pixel and second pixel in evaluating search logs associated with search requests performed by users; and presenting lift data to a sponsor associated with the first content item.
US09858582B2
Systems and methods for managing inventory in an online advertising system are described herein. The inventory may comprise advertisement (“ad”) impressions. In accordance with certain implementations, the systems and methods enable advertisers to target groups of inventory (e.g., “run of” inventory groups) made available by publishers and sold at a non-premium rate, while also enabling the publishers to selectively designate certain inventory within a given inventory group as premium. Inventory so designated is automatically excluded from an inventory group to which it would normally belong both during a booking process as well as during an ad serving process.
US09858579B1
A computer implemented method for providing optimized planning is provided. Collected data is analyzed. A plan for a first period of time is created based on the collected data. For a plurality of times during the first period, data collected during the first period is analyzed. At least one tuning indicator is generated based on analyzing the data collected during the first period that indicates whether a tuning should be performed. The plan is tuned a plurality of times during the first period, wherein the tuning uses the data collected during the first period.
US09858541B2
A method for providing an energy map may include receiving an indication of status for each of a plurality of individual entities with respect to corresponding priorities defined for each respective individual entity, correlating received indications of status to respective group priorities, providing a representation of a plurality of the group priorities, and mapping an amount of energy associated with the group priorities by providing a graphical representation of a respective amount of resources associated with the group priorities based on the received indications.
US09858517B2
Embodiments of the invention relate to payment cards and methods for making payment cards. In one embodiment, a card comprises a first layer and a second layer adjacent to the first layer. The second layer comprises a plurality of particles comprising metal, and the plurality of particles comprise at least about 15 volume % of the second layer. In another embodiment, a mixture is prepared comprising polymer and a plurality of particles comprising metal. The plurality of particles comprise at least about 15 volume % of the mixture. The mixture is pressed and an outer layer is applied. The mixture and outer layer are then cut to form the card.
US09858513B2
Provided is a document file output apparatus capable of appropriately storing each document as different files depending on a difference in printing setting, even when printed materials which are to be different documents for each single sheet or every plurality of sheets are continuously read, a document file output method, and a computer readable medium storing a program for operating a computer as the document file output apparatus. The document file output apparatus each specifies the printing setting of each read printed material, for example, a layout, a difference in a size of the read printed material, presence or absence of framework printing, presence or absence of reduction printing, color/monochromatic setting, or image embedding, from the obtained image data, and outputs by dividing the document files before and after the read printed material in which the printing setting is changed.
US09858509B2
A color processing device includes a color data acquisition section and a first-relationship generation section. The color data acquisition section acquires color data of a first image output by a first image forming device on a basis of image data. The first-relationship generation section generates a first relationship that is a relationship between the image data and the acquired color data, the first relationship being generated by applying the image data and the acquired color data to at least one first relationship candidate prepared in advance in a color gamut wider than a color gamut of the color data and by performing matching on the image data and the acquired color data with the first relationship candidate.
US09858508B2
A dot recording apparatus performs multi-pass recording through which recording of dots is terminated in main scanning passes of N times (N is an integer equal to or greater than two) on a main scanning line, the multi-pass recording is performed for respective supercell regions defined as a region including pixel positions on which recording of dots is performed in each main pass, a first supercell region recorded in a first pass in the supercell regions is configured with a first concave polygon having a concave portion and a convex portion, a second supercell region recorded in a second pass in the supercell regions is configured with a second concave polygon having a concave portion and a convex portion, and shapes of the first concave polygon and the second concave polygon are inversely symmetrical shapes in the main scanning direction.
US09858498B2
Methods, systems, computer-readable media, and apparatuses for incremental object detection using a staged process and a band-pass feature extractor are presented. At each stage of the staged process, a different band of features from a plurality of bands of features in image data can be extracted using a dual-threshold local binary pattern operator, and compared with features of a target object within the band for a partial decision. The staged process exits if a rejection decision is made at any stage of the staged process. If no rejection decision is made in each stage of the staged process, the target object is detected. Features extracted at each stage may be from a different image for some applications.
US09858497B2
Techniques are provided in which a plurality of edges are detected within a digital image. An anchor point located along an edge of the plurality of edges is selected. An analysis grid associated with the anchor point is generated, the analysis grid including a plurality of cells. An anchor point normal vector comprising a normal vector of the edge at the anchor point is calculated. Edge pixel normal vectors comprising normal vectors of the edge at locations along the edge within the cells of the analysis grid are calculated. A histogram of similarity is generated for each of one or more cells of the analysis grid, each histogram of similarity being based on a similarity measure between each of the edge pixel normal vectors within a cell and the anchor point normal vector, and a descriptor is generated for the analysis grid based on the histograms of similarity.
US09858496B2
Systems, methods, and computer-readable media for providing fast and accurate object detection and classification in images are described herein. In some examples, a computing device can receive an input image. The computing device can process the image, and generate a convolutional feature map. In some configurations, the convolutional feature map can be processed through a Region Proposal Network (RPN) to generate proposals for candidate objects in the image. In various examples, the computing device can process the convolutional feature map with the proposals through a Fast Region-Based Convolutional Neural Network (FRCN) proposal classifier to determine a class of each object in the image and a confidence score associated therewith. The computing device can then provide a requestor with an output including the object classification and/or confidence score.
US09858493B2
A method for performing registration plate detection includes: performing image processing on image data of a predetermined region in an image to generate an edge image; and performing registration plate detection according to the edge image and the image data of the predetermined region to determine a location of a registration plate image within the predetermined region, for performing a post-processing corresponding to the registration plate image. The step of performing the image processing includes: performing gradient calculations on image data of the predetermined region to generate a gradient image, where the gradient image includes gradient data of the predetermined region; performing edge threshold estimation on the gradient data of the predetermined region, to update an edge threshold through a set of iterative calculations; and generating the edge image according to the edge threshold and according to selective gradient data of the predetermined region.
US09858472B2
The present disclosure provides a three-dimensional facial recognition method and system. The method includes: performing pose estimation on an input binocular vision image pair by using a three-dimensional facial reference model, to obtain a pose parameter and a virtual image pair of the three-dimensional facial reference model with respect to the binocular vision image pair; reconstructing a facial depth image of the binocular vision image pair by using the virtual image pair as prior information; detecting, according to the pose parameter, a local grid scale-invariant feature descriptor corresponding to an interest point in the facial depth image; and generating a recognition result of the binocular vision image pair according to the detected local grid scale-invariant feature descriptor and training data having attached category annotations. The present disclosure can reduce computational costs and required storage space.
US09858471B2
An identification apparatus has an extraction unit comprising: an extraction unit; an acquisition unit; and an identification unit. The extraction unit extracts, from an object region in an image, a candidate region including candidate points of a predetermined object using parallax information. The acquisition unit acquires a characteristic value based on image information in the candidate region. The identification unit that identifies whether or not the candidate region includes the predetermined object based on similarity between the characteristic value and a reference characteristic value.
US09858467B2
A fingerprint recognition method and apparatus are provided for quickly and accurately authenticating a user using a direction of a fingerprint. The fingerprint recognition method includes sensing a fingerprint input from a user; creating fingerprint data including a direction angle of the fingerprint input; and authenticating the user based on the fingerprint data.
US09858463B2
A barcode reader and an accessory are disclosed. The accessory may include an interface system and a wireless and/or wired interface for communication with a host computer such that the barcode reader may communicate with the host computer via the accessory. The interface system includes an authentication coprocessor such that the barcode reader may establish mutual authentication with the host computer using the authentication coprocessor of the interface system. The barcode reader may send a request for an accessory identifier, and the accessory may then query the authentication coprocessor for the accessory identifier and provide the accessory identifier to the barcode reader. The barcode reader may send an authentication challenge to the accessory, and the accessory may then present the authentication challenge to the authentication coprocessor to obtain an authentication response, and provide the authentication response to the barcode reader.
US09858452B2
In embodiments of the present invention improved capabilities are described for a system of information RFID tagging facilities comprising a first radio frequency (RF) tag and a second RF tag, wherein the first RF tag and the second RF tag are adapted to at least in part operate using energy received from an RF signal, wherein the first RF tag receives energy from a first RF signal from an RF device and the second RF tag is out of range of the first RF signal from the RF device, wherein the first RF tag and the second RF tag are adapted to exchange data.
US09858447B2
A laser marker enables efficient determination of an optimum condition for a printing pattern of a two-dimensional code and simplification of the evaluation operation of the printing pattern of the two-dimensional code. A printing pattern regarding a cell to be printed in each of reference cells of a two-dimensional code is generated. The two-dimensional code is printed in this cell printing pattern. The recognition rate of the two-dimensional code is calculated on the basis of the reference cells. When the recognition rate is a predetermined value or more, a present printing pattern is stored as an optimum condition (optimum printing pattern) in a database. In contrast, when the recognition rate is less than the predetermined value, the size of cells constituting the present printing pattern is changed. The two-dimensional code is printed in the changed cell printing pattern, and the recognition rate of the two-dimensional code is calculated again.
US09858443B2
A method, system and computer program product are provided for implementing block extent granularity authorization model processing in Coherent Accelerator Processor Interface (CAPI) adapters. The CAPI adapter includes an authorization table and a file system authorization function to authenticate data access for a client at an extent granularity and to prevent an application from accessing unauthorized data in the CAPI adapter. Each authorization table entry provides for the CAPI client, a CAPI client identification (ID), a CAPI server register space assigning resource ownership to the CAPI client with a CAPI set of allowed functions.
US09858438B2
An approach for managing photograph metadata anonymization is provided. The approach receives, by one or more processors, a photograph file, wherein the photograph file comprises a digital photograph and a first metadata. The approach receives, by one or more processors, a rule set for modifying the first metadata. The approach determines, by one or more processors, whether at least one rule of the rule set corresponds to a datum of the first metadata. Responsive to determining at least one rule corresponds to at least one datum of the first metadata, the approach modifies, by one or more processors, the first metadata based on the rule set to create a second metadata. The approach stores, by one or more processors, the first metadata in a database.
US09858433B2
A hierarchical tree structure is used to facilitate the communication of encrypted keys to particular users having access to the tree. All users are in communication with a root node, but the information content of the material at the root node is decipherable only by the intended users of this information. Protected data is encrypted using a variety of data-keys specific to the data. These data-keys are encrypted using a combination of node-keys that are specific to particular users or groups of users. Users having access to the node-key associated with a particular encrypted data-key are able to decipher the data associated with the data-key; users without access to the particular node-key are unable to decrypt the data-key, and thus unable to decipher the data. The hierarchical tree is preferably structured based on a similarity of access rights among users, to minimize the overhead associated with providing user-specific access rights.
US09858421B2
A method comprising may include storing, in a BIOS comprising a program of instructions executable by the processor and configured to cause the processor to initialize one or more information handling resources of an information handling system, a hardware profile of the information handling system, the hardware profile comprising identifying information of one or more information handling resources of the information handling system recorded during creation of the hardware profile. The method may also include, during a boot of the information handling system in a hardware verification mode, creating a new hardware profile comprising identifying information of the one or more information handling resources, comparing the new hardware profile to the hardware profile stored in the BIOS, and if the new hardware profile differs from the hardware profile stored in the BIOS, issuing an alert indicating potential tampering with hardware of the information handling system after creation of the profile.
US09858416B2
According to a first aspect of the present invention there is provided a method of protecting a computer system from malware, which malware attempts to prevent detection or analysis when executed in an emulated computer system. The method comprises determining if an executable file should be identified as being legitimate and, if not, executing the executable file while providing indications to the executable file that it is being executed within an emulated computer system.
US09858406B2
An authenticity accuracy, corresponding to a personal identification number, is determined. A device presents a correct image (or group of images) and an incorrect image (or group of images). Selections from a user are received until a sufficient number of correct images are selected to satisfy the authenticity accuracy. For example, a counter may be incremented when the correct image is selected, and the user may be considered to be authenticated if the counter reaches a sufficient level.
US09858396B2
Media content is delivered to a variety of mobile devices in a protected manner based on client-server architecture with a symmetric (private-key) encryption scheme. A media preparation server (MPS) encrypts media content and publishes and stores it on a content delivery server (CDS), such as a server in a content distribution network (CDN). Client devices can freely obtain the media content from the CDS and can also freely distribute the media content further. They cannot, however, play the content without first obtaining a decryption key and license. Access to decryption keys is via a centralized rights manager, providing a desired level of DRM control.
US09858392B2
The present invention relates to effective diagnosis of patients and assisting clinicians in treatment planning. In particular, invention provides a medical analysis system that enables refinement of molecular classification. The system provides a molecular profiling solution that will allow improved diagnosis, prognosis, response prediction to provide the right chemotherapy, and follow-up to monitor for cancer recurrence.
US09858388B1
A system for monitoring participants in a group includes one or more thermal image capturing devices configured to capture one or more thermal images of a plurality of participants in an event, and a processing device configured to receive the one or more thermal images and identification data for at least one of the plurality of participants. The processing device is configured to perform a method that includes identifying the at least one of the plurality of participants, calculating a heat profile of the at least one of the plurality of participants, comparing the heat profile to a reference profile, and determining whether a deviation exists between the heat profile and the reference profile. The method also includes, based on detecting the deviation, calculating a magnitude of the deviation and determining whether a health risk exists based on the magnitude of the deviation.
US09858378B2
A method of designing an integrated circuit, that includes receiving a first list corresponding to at least one circuit component in a layout, generating a condensed layout from the layout and performing an electrostatic discharge (ESD) check of the condensed layout. The condensed layout is generated by a processor. The ESD check is configured to verify compliance with one or more ESD design rules. The condensed layout includes at least one circuit component. The at least one circuit component includes an ESD circuit and an associated ESD current path.
US09858377B2
A computer-implemented method of performing physical synthesis in a chip design process using hierarchical wire-pin co-optimization, a system, and a computer program product are described. Aspects include providing an indication of candidate pins among a plurality of pins of a plurality of macros that may be moved, and providing constraints on a range of movement of one or more of the plurality of pins. Aspects also include performing macro-level physical synthesis at each of the plurality of macros based on the candidate pins and the constraints to generate pin locations and timing results.
US09858372B1
Disclosed are techniques for implementing formal verification of an electronic design. These techniques identify a target property for verification in a hierarchical electronic design that has a plurality of hierarchies and perform hierarchical synthesis on a hierarchy or a portion thereof in the plurality of hierarchies while black-boxing a remaining portion of the hierarchical electronic design. Cone of influence (COI) data that is relevant to the target property may be determined at least by extracting the cone of influence data from a hierarchically synthesized hierarchy or portion of the hierarchy or the portion thereof. At least the cone of influence data may be forwarded to a formal engine that uses the cone of influence data to verify the target property.
US09858367B1
A parameterizable integrated circuit (IC) and method for designing, refining and implementing a circuit including the parameterizable IC are described. The method begins with receiving information on candidate sensing sub-circuits, parameterizable ICs and user specified requirements for the circuit including physical properties to be sensed and target values for the circuit. Each of the parameterizable ICs include a number of parametric analog and digital circuit elements, and a scheduler to schedule resources of the IC according to measurement priorities, measurement rates and the available circuit elements. Next, each of the candidate sensor-sub-circuits is evaluated with reference to the specified requirements, and each of the candidate ICs evaluated with reference to the requirements and the sensor-sub-circuits. Generally, the method further includes communicating to a user a number of candidate circuit-designs within a predetermined percentage of the one or more target values for the circuit.
US09858363B2
Methods, systems, and computer programs, for estimating think times. One of the methods includes receiving a request to perform a test of one or more computing resources. The test of the one or more computing resources is performed by simulating an interaction of one or more simulated users with the one or more computing resources. Requests are submitted from the simulated user for execution by the one or more computing resources. Respective response times of the one or more computing resources to each of the requests are measured. An estimated think time of the simulated user is computed, wherein the estimated think time is computed based on at least one preceding response time.
US09858353B2
Input is received to store information to access content displayed within a browser as a bookmark. A bookmark properties form is generated to include fields in which environments are identified as corresponding to the bookmark. Input is received that includes a first URL corresponding to the label of a first bookmark within a first environment. The bookmark is stored by including in the properties form, a label of the bookmark, the first environment corresponding to the bookmark, and the first URL corresponding to the first environment. A second URL is received that corresponds to the label of the first bookmark, but within a second environment, and includes the second environment in the properties form as corresponding to the label of the bookmark, and includes the second URL in the properties form as corresponding to the second environment, wherein the first URL differs from the second URL.
US09858352B2
Input is received to store information to access content displayed within a browser as a bookmark. A bookmark properties form is generated to include fields in which environments are identified as corresponding to the bookmark. Input is received that includes a first URL corresponding to the label of a first bookmark within a first environment. The bookmark is stored by including in the properties form, a label of the bookmark, the first environment corresponding to the bookmark, and the first URL corresponding to the first environment. A second URL is received that corresponds to the label of the first bookmark, but within a second environment, and includes the second environment in the properties form as corresponding to the label of the bookmark, and includes the second URL in the properties form as corresponding to the second environment, wherein the first URL differs from the second URL.
US09858350B2
A centralized barcode system is described. The centralized barcode system includes a barcode generation system configured to create a customized barcode by creating a new barcode or enhancing an existing barcode.
US09858346B2
An exemplary geographic playlist system includes a plurality of mobile devices with global positioning systems that provide geographic location information of the mobile device to a geographic location playlist device. The geographic location playlist device has a database of geographic playlist information that includes at least a unique identifier for each one of a plurality of media content events and at least one associated geographic location for each of the plurality of media content events. The geographic location playlist device determines a current geographic location of the mobile device, compares the geographic location of the mobile device with the geographic locations residing in the database, and generates user geographic playlist information that includes the identifier of media content events that has an associated geographic location that matches with the determined geographic location of the mobile device. A geographic playlist is then presented to the user of the mobile device.
US09858342B2
A method for searching for applications respective of a connectivity mode of a user device is provided. The method includes detecting a set of applications of a plurality of applications installed in the user device that can operate in an offline mode; receiving a search query entered by a user of the user device; determining a current connectivity mode of the user device, wherein the current connectivity mode is any one of an offline mode and an online mode; searching for at least one matching application from the set of applications, when the current connectivity mode of the user device is the offline mode; and displaying the at least one selected application on a display of the user device.
US09858336B2
Electronic natural language processing in a natural language processing (NLP) system, such as a Question-Answering (QA) system. A receives electronic text input, in question form, and determines a readability level indicator in the question. The readability level indicator includes at least a grammatical error, a slang term, and a misspelling type. The computer determines a readability level for the electronic text input based on the readability level indicator, and retrieves candidate answers based on the readability level.
US09858333B2
According to one exemplary embodiment, a method for exploring a structured data set is provided. The method may include receiving a plurality of bivariate pairs and an input bivariate pair, wherein the plurality of bivariate pairs and the input bivariate pair are based on the structured data set. The method may include constructing a graph having a plurality of nodes and a plurality of edges based on the received plurality of bivariate pairs and input bivariate pair. The method may include constructing an adjacency matrix based on the constructed graph. The method may include calculating a centrality for each node based on the constructed matrix. The method may include constructing an orthogonal list based on the plurality of bivariate pairs and the input bivariate pair. The method may include ordering the orthogonal list based on the calculated centrality of each node within the plurality of nodes.
US09858330B2
Representative implementations of devices and techniques provide a system for categorizing electronically stored information without the need for user input, direction, or guidance. In an implementation, the system determines meanings of input textual data items and groups of textual data items, identifies equivalent meanings between textual data items and between groups of textual data items, and outputs user-selected information that is categorized, indexed, and searchable.