US11323548B2
Method and system for lossless and stateless compression scheme is used with a fixed-length data such as frames. Frames having a payload of M bits length are mapped into a payload of N bits length, where N
US11323536B2
A system comprising: a plurality of mobile edge caches integrated within a corresponding plurality of mobile environments; a local network manager coupled to each edge cache device in each mobile environment to provide network connectivity to client devices; a plurality of network access devices, each network access device to provide local network access to client devices within the mobile environment, and to further perform network address translation on behalf of the client devices within the local network of the mobile environment; and regional configuration logic, responsive to an event indicating that a first mobile environment has moved from a first geographical region to a second graphical region, to modify one or more configuration settings of a first network access device in a first mobile environment and/or client devices in the first mobile environment to align content availability from the edge cache with requirements of the second geographical region.
US11323535B2
Described herein are enhancements for operating cache nodes in a content delivery network to synchronize edge dictionary configurations. In at least one implementation, a cache node of a content delivery network receives a content request from an end user device. In response to the request, the cache node identifies a modification to a key-value pair of an edge dictionary, wherein the edge dictionary comprises a reference key-value function for a Hypertext Transfer Protocol (HTTP) accelerator service. The method further provides generating a modified version of the edge dictionary based on the modification, and transferring a notification of the modification to at least one other cache node in the content delivery network.
US11323524B1
Techniques for server movement control are described. A capacity library service (CLS) can manage which hosts in a provider network can be taken in and out of production. The CLS may also control which entities may remove hosts from production and under what conditions the hosts may be removed from production. In some embodiments, the CLS can execute various workflows to manage checkout and check-in of hosts. Workflows may also be used to manage hosts while they are out of production to manage state transitions (e.g., in production, in testing, in reserve, etc.) based on current host fleet capacity and checkout rules.
US11323522B2
A client device may connect to a remote browsing server, which may browse to a Uniform Resource Identifier, render a web service or other content, and stream the content back to the client device. The client device may have a web browser through which the server may stream rendered images and which may capture various inputs, such as mouse operations, keyboard inputs, and other input. The remote browsing server may receive the inputs from the browser, then transmit the inputs to the web service through a server browser, which may render the images transmitted to the client device. The remote browsing server may be a virtual machine that may be created for a limited use, such that the virtual machine and browser may be wiped clean with each use.
US11323521B1
Methods, systems, and devices associated with an edge device are described. An edge device can include a processing resource and a memory resource having instructions executable to receive, at the processing resource, the memory resource, or both, and from a first source comprising a device in communication with the edge device, first input associated with a user of the device. The instructions can be executable to receive, from a second source, second input associated with a user of the device, determine, based on the first input and the second input, operational instructions for the device and transmit the operational instructions to the device. The instructions can be executable to update, using a machine learning model, the operational instructions responsive to receiving an indication of performance of the operational instructions by the device and responsive to third input received from the first source, the second source, or both.
US11323511B2
A network service may be supported by a software application that is executed by multiple computer servers, such as servers that are maintained as part of a server pool. To migrate to a container-based platform, the software application is containerized to create a container image. A container cluster is then created based on the container image. The container cluster includes one or more executing containers, each of which performs the functions of the software application. The container cluster is then added as a member of the server pool to receive a portion of any network requests for the network service. Computer servers of the server pool may then be removed gradually, over time, to let the container cluster gradually assume responsibility for responding to network requests.
US11323495B2
Information regarding application usage on an actor device may be provided through activity notifications and activity reports. An activity notification describing current application activity on an actor device is sent, via wireless connection, to an observer device which displays the activity notification. Activity notifications provide different granularity levels of information based on a received level selection or based on a distance (proximity) between the actor device and the observer device. An activity report representing the history of application usage on an actor device may be displayed on the actor device. For example, the activity report may be triggered to by displayed when the actor device is placed flat. The activity report provides a graphical representation of the application usage on the actor device for a predetermined time period of prior usage. The graphical representation may comprise a plurality of stripes, each stripe representing a particular application or application type.
US11323491B2
A method is described for processing a request by server of a multimedia IP network core, the request issued by a first device registered with a first multimedia IP network core and destined for a public identity allocated to at least one second device. The method includes replication of the request as a first request and at least one second request; triggering a routing of the first request within the first multimedia IP network core; and triggering a routing of the at least one second request according to at least one predetermined route destined for at least one entity for interconnection of the first multimedia IP network core with a second network core distinct from the first multimedia IP network core.
US11323490B2
An apparatus for transmitting a broadcast signal includes a processor configured to format a plurality of Internet Protocol (IP) packets to output one or more Physical Layer Pipes (PLPs). Further, the plurality of IP packets includes signaling information for listing broadcast service, a content component for a broadcast service and service signaling information, the service signaling information including format information representing a payload format of an object; and a time interleaver configured to time interleave data in a PLP based on a Time Interleaving (TI) block. In addition, the TI block including data FEC blocks, and a number of the data FEC blocks is equal to a difference between a maximum value for the TI block and a number of virtual FEC blocks; and a transmitter configured to transmit the broadcast signal including the time interleaved data. Further, the signaling information is transmitted at an IP packet level, and the service signaling information is transmitted through transport packets included in the IP packets.
US11323480B2
An authentication system handles authentication requests to apply introspection and policy enforcement. A policy server obtains a client security policy and an authenticator security policy. The policy server obtains an encrypted credential request with client metadata from a client and determines whether the client metadata satisfies the client security policy. The policy server provides the encrypted credential request to an authenticator device and obtains an encrypted credential response with authenticator metadata in response. The policy server determines whether the authenticator metadata satisfies the authenticator security policy. The policy server processes the encrypted credential response, without decrypting the encrypted credential request or the encrypted credential response, based on a determination of whether the client metadata satisfies the client security policy and the authenticator metadata satisfies the authenticator security policy.
US11323478B2
A communication device comprises a container environment with a plurality of containers each having one or more applications and each being connectable to a network slice, and a container manager configured to control communication between the applications and the network slices, wherein the container manager prohibits communication between a first application in a first container and a second application in a second container.
US11323474B1
A technique to stop lateral movement of ransomware between endpoints in a VLAN is disclosed. A security appliance is set as the default gateway for intra-LAN communication. Message traffic from compromised endpoints is detected. Attributes of ransomware may be detected in the message traffic, as well as attempts to circumvent the security appliance. Compromised devices may be quarantined.
US11323465B2
Systems and methods for implementing sequence data based temporal behavior analysis (SDTBA) to extract features for characterizing temporal behavior of network traffic are provided. The method includes extracting communication and profile data associated with one or more devices to determine sequences of data associated with the devices. The method includes generating temporal features to model anomalous network traffic. The method also includes inputting, into an anomaly detection process for anomalous network traffic, the temporal features and the sequences of data associated with the devices and formulating a list of prediction results of anomalous network traffic associated with the devices.
US11323461B2
Disclosed herein are systems and method for intercepting malicious messages for training a malware detection classifier. In an exemplary aspect, an application selection module may select, from a plurality of applications, an application for execution in an execution environment based on a priority level of the application. During the execution of the selected application, a network interception module may monitor network activity comprising information about data being sent and received over a network connected to the execution environment and storing the network activity in memory of the execution environment (e.g., in a network activity log). A message selection module may subsequently extract, from the stored network activity, an electronic message, in response to determining that the electronic message corresponds to the selected application, may storing the electronic message in a message database used for training the malware detection classifier.
US11323459B2
In some embodiments, a behavioral computer security system protects clients and networks against threats such as malicious software and intrusion. A set of client profiles is constructed according to a training corpus of events occurring on clients, wherein each client profile represents a subset of protected machines, and each client profile is indicative of a normal or baseline pattern of using the machines assigned to the client respective profile. A client profile may group together machines having a similar event statistic. Following training, events detected on a client are selectively analyzed against a client profile associated with the respective client, to detect anomalous behavior. In some embodiments, individual events are analyzed in the context of other events, using a multi-dimensional event embedding space.
US11323457B2
A network topology is provided that includes multiple data centers for building blockchain blocks. The data centers can process different subgroups of blocks, and then send updates to one another with information about new blocks. Additionally, some data centers may protect sensitive block body information, and instead may only share block headers.
US11323451B2
Devices, systems, and methods of detecting whether an electronic device or computerized device or computer, is communicating with a computerized service or a trusted server directly and without an intermediary web-proxy, or indirectly by utilizing a proxy server or web-proxy. The system searches for particular characteristics or attributes, that characterize a proxy-based communication session or channel and that do not characterize a direct non-proxy-based communication session or channel; or conversely, the system searches for particular characteristics or attributes, that characterize a direct non-proxy-based communication session or channel and that do not characterize a proxy-based communication session or channel; and based on these characteristics, determines whether or not a proxy server exists and operates.
US11323443B2
Methods and systems for performing on demand access transactions are disclosed. In one example, the method includes receiving, by a directory service computer from an authorizing computer, a file including a primary access identifiers and virtual access identifiers, the virtual access identifiers not being capable of being used at resource providers to conduct transactions. The method also includes receiving a request to provide an access token that is associated with an account, the request comprising information that identifies the account. The method further includes retrieving a virtual access identifier based on the identifying information; and requesting, by the directory service computer to a token service computer, that the access token be provisioned on the user device or an application computer associated with an application on the user device.
US11323433B2
Provided in the present invention are a digital credential management method and a device, the method comprising: a digital credential application device negotiating establishment of a secure data channel with a digital credential issuing device, and sending to the digital credential issuing device a digital credential management request message; the digital credential issuing device receiving the message, and sending to the digital credential application device a digital credential management verification request message; the digital credential application device receiving the verification request message, and sending to the digital credential issuing device a digital credential management verification response message; the digital credential issuing device receiving the digital credential management verification response message, and sending to the digital credential application device a digital credential management response message; the digital credential application device receiving the digital credential management response message, and sending to the digital credential issuing device a digital credential management confirmation message.
US11323431B2
A technique for providing access to protected resources uses personal authentication tags (PATs) and enforces a requirement that a workstation sending an authentication request be trusted by a server that receives the request. Accordingly, the server allows an authentication request to proceed only when the request is received from a workstation having a trust relationship with the server. Otherwise, the server denies the authentication request. By restricting PAT-type authentication requests to trusted workstations, risks posed by malicious users are greatly reduced.
US11323427B2
A method and apparatus for mixed-mode cloud/on-premise secure communication. The method includes commissioning an on-premise device, and connecting to web address via a client web browser using a name and a log in credential of a user; and verifying a login credential of a user at a cloud-based service and establishing communication with the client web browser if the login credential is authenticated, then permitting communication between the client web browser and the cloud based service.
US11323424B2
The techniques herein are directed generally to a “zero-knowledge” data management network. Users are able to share verifiable proof of data and/or identity information, and businesses are able to request, consume, and act on the data—all without a data storage server or those businesses ever seeing or having access to the raw sensitive information (where server-stored data is viewable only by the intended recipients, which may even be selected after storage). In one embodiment, source data is encrypted with a source encryption key (e.g., source public key), with a rekeying key being an encrypting combination of a source decryption key (e.g., source private key) and a recipient's public key. Without being able to decrypt the data, the storage server can use the rekeying key to re-encrypt the source data with the recipient's public key, to then be decrypted only by the corresponding recipient using its private key, accordingly.
US11323417B2
A network management apparatus configured to obtain multiple rules that each control communication in accordance with an address range of a packet, divide a full set of the address range of the multiple rules into multiple subsets that are mutually disjoint in accordance with inclusion relations of the address range among the multiple rules, extract, with respect to each rule of the multiple rules, one or more subsets that are included in the address range from the multiple subsets, and determine, with respect to each rule of the multiple rules, an inclusion relation of the one or more subsets between a particular rule and another rule of the multiple rules that is assigned higher priority than that of the particular rule and determine disposition for each of the multiple rules in accordance with a determination result of the inclusion relation of the one or more subsets.
US11323411B2
The present disclosure is related to the content delivery technology and discloses a method and system for scheduling an edge CDN node. The method is applicable to a CDN scheduling center under a 5G network architecture and includes: receiving a terminal request for a target domain name sent by a central layer UPF network element; assigning a target edge CDN node to a terminal according to location information of the terminal carried in the terminal request if the terminal request is an HTTPDNS request; and assigning the target edge CDN node to the terminal according to a source IP address of the terminal request if the terminal request is a conventional DNS request. By adopting the present disclosure, the CDN scheduling center may determine the location information of the terminal under the 5G network architecture, thereby accurately assigning the edge CDN node to the terminal.
US11323408B2
The present disclosure relates generally to facilitating routing of communications. More specifically, techniques are provided to dynamically route messages having certain intents between bots and user devices during communication sessions configured with multi-channel capabilities.
US11323407B2
A method and system for facilitating managing digital content captured using multiple content capturing devices is provided. Further, the method comprises receiving a content capturing context from a source user device, analyzing the content capturing context, determining a content capturing parameter based on the analyzing, generating a command based on the determining, transmitting the command to the source user device, receiving device digital content from the source user device, receiving a supplemental content identifier from the source user device, receiving target identifiers from the source user device, identifying social media servers associated with the target identifiers, identifying a supplemental content based on the supplemental content identifier, processing a digital content of the device digital content based on platform characteristics corresponding to the social media servers, embedding the supplemental content in the digital content, generating digital content based on the processing, and transmitting the digital content to the social media servers.
US11323404B2
A system and method displays lists of users or messages in segments, with some segments showing messages or users believed to be more relevant to the user than others on the list.
US11323396B2
A system and method for secure vehicle communication of a vehicle. The system comprises a communication system comprising at least one telematics module for executing one or more telematics applications, and a session module for session management of the telematics applications, wherein the session management comprises the assigning of at least one session identification, session ID, to each telematics application, wherein the session module assigns a new session ID to each telematics application after expiration of a predetermined time period.
US11323390B2
Example implementations relate to hybrid arbitration of requests for access to a shared pool of resources. An example implementation includes receiving a set of requests for access to the shared pool of resources. The requests may each be from any number of traffic classes. A traffic class may be selected according to turn-based arbitration logic. Additionally, a request from each traffic class of a subset of received requests may be selected. A request selected by the age-based arbitration logic and of the selected traffic class may be granted access to the shared pool of resources.
US11323383B2
Device, system, and method of Voice over Internet Protocol (VoIP) communications, and particularly of Real Time Protocol (RTP) communication. In order to improve quality-of-service or quality-of-experience for a group of VoIP calls that are served by a VoIP router, each VoIP transmitter implements and adds a pseudo-random waiting-period prior to transmitting each outgoing RTP packet, or otherwise re-orders or mixes or shuffles the order of channels of RTP packets that are buffered or queued for transmission. Accordingly, no particular VoIP channel suffers from repeated drops of its RTP packets at the VoIP router. Additionally, VoIP network analyzers operate to measure the overall VoIP network overuse, or the average RTP packet loss rate of multiple VoIP channels, based on measuring RTP packet loss rate of a single VoIP channel which enforces a random pre-transmission waiting-period.
US11323382B1
A network device may receive traffic to be processed by a routing component, and may determine temperatures of an ASIC and an HBM of the routing component at a first time. The network device may determine whether the temperature of the ASIC satisfies a first ASIC temperature threshold or a second ASIC temperature threshold, and may determine whether the temperature of the HBM satisfies a first HBM temperature threshold or a second HBM temperature threshold. The network device may selectively throttle processing of the traffic by a first quantity when the temperature of the ASIC satisfies the first ASIC temperature threshold or the temperature of the HBM satisfies the first HBM temperature threshold, or throttle the processing of the traffic by a second quantity when the temperature of the ASIC satisfies the second ASIC temperature threshold or the temperature of the HBM satisfies the second HBM temperature threshold.
US11323381B2
In general, this disclosure describes a network device to determine a cause of packets being dropped within a network. An example method includes generating, by a traffic monitor operating on a network device, an exception packet that includes a unique exception code that identifies a cause for a component in the network device to discard a transit packet, and a nexthop index identifying a forwarding path being taken by the transit packet experiencing the exception. The method also includes forwarding the exception packet to a collector to be processed.
US11323375B2
In order to enable prediction of communication having high quality requirements, this communication device is provided with: a determination unit that determines that a change has occurred in the communication state of communication which is performed, with a device connected to a network, by each of a first terminal and a second terminal communicating with the device; and a derivation unit that, when the change in the second terminal is determined to be being occurring in synchronization with the change in the first terminal, derives a second change time at which the change occurs in the second terminal, on the basis of a first change time at which the change occurs in the first terminal.
US11323372B2
In one embodiment, a network device includes an interface configured to receive a data packet including a header section, at least one parser to parse the data of the header section yielding a first header portion and a second header portion, a packet processing engine to fetch a first match-and-action table, match a first index having a corresponding first steering action entry in the first match-and-action table responsively to the first header portion, compute a cumulative lookup value based on the first header portion and the second header portion responsively to the first steering action entry, fetch a second match-and-action table responsively to the first steering action entry, match a second index having a corresponding second steering action entry in the second match-and-action table responsively to the cumulative lookup value, and steering the packet responsively to the second steering action entry.
US11323369B2
A network device may receive forwarding data associated with a multi-level hybrid hierarchy forwarding information base of the network device. The network device may process the forwarding data to generate a first set of transformed forwarding next hop entries. The network device may process the first set of transformed forwarding next hop entries, associated with default forwarding classes, to generate a second set of transformed forwarding next hop entries. The network device may process the first set of transformed forwarding next hop entries, associated with all classes of traffic, to generate a third set of transformed forwarding next hop entries. The network device may group the sets of transformed forwarding next hop entries, based on transformed group next hop entries, to generate a final set of transformed forwarding next hop entries. The network device may transform the final set of transformed forwarding next hop entries into a particular format.
US11323367B2
A method, apparatus and system for transferring data from an apparatus called multi-protocol gateway in a network seamlessly that operates using a particular protocol, to another device that is either in the same network or outside operating in a totally different protocol is described. Today, to accomplish this requires external units, one per technology. For example, for supporting both WiFi and WiMAX devices today, we would require a WiFi access point, a WiMAX base station and a router. We provide plug-ins that would handle multiple protocols within the same gateway, to cater to devices that operate in those protocols. The apparatus translates between various protocols in the back end making it inexpensive and portable. The unit is scalable, grows with technology, and acts as a gateway to a local network. The device can be configured to address Quality of Service, Priority between technologies and fault-tolerance through management layer.
US11323366B2
Embodiments of the present invention disclose a path determining method, apparatus, and system. In a hybrid network including one controller for implementing a control function, the controller may separately obtain network topology information of a first network and a second network of different network types by using a same control channel protocol. When the controller obtains a path determining requirement for the data transmission path, because the controller has the network topology information of the first network and the second network, during computation of the data transmission path, the controller can determine a path computation result including transmission path parts of the first network and the second network, without performing additional information exchange with another device, and send the path computation result to the first network device. In this way, planning efficiency of the data transmission path is improved.
US11323359B2
Multi-channel communication over wired and/or wireless communication mediums is contemplated. The multi-channel communication may be of the type sufficient to facilitate data delivery utilizing two or more channels/paths associated with an access point configured to facilitate communications with a plurality of devices. The multi-channel communications may be controlled to maximize performance through limitations placed on communications permitted over one or more of the channels/paths.
US11323353B1
In an example, a computer-implemented method includes generating test data that is configured to be identified as data of interest at one or more visibility points in a network having a plurality of network routes. The method also includes injecting the test data into each network route of the plurality of network routes at a location upstream from the one or more visibility points, and determining, for each network route through which the test data travels, whether the test data is identified at the one or more visibility points. The method also includes outputting, for each network route through which the test data travels, data that indicates whether the test data is identified at the one or more visibility points as data of interest.
US11323352B2
System and method for testing a device under test via a wireless communication link. When testing the device under test, an interference signal may be applied to the test scenario. The generation of the interference signal may be controlled based on a monitoring of a frequency spectrum in the test scenario, in particular a frequency spectrum at the device under test. In this way, a more realistic test scenario can be achieved.
US11323350B2
In one embodiment, a processor-readable medium storing code representing instructions that when executed by a processor cause the processor to update, at a memory location, a first flow state value associated with a data flow to a second flow state value when at least one of a packet from the data flow is received or the memory location is selected after a time period has expired. At least a portion of the packet is analyzed when the second flow state value represents a flow rate of a network data flow anomaly.
US11323347B2
Systems and methods for social graph data analytics to determine the connectivity between nodes within a community are provided. A user may assign user connectivity values to other members of the community, or connectivity values may be automatically assigned from third parties or based on the frequency of interactions between members. Connectivity values may represent such factors as alignment, reputation, status, and/or influence within a social graph of a network community, or the degree of trust. The paths connecting a first node to a second node may be retrieved, and social graph data analytics may be performed on the retrieved paths. Network connectivity values and/or other social graph data may be outputted to third-party processes and services for use in initiating automatic transactions or making automated network-based or real-world decisions.
US11323346B1
A system includes a plurality of SIP servers that are configured and arranged to provide services for a respective set of endpoints. A monitor server having at least one processor circuit receives connectivity status of the respective set of endpoint devices based on registration status provided by the endpoints to the SIP servers. Based upon the received connectivity status, endpoints having connectivity problems are parsed into subgroups. Based upon the parsed endpoints, potential problem sources for the connectivity problems of the parsed endpoints are identified. A monitor device having at LAN interface circuit connected to the LAN and at least one processor circuit receives the command from the monitor server and performs a diagnostic test on the LAN. Results from the at least one diagnostic test are provided to the monitor server.
US11323339B1
An example computing device is configured to receive, from a customer device, an indication of a plurality of resources and an indication of a plurality of customer services, each of the plurality of customer services being associated with a corresponding at least one requirement and a corresponding at least one constraint. The computing device is configured to automatically determine, for each requirement and each constraint, whether the requirement or the constraint can only be satisfied by a particular resource of the plurality of resources, and allocate, based on the determining, at least one resource of the plurality of resources to at least one customer service of the plurality of customer services. The example computing device is configured to provide, to the customer device and subsequent to the determining for every requirement and for every constraint, information to enable the customer device to provision the at least one customer service.
US11323336B2
This application discloses a network slice management method and a device that is designed to improve network slice deployment efficiency. In the network slice management method, after obtaining indication information of a network slice template and performance requirement information of a target network slice, a first network management device may determine deployment information of the target network slice based on the two pieces of information, and may manage the target network slice based on the deployment information of the target network slice, without manual involvement. Therefore, network slice deployment efficiency can be improved.
US11323335B2
Embodiments herein relate to a method performed by a RAN node (12), for managing communication on a first network slice in a communications network (1). The communications network (1) comprises partitioned sets of functionalities. A first set of functionalities belongs to the first network slice. The first set of functionalities is at least 5 partly separated from another set of functionalities out of a total set of functionalities in the communications network (1). The RAN node (12) receives, from a CN node (16), information regarding requested resources for a first network slice identified by a network slice identifier. The RAN node (12) determines that the received information does not correspond to a Service Level Agreement (SLA) for the first network slice.
US11323334B2
There is provided a method for evaluating a network comprising: providing graphs each indicative of a respective sequential snapshot of a dynamic graph obtained over a historical time interval, the dynamic graph denoting the network, computing sets of meta-parameters, each set of meta-parameters computed according to a respective graph of the graphs, wherein each one of the meta-parameters denotes a network level parameter computed according to a plurality of at least one of edges and nodes of the respective graphs, analyzing sets of meta-parameters according to values computed based on a physics-based analytical model of an evolving physical system, and predicting a likelihood of stabilization of the network during a future time interval according to an indication of convergence of the values according to a convergence requirement, computed based on the physics-based analytical model during the future time interval.
US11323332B2
Embodiments of the present invention provide a computer system, a computer program product, and a method that comprises generating a first user workplan based on received input; automatically modifying the first user workplan based on subsequent received input, wherein automatically modifying the first user workplan comprises comparing the first user workplan to a performance baseline workplan for a user computing device, measuring a deviation between the performance baseline workplan and the first user workplan; and generating a second user workplan based on any modifications made.
US11323328B2
A network device has an input configured to receive a message relating to a given user attempting to forward one or more packets across a computer network. The message has given user information relating to the given user. In addition, the routing device also has a selector, operatively coupled with the input, configured to select (after receiving the message) a given group routing policy from a plurality of group routing policies. Preferably, the selector is configured to select the given group routing policy as a function of the given user information. The routing device also has an output operatively coupled with the selector. The output is configured to cause routing of user communication across the network using link-layer routes specified by the given group routing policy.
US11323324B2
Disclosed herein are system, method, and computer program product embodiments for analyzing a network. An embodiment operates by a third-party component deriving network data based on a received data packet from a network component configured to perform a network function. The third-party component orders a transaction including second network data from a distributed ledger. The third-party component determines that the first and second network data meet or exceed a condition of a smart contract comprising the condition and an associated network action related to the network function. The third-party component sends the condition of the smart contract and the first and second network data to another third-party component. The third-party component receives a validation that the first and second network data meet or exceed the first condition of the first smart contract and performing the first network action on the network.
US11323322B2
Coordinated timing networks are dynamically merged into a single coordinated timing network. This merge occurs without taking down any of the servers. Each server of the merged coordinated timing network has the same coordinated timing network identifier (CTN ID), and the merged coordinated timing network has one selected primary time server. Optionally, the merged coordinated timing network may include a backup time server and an arbiter.
US11323304B2
Various aspects of the subject technology relate to methods, systems, and machine-readable media for self-correlating network operations. The method includes receiving a stream of network messages, the stream of network messages comprising a variety of network events for various network devices. The method also includes identifying patterns within the stream of network messages, the patterns comprising groupings of the variety of network events. The method also includes determining for each pattern an appropriate operationalization scenario. The method also includes operationalizing the patterns as correlation rules in a correlation engine to automatically detect or predict network alarms from input provided by a fault management system.
US11323300B2
A user equipment (910) is provided for use in a cellular network. The user equipment includes a transceiver (1010), a processor (1020), and a memory (1030). The user equipment (910) is configured to determine, for a data transmission, a mapping form a demodulation reference signal (DMRS) to a PNT-RS. A DMRS resulting signal is generated from a subset of DMRS for a first resource element in a subcarrier. The DMRS resulting signal is copied from the first resource element to a second resource element assigned to the PNT-RS in the subcarrier. The data transmission is transmitted using the DMRS resulting signal and the PNT-RS.
US11323296B1
The embodiments described herein provide for a method and system for training an optimal decision feedback equalization (DFE) coefficient for use in GDDR and DDR applications. The method includes determining a first expected bit pattern using a reference voltage. The method further includes determining a transition voltage value of the first expected bit pattern. The method further includes receiving a second expected bit pattern having a same first bit as the first expected bit pattern. The method further includes determining a transition voltage value of the second expected bit pattern using the reference voltage. The method further includes calculating an optimal reference voltage value by averaging the transition voltage values of the first expected bit pattern and the second-expected bit pattern and storing the optimal reference voltage value in a register corresponding to a logic value of the same first bit.
US11323294B2
An ultra-wideband (UWB) wireless communication system, comprises a first wireless apparatus; a second wireless apparatus that participates in a first ranging sequence with the first wireless apparatus; and a transmission channel between the first and second wireless apparatuses that transmits data of the first ranging sequence. At least one of the first wireless apparatus or second wireless apparatus generating at least one channel impulse response (CIR) and determining from the at least one CIR whether the transmission channel includes a line-of-sight channel. A special purpose processor reduces a current performance level of at least one of the first and second wireless apparatuses during a second ranging sequence in response to a determination that the transmission channel includes the line-of-sight channel.
US11323293B2
A wireless communication method and a wireless communication device. An electronic device for a user equipment in a wireless communication system, including a processing circuit configured to receive, from a base station, channel state information reference signal with a set of reception filters, perform channel estimation on a downlink channel from the base station to the user equipment, select, from the set of reception filters, one or more particular reception filters corresponding to respective channel estimation results that satisfy a first predetermined condition, and signal, from the user equipment to the base station, sounding reference signal with one or more particular transmission filters, wherein the one or more particular transmission filters and one or more particular reception filters are reciprocal respectively.
US11323292B2
Aspects of the disclosure involve systems and methods for utilizing Virtual Local Area Network separation in a connection, which may be a single connection, between a customer to a telecommunications network and a cloud environment to allow the customer to access multiple instances within the cloud through the connection. A customer may purchase multiple cloud resource instances from a public cloud environment and, utilizing the telecommunications network, connect to the multiple instances through a communication port or connection to the cloud environment. To utilize the single connection or port, communication packets intended for the cloud environment may be tagged with a VLAN tag that indicates to which cloud instance the packet is intended. The telecommunications network may route the packet to the intended cloud environment and configure one or more aspects of the cloud environment to analyze the attached VLAN tag to transmit the packet to the intended instance.
US11323283B2
Methods for commissioning a domestic appliance, as provided herein, may include the transmission and receiving of signals between the domestic appliance, a previously-commissioned appliance, a remote user-interface device, and a remote server such that a network credential for a local wireless network is transmitted from the previously-commissioned appliance to the domestic appliance.
US11323272B2
Method of certification including receiving user data at a device of a certifying entity. The method includes generating a salt that is unique. The method includes hashing the data combined with the salt to create a generated hashed data. The method includes generating a certification record based on signing the generated hashed data using a private key of the certifying entity to create a signed certification of the data. The method includes hashing the certification record. The method includes transmitting the hashed certification record to a blockchain for storing. The method includes receiving a certification tx-ID of the hashed certification record. The method includes generating a certification data block including the certification record and the certification tx-ID. The method includes storing the certification data block to a side chain.
US11323267B1
Systems and methods for securely sharing and authenticating a last secret. A system includes a dealer computing system and a combining computing system. The dealer computing system includes a public/private key pair, an encryption key established with the combining computing system, and a circuit structured to generate a last secret and a first key controlling access to a secure computing system. The last secret is the last cryptographic element controlling access to the first key. The circuit is structured to split the last secret into first and second splits. The circuit is structured to generate a first and second SigncryptedData messages by signcrypting each of the first split and the second split with the public/private key pair and the encryption key established with the combining computing system. The circuit is structured to transmit the first SigncryptedData message to a first share-holder and the second SigncryptedData message to a second share-holder.
US11323265B2
A storage device includes a basic memory to store a message received from an external device, a security memory to store an authentication key for authenticating the message, a controller to output a control signal, and a security engine to obtain the authentication key from the security memory with an authority to access the security memory in response to the control signal from the controller and to block an access of the controller to the security memory.
US11323255B2
Disclosed are methods and systems to encrypt/decrypt a data message using Geometric Algebra and Hensel encoding (i.e., finite p-adic arithmetic). The security key(s), message data, and ciphertext are all represented as Geometric Algebra multivectors where a sum of the coefficients of an individual multivector is equal to the numeric value of the corresponding message or security key. Various Geometric Algebra operations with the message and security key multivectors act to encrypt/decrypt the message data. Each coefficient of the security key and message multivectors is further Hensel encoded to provide additional confusion/diffusion for the encrypted values. The Geometric Algebra operations permit homomorphic operations for adding, subtracting, multiplication and division of ciphertext multivectors such that the resulting ciphertext, when decrypted, is equal to corresponding mathematical operations using the unencrypted values. The additional Hensel encoding of the coefficients of the multivectors does not impede the homomorphic aspects of the Geometric Algebra encryption operations. Operations for security key updates and exchanges are also provided.
US11323243B2
An example operation may include one or more of receiving one or more responses to a storage request for a blockchain from one or more endorser nodes of the blockchain, extracting transaction data of the storage request included in the one or more responses, generating a zero-knowledge proof of endorsement based on the extracted transaction data and the one or more responses, and transmitting the zero-knowledge proof to a blockchain node for inclusion within a data block among a hash-linked chain of data blocks.
US11323238B2
A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination. According to this invention, it is possible to provide a frame synchronization apparatus that correctly determines a synchronization state even if an error rate of received symbols is high.
US11323219B2
A triggering method and a transmitting method for an uplink reference signal in a communication system, apparatuses thereof, and a storage medium are provided. The communication system includes at least two different signal parameters. The triggering method applied to a network side includes: generating, by the network side, a trigger signaling for triggering a terminal to transmit the uplink reference signal to the network side for one or more times; and transmitting, by the network side, the trigger signaling to the terminal.
US11323218B2
The present disclosure relates to a communication technique for combining a 5G communications system that supports higher data transmission rates after 4G systems with IoT technology, and a system therefor. The present disclosure can be applied to intelligent services based on 5G communications technology and IoT related technology (for example, smart homes, smart buildings, smart cities, smart cars or connected cars, healthcare, digital education, retail businesses, security and safety related services, and the like). The method for a terminal according to the present invention is characterized by comprising the steps of: receiving a reference signal; generating channel state information by means of a circular application of a precoding matrix for each resource element; and transmitting the channel state information to a base station.
US11323210B2
The present disclosure provides a method and device for transmitting hybrid automatic repeat request (HARQ) information. The method can include monitoring a channel bearing the HARQ information on a target time domain unit, demodulating, on the basis of a HARQ network temporary identity notified by a base station, downlink control information borne by the channel in response to determining that a channel is monitored, and acquiring the HARQ information from a specified information field of the downlink control information.
US11323205B2
A polar code encoding method and apparatus are provided, the method including obtaining a first sequence used to encode K to-be-encoded bits, where the first sequence comprises sequence numbers of N polar channels, where the sequence numbers of the N polar channels are arranged in the first sequence according to reliability of the N polar channels, where K is a positive integer, where N is a mother code length of a polar code, where N is a positive integer power of 2, and where K≤N, selecting sequence numbers of K polar channels from the first sequence in descending order of the reliability, and placing the to-be-encoded bits according to the selected sequence numbers of the K polar channels, and performing polar code encoding on the to-be-encoded bits.
US11323201B2
A method by a terminal in a wireless communication system is provided. Downlink control information including modulation and coding scheme (MCS) information is received from a base station. A number of information bits are identified based on the downlink control information. A transport block size (TBS) is identified based on the number of information bits and a TBS candidate set. The TBS candidate set includes values separated by an interval among a plurality of intervals. Each of the plurality of intervals is a multiple of 8. A first interval between first consecutive values included in the TBS candidate set is larger than a second interval between second consecutive values included in the TBS candidate set. The first consecutive values are greater than or equal to a predetermined value, and the second consecutive values are less than the predetermined value.
US11323199B2
This application provides a sending device, a receiving device, an optical transmission system, and an optical power control method. The sending device includes a multiplexing unit and an optical power adjustment unit. The multiplexing unit is configured to send at least two communication optical waves to a fiber channel, and is further configured to send or receive at least two detection optical waves through the fiber channel. The optical power adjustment unit is configured to: obtain a power control instruction, where the power control instruction is generated according to power change information between the at least two detection optical waves. The optical power adjustment unit is further configured to perform optical power amplification and/or attenuation on at least one communication optical wave in the at least two communication optical waves according to the power control instruction.
US11323196B1
Disclosed embodiments include systems, methods, and media for receiving and transmitting digital data over a plurality of channels. Disclosed embodiments may include receiving data from a plurality of sources through one or more networks. Disclosed embodiments may also include assigning a geographic area to the data from the plurality of sources, the geographic area corresponding to one or more locations associated with the data. Additionally, disclosed embodiments may include determining health effects for a predetermined location based on the data and its associated geographic locations. Further, disclosed embodiments may include generating, by querying a predetermined response database, instructions that address the determined health affects for the predetermined location, the instructions including an action and an associated device. And, disclosed embodiments may include transmitting, to the associated device, the action associated with the instructions.
US11323192B2
The present disclosure provides an adaptive modulation method for a naive Bayes classifier-based energy harvesting relay system. First, a sending end determines its modulation mode based on a status of a data buffer of a relay, so that sent data does not exceed a storage capability of the relay. Then, based on data sent by the sending end, and channel status information and energy harvesting status information within a period of time, the relay determines an optimal modulation mode used by the relay within the period of time. After that, the modulation mode, the channel status information, and the energy harvesting status information are used as training data to obtain a classification model based on a naive Bayes classifier algorithm. In this way, the relay can adaptively select a modulation mode when only knowing of channel information and energy information in a current timeslot.
US11323190B2
Radio frequency channel connection detection methods and apparatus, to detect a connection mode between a radio frequency channel and an antenna, thereby reducing difficulty in secondary onsite construction, and improving construction efficiency. The method includes: receiving, by a first radio frequency unit by using each of N to-be-detected radio frequency channels, signals sent by using at least one of N reference radio frequency channels of a reference radio frequency unit; and determining a connection relationship between the N to-be-detected radio frequency channels and N antennas based on the signals received by using each to-be-detected radio frequency channel.
US11323188B2
Disclosed are implementations, including a method for monitoring a performance of a transmitter in a radio with an adjustable digital predistortion system. The method includes determining a plurality of system characteristics, including determining one or more of, for example, data characterizing an input/output characteristic of a digital predistorter of the system, data characterizing a performance of a crest factor reduction process of the system, data characterizing a quality of a plurality of parameters associated with the digital predistorter, data characterizing an average time delay associated with the system, data characterizing an average gain associated with the system, and/or data characterizing a phase associated with the system. The method further includes comparing one or more of the plurality of system characteristics to respective one or more reference values, and controlling the adjustable digital predistortion system based on a result of the comparing.
US11323186B2
A power over fiber system includes an optical fiber cable. The optical fiber cable includes a core, a first cladding and a second cladding. The core transmits signal light. The first cladding is positioned in contact with periphery of the core and transmits feed light. The second cladding is positioned in contact with periphery of the first cladding. Radial refractive index distribution of the first cladding is distribution in which refractive index gradually decreases from a local maximum at an internal point toward points where the first cladding is in contact with the core and the second cladding, respectively. The internal point is away from the core and the second cladding. The refractive index of the core is higher than the refractive index of the first cladding at the point where the first cladding is in contact with the core.
US11323182B2
A transmitting and receiving device includes a controller, a driver, a specific pattern generator, a transmitting signal detector, an amplifier, a differential amplifier, an average current detector, and a received signal detector. In a non-signal period, the controller causes a current signal to be input from the driver to a laser diode and causes an optical signal to be output from the laser diode. When an optical signal of a specific pattern output from the other-side laser diode reaches a photodiode over a period of length that depends on an average value of a current signal output from the other-side photodiode that receives the optical signal, the controller adjusts a magnitude of the current signal input from the driver to the laser diode based on the length of the period of the optical signal of the specific pattern.
US11323180B2
An analog signal processor includes a sampling unit configured to (i) filter, in the frequency domain, a received time domain analog signal into a low-frequency end of a corresponding frequency spectrum, (ii) sample the filtered analog signal at a frequency substantially higher than the low-frequency end, and (iii) spread quantization noise over an expanded Nyquist zone of the corresponding frequency spectrum. The processor further includes a noise shaping unit configured to shape the spread quantization noise out of the low-frequency end of the corresponding frequency spectrum such that the filtered analog signal and the shaped quantization noise are substantially separated in the frequency domain, and a quantization unit configured to apply delta-sigma modulation to the filtered analog signal using at least one quantization bit, and output a digitized bit stream that substantially follows the amplitude of the received time domain analog signal.
US11323176B2
A cell site test tool provides field technicians with resources to support multiple aspects of cell site testing. The cell site test tool includes multiple, integrated and removably connectable modules such as a base module, a user interface module, and a battery module. Additional modules include a CPRI module to provide Common Public Radio Interface testing, an OTDR module to provide dedicated Optical Time-Domain Reflectometer testing, a CAA module to provide Cable Antenna Analysis testing, a fiber inspection module to visually inspect optical fiber, and an SA/CPRI module to provide Radio Frequency over Common Public Radio Interface testing.
US11323165B2
A wireless communication device includes a plurality of antenna elements; a modulation unit modulating signals including data in a plurality of first OAM modes having different real number values; a calculation unit calculating factors indicating weights corresponding to each of the signals in the plurality of first OAM modes modulated by the modulation unit for each of the plurality of antenna elements, based on information indicating a wireless environment of a counter wireless communication device that is a transmission destination of the data; and a transmission processing unit multiplexing each of the signals in the plurality of first OAM modes for each of the plurality of antenna elements by using the factors, and outputting the signals obtained through multiplexing for each of the plurality of antenna elements to each of the plurality of antenna elements.
US11323160B2
A method of operating a communication node according to some embodiments includes generating (400) a link adaptation for a downlink transmission to a plurality of UEs based on first channel state information, generating (402) estimated SINR values for the UEs based on the link adaptation, obtaining (404) new channel state information for the UEs, generating (406) updated estimated SINR value based on the new channel state information and the link adaptation, modifying (408) a power allocation for the UEs based on the updated estimated SINR, and transmitting (410) data to the UEs using the link adaptation and the modified power allocation.
US11323146B2
An electronic device according to various embodiments of the present invention can comprise: a housing; a first antenna element positioned inside the housing or at a first position thereof; a second antenna element positioned inside the housing or at a second position separated from the first position thereof; and a wireless communication circuit positioned inside the housing and electrically coupled to the first antenna element and the second antenna element. The wireless communication circuit comprises: a wireless modem; a source RF circuit electrically connected to the wireless modem, and configured to generate an IF signal; and a second RF circuit positioned at a fourth position closer to the second position than to the first position, wherein: each of the first RF circuit and the second RF circuit is configured to alternately receive an IF signal for transmitting a transmitted signal via the first antenna element and the second antenna element, and includes a first electrical path between the source RF circuit and the second RF circuit, a second electrical path between the source RF circuit and the second RF circuit, and a third electrical path between the first RF circuit and the second RF circuit; the first RF circuit, while being electrically blocked from the first antenna element, is configured to form at least a portion of a first loopback path from the first RF circuit to the source RF circuit through the third electrical path and the second electrical path; and the second RF circuit, while being electrically blocked from the second antenna element, can be configured to form at least a portion of a second loopback path from the second RF circuit to the source RF circuit through the third electrical path and the first electrical path. Additional other embodiments are also possible.
US11323145B2
Systems and methods are disclosed for correcting Local Oscillator (LO) phase misalignment between different Radio Frequency Integrated Circuits (RFIC) of an Advanced Antenna System (AAS).
US11323141B2
A control method of a multi-antenna module includes the following. Antennas generating signals in at least a first frequency band and a second frequency band are provided. The antennas are divided into a first group and a second group by detecting performance of the antennas in the first frequency band and the second frequency band. Antennas of the first group have better performance in the first frequency band than in the second frequency band, and antennas of the second group are antennas other than the antennas of the first group. The number of the antennas of each of the first group and the second group is at least greater than or equal to 2. The first group is instructed to generate the signals in the first frequency band, and the second group is instructed to generate the signals in the second frequency band.
US11323138B1
Disclosed is an erasure-based Reed-Solomon code soft-decision decoding method and device, capable of reducing a decoding time while minimizing the effect on error correction performance. The Reed-Solomon code soft-decision decoding device includes an erasure control circuit configured to determine whether a number of errors in a codeword is odd or even, and to provide a key equation solver circuit with a first erasure pattern or a second erasure pattern according to a result of the determining when a decoding failure is detected by a decoding error detection circuit, the first erasure pattern being provided when the number of errors is odd, the second erasure pattern being provided when the number of errors is even.
US11323135B2
The present disclosure provides a polar code coding method, a polar code decoding method, apparatus and device. The polar code coding method includes: obtaining a plurality of CRC check bits; determining interleaved padding positions in a to-be-coded sequence; filling a first predetermined number of CRC check bits of the plurality of CRC check bits into the interleaved padding positions in the to-be-coded sequence in an interleaving manner; and performing polar coding on the to-be-coded sequence that is filled with the predetermined number of CRC check bits in interleaving manner, and transmitting a coded sequence to a receiving end. The first predetermined number is less than or equal to a total number of the plurality of CRC check bits.
US11323130B2
A method of filtering includes generating a random value by a random number generator circuit, filtering a first signal by a first filter to form a filtered first signal, dithering the filtered first signal using the random value to form a dithered first signal, filtering a second signal by a second filter to form a filtered second signal, and dithering the filtered second signal using the random value to form a dithered second signal.
US11323124B1
A clock stretcher includes a DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The DLL has a phase error because of its finite bandwidth. The clock stretcher measures the phase error and corrects for a glitch in the modified clock signal by using the phase error when phase selection wraparound occurs. The clock stretcher may operate from a power supply that has droops, without intervening voltage regulation.
US11323120B2
An integrated circuit comprising a field programmable gate array including a plurality of logic tiles, wherein, during operation, each logic tile is configurable to connect with at least one other logic tile, and wherein each logic tile includes: (1) a normal operating mode and test mode, (2) an interconnect network including a plurality of multiplexers, wherein during operation, the interconnect network of each logic tile is configurable to connect with the interconnect network of at least one other logic tile in the normal operating mode and (3) bitcells to store data. The FPGA also includes control circuitry, electrically connected to each logic tile, to configure each logic tile in a test mode and enable concurrently writing configuration test data into each logic tile of the plurality of logic tiles when the FPGA is in the test mode.
US11323106B1
One example includes a glitch filter system. The system includes an input stage to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-element receives the first digital signal and the second digital signal and provides a third digital signal at a first logic state in response to each of the first and second digital signals having a second logic state opposite the first logic state. An output latch provides an output signal at the second logic state in response to the first logic state of the third digital. The output latch also receives the first and second digital signals to maintain the first logic state of the third digital signal in response to one of the first and second digital signals changing from the second logic state to the first logic state.
US11323094B2
Networks and filters are disclosed. A network includes a resonator that exhibits both a resonance and an anti-resonance and an inverter circuit connected in parallel with the resonator to form a composite resonator. An anti-resonant frequency of the composite resonator is different from the resonator's anti-resonant frequency.
US11323087B2
Disclosed is a method and apparatus for determining one or more operation parameters for a dynamic range compression (DRC) system. The method comprises obtaining, as an input, a parameter indicative of a hearing ability of a user, the parameter relating to a first difference in sound intensity between a maskee at a first frequency and a masker at a second frequency, determining a target value for the parameter, and determining the one or more operation parameters such that a second difference in sound intensity after sound intensity modification by the DRC (between sound intensity of the maskee of the masker) corresponds to the target value for the parameter. The operation parameters are determined such that a dependence of the second difference in sound intensity on the sound intensity of the maskee is minimized for a given range of sound intensities of the maskee.
US11323084B2
A linear amplifier includes a pre-amplifier configured to amplify an input differential signal, a post-amplifier configured to amplify an output signal of the pre-amplifier, an amplitude detector configured to detect an amplitude of an output signal of the post-amplifier, and an output voltage corresponding to the detected amplitude, a comparator configured to control a tail current source of the pre-amplifier such that when the output voltage of the amplitude detector is less than or equal to a reference voltage, a tail current of the pre-amplifier is set to a constant value, and when the output voltage of the amplitude detector is larger than the reference voltage, the tail current is reduced to make the output voltage of the amplitude detector equal to the reference voltage.
US11323077B2
Components of a power amplifier controller may support lower voltages than the power amplifier itself. As a result, a surge protection circuit that prevents a power amplifier from being damaged due to a power surge may not effectively protect the power amplifier controller. Embodiments disclosed herein present an overvoltage protection circuit that prevents a charge-pump from providing a voltage to a power amplifier controller during a detected surge event. By separately detecting and preventing a voltage from being provided to the power amplifier controller during a surge event, the power amplifier controller can be protected regardless of whether the surge event results in a voltage that may damage the power amplifier. Further, embodiments of the overvoltage protection circuit can prevent a surge voltage from being provided to a power amplifier operating in 2G mode.
US11323076B2
A method for modelling a power amplifier, including memory effect modelling, for general input waveforms and power levels involves generating an extraction waveform having a plurality of tones each having a different frequency, a difference between the frequencies of two adjacent tones of the plurality of tones not being an integer multiple of a difference in frequency between any two other adjacent tones of the plurality of tones. The method further involves providing the extraction waveform to the power amplifier, receiving output from the power amplifier generated in response to the extraction waveform, and generating a model of the power amplifier based on the output.
US11323074B2
Disclosed in the present invention are a radio frequency power amplifier based on power detection feedback, a chip, and a communication terminal. The radio frequency power amplifier comprises multiple stages of amplifier circuits and at least one power detection feedback circuit; the input end of the power detection feedback circuit is connected to the output end of a current stage of amplifier circuit, and the output end of the power detection feedback circuit is connected to the input ends of the current stage of amplifier circuit and at least one stage of amplifier circuit located prior to the current stage of amplifier circuit. The power detection feedback circuit generates, according to the detected output power of the current stage of amplifier circuit, a control voltage varying inversely with the output power, so that the power detection feedback circuit outputs current varying positively with the control voltage.
US11323071B1
An oscillator includes a resonator, sustaining circuit and detector circuit. The sustaining circuit receives a sense signal indicative of mechanically resonant motion of the resonator generates an amplified output signal in response. The detector circuit asserts, at a predetermined phase of the amplified output signal, one or more control signals that enable an offset-reducing operation with respect to the sustaining amplifier circuit.
US11323069B2
A resonator circuit includes a transformer comprising a primary winding and a secondary winding. The primary winding is inductively coupled with the secondary winding. A primary capacitor is connected to the primary winding. The primary capacitor and the primary winding form a primary circuit. A secondary capacitor is connected to the secondary winding. The secondary capacitor and the secondary winding form a secondary circuit. The resonator circuit has a common mode resonance frequency at an excitation of the primary circuit in a common mode. The resonator circuit has a differential mode resonance frequency at an excitation of the primary circuit in a differential mode. The common mode resonance frequency is different from the differential mode resonance frequency.
US11323067B2
The present invention provides an oscillator circuit and a semiconductor integrated circuit, which can suppress the upper limit of the frequency of a clock signal due to an error of the constant current circuit. The oscillator circuit of the present invention includes a constant current circuit, an oscillator, and a current limiting circuit. The constant current circuit generates a first output current according to a supply voltage. The current limiting circuit receives the first output current and generates a second output current, and establishes an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit. The oscillator generates a clock signal according to the second output current. By establishing the upper limit for the second output current, the upper limit of the frequency of the clock signal can be suppressed.
US11323064B2
A processing device for forming connection conductors for semiconductor components, in particular for producing a periodic structure, which device includes a forming unit for forming at least one connection conductor. The processing device has an advancing unit which is designed to move the connection conductors and the forming unit relative to one another in a direction of advance, and the forming unit has at least one step element, at least one forming element which can be moved relative to the step element, and a forming-element moving unit for moving the forming element relative to the stop element, the forming element, stop element and forming-element moving unit being designed to cooperate such that the connection conductor can be bent by moving the forming element between the stop element and the forming element by the forming-element moving unit. A method for forming connection conductors for semiconductor components is also provided.
US11323063B2
A heliostat includes an optical member (e.g., a mirror), a mounting frame under the optical member, a support stand and a hinge assembly. The hinge assembly allows the optical member to pivot about two orthogonal directions relative to the support stand. A drive mechanism adjusts one or both of an elevation angle and a roll angle of the optical member.
US11323056B2
To provide a controller for AC rotary electric machine which can reduce an electromagnetic exciting force in the execution region of the magnetic flux weakening control. A controller for AC rotary electric machine, in a specific operating region which is set in an operating region of the magnetic flux weakening control, increases a maximum value of amplitude of fundamental wave components of applied voltages applied to windings more than a normal operating region other than the specific operating region; and calculates dq-axis current command values by the magnetic flux weakening control, in a condition in which the maximum value of amplitude of the fundamental wave components of the applied voltages is increased.
US11323049B2
A drive device includes a first inverter and a second inverter configured to respectively drive two rotary electric machines. Carrier signals for controlling the first inverter and the second inverter are set to be in mutually opposite phases. For at least one connection line out of a connection line between the first inverter and one of the rotary electric machines and a connection line between the second inverter and another one of the rotary electric machines, a balance capacitor and a balance inductor are disposed between the at least one connection line and a ground potential such that an impedance to ground generated between the one of the rotary electric machines and the ground potential coincides with an impedance to ground generated between the other one of the rotary electric machines and the ground potential.
US11323048B2
A device for driving a plurality of motors and an electric apparatus includes a first and a second capacitor, an inverter connected to a DC terminal, a multi-phase motor connected to the inverter, a single-phase motor serially connected with the multi-phase motor, and a controller configured to control the inverter. For starting the single phase motor during operation of the multi-phase motor, the controller is configured to perform, during an alignment period, an alignment of a rotor of the single-phase motor and perform, during a voltage compensation period, a voltage compensation for compensating a voltage change of a DC terminal neutral point between the first capacitor and the second capacitor based on the alignment of the rotor of the single-phase motor.
US11323031B2
First and second FETs of a half-bridge are series connected between first and second terminals and are gate driven, respectively, by first and second drivers. An inductance is connected to the intermediate node of the half-bridge. Power supply for the second driver circuit is a supply voltage generated by a voltage regulator as a function of the voltage between the first and the second terminal. Power supply for the first driver circuit is a supply voltage generated by a bootstrap capacitor having a first terminal connected via a first switch to receive the supply voltage output from the voltage regulator and a second terminal connected to the intermediate node. The first terminal of the bootstrap capacitor is further connected by a second switch to receive a second supply voltage. A control circuit generates control signals for the first and second driver circuits and the first and second switches.
US11323027B2
Apparatus, systems, and methods are disclosed, including a high-voltage charge pump including multiple pump stages connected in series to provide a high-voltage output, a common discharge circuit, and multiple high-voltage devices coupled between the outputs of each of the multiple pump stages and the common discharge circuit. Each of the multiple pump stages include a low-voltage switching device. The common discharge circuit is coupled to each of the multiple pump stages and is configured to discharge the multiple pump stages when the multiple pump stages are disabled. The multiple high-voltage devices include a respective high-voltage device coupled between an output of each of the multiple pump stages and the common discharge circuit.
US11323018B2
A control system controls a plurality of controllable units with a central control device and further has a plurality of control modules, each of which is assigned to one of the units to be controlled. The central control device is set up to exchange digital data with each control module. The control modules form a connection network, wherein each control module is connected to at least one other control module via a communication line so that data exchange between them is possible. One of the control modules is directly connected to the central control device as the master node of the connection network, and the control modules are set up to form a communication network within the connection network, so that the data exchange between the central control device and each control module can be respectively carried out via an assigned communication path within the communication network.
US11323004B2
A rotating electric machine includes a non-rotating member, a stator fixed to the non-rotating member, a field coil fixed to the non-rotating member, disposed on an inner diameter side of the stator, and having an iron core and a winding wound around the iron core, and a rotor rotatably disposed between the stator and the iron core. A flow path through which a heat exchange medium is supplied and discharged is formed in the iron core along an axial direction thereof.
US11322999B2
The present invention relates to an electric motor (1) comprising a rotor main body (2), to which a plurality of permanent magnets (3) or a rotor winding can be attached, and a shaft (4) for receiving the rotor main body (2), characterized in that an isolation body (5) is arranged between the shaft (4) and the rotor main body (2) to electrically isolate the rotor main body (2) from the shaft (4), in that the isolation body (5) engages at least partially into the shaft (4) and into the rotor main body (2) in order to connect the shaft (4) and rotor main body (2) for conjoint rotation, and in that the isolation body (5) is made from a composite of ceramic and plastic.
US11322997B2
The invention relates to a rotor for a synchronous drive motor of an electrically driven motor vehicle having several rotor poles, wherein each rotor pole has at least three magnetic layers arranged radially one after the other with cavities, wherein an outermost magnetic layer includes at least one cavity filled with permanent magnetic material and each further magnetic layer includes at least two cavities filled with permanent magnetic material, furthermore each magnetic layer has an extension of a section of an ellipse, furthermore the central points of all ellipses lie within the smallest ellipse of the outer magnetic layer, wherein each cavity belonging to one of the at least three magnetic layers defines an interface in a radial plane, and each of these interfaces of a magnetic layer of the corresponding ellipse is divided into two partial interfaces, wherein bars made of the rotor material are formed in the second and every other magnetic layer between the cavities, and these bars, at the narrowest point, are at least twice as wide as the respective outer bars of the same magnetic layer.
US11322994B2
A radial flux electric machine includes a rotor configured to rotate about an axis of rotation and a stator. At least one of the rotor or the stator may include a plurality of teeth annularly arranged about the axis of rotation. The electric machine may also include a plurality of electromagnetic coils. Each coil of the plurality of electromagnetic coils may have a non-uniform trapezoidal cavity therethrough. Each cavity may be configured to contain therein one tooth of the plurality of teeth. Each tooth of the plurality of teeth may be formed of multiple pieces that, when assembled together correspond to a shape of the non-uniform trapezoidal cavity.
US11322980B2
In one aspect of the present disclosure, an induction hub is disclosed for use in powering components in a vehicle. The induction hub includes a source coil; first and second receiver coils having first and second conductive portions, respectively; and at least one isolation member that is positioned between the first and second conductive portions. The receiver coils are separated from the source coil such that, upon being energized by a power source, the source coil creates an induced electromagnetic field (EMF) and an electrical current in the receiver coils, which are in electrical communication with at least one component in the vehicle to thereby deliver power from the receiver coils to the at least one component. The at least one isolation member includes a material that is electrically nonconductive and electromagnetically permeable so as to physically and electrically separate the receiver coils without impacting the induced EMF.
US11322977B2
A system and method to join distributed energy resources (DER) to achieve common objectives is provided. The present technology organizes and/or aggregates DERs by routing a (DER) program request for resources to DER contributors capable of responding to and performing the request using a routing system. The system accesses a plurality of DER profiles, each profile associated with a DER contributor capable of contributing a resource to the request, and calculates an initial value for each DER profile based on request attributes and scoring metrics associated with the profile. The system then calculates a fitness metric for each DER profile based on the initial value using a neural network having weights based on the plurality of performance indicators and selects the DER profile and contributors to whom to route the request.
US11322971B2
The disclosure generally relates to wireless sensing nodes, energy harvesting, and energy charging. The disclosure also generally relates to reporting data gathered by the wireless sensing nodes to one or more network services.
US11322967B2
A control device for controlling discharging of a rechargeable battery, the control device being configured to: determine the voltage of the battery during discharging of the battery, stop discharging, when the determined voltage falls below a first predetermined lower voltage limit, determine the voltage of the battery after stopping discharging, determine the voltage difference between the first predetermined lower voltage limit and the determined voltage of the battery after stopping discharging, and continue discharging, when the determined voltage difference exceeds a predetermined threshold. A corresponding method controls discharging of a rechargeable battery.
US11322960B2
A battery system includes a battery pack including a plurality of cells, and an ECU. The ECU calculates a current distribution in each cell using a ladder circuit network model, the ladder circuit network model being obtained by geometrically modeling an interior of the cell using a plurality of resistance elements and a plurality of power storage elements. The ECU calculates the current distribution in the cell by applying, to the ladder circuit network model, a resistance distribution in the cell calculated based on a salt concentration distribution in the cell.
US11322952B2
Systems, methods, and apparatus for providing a homopolar generator charger with an integral rechargeable battery. A method is provided for converting rotational kinetic energy to electrical energy for charging one or more battery cells. The method can include rotating, by a shaft, a rotor in a magnetic flux field to generate current, wherein the rotor comprises an electrically conductive portion having an inner diameter conductive connection surface and an outer diameter conductive connection surface, and wherein a voltage potential is induced between the inner and outer diameter connection surfaces upon rotation in the magnetic flux field. The method can also include selectively coupling the generated current from the rotating rotor to terminals of the one or more battery cells.
US11322946B2
Disclosed is a battery pack, including: at least one battery module which includes a plurality of battery cells and is connected between a first terminal and a second terminal; a relay connected between the first terminal and a third terminal; and a battery management system (BMS) which is connected to the first to third terminals, and generates a charge control signal controlling a charge operation of a charger connected to the third terminal based on battery detection information obtained by detecting the plurality of battery cells and the at least one battery module.
US11322945B2
Methods, systems, and computer storage media are disclosed for determining electric energy flow predictions for electric systems including photovoltaic solar systems. In some examples, a method is performed by a computer system and includes supplying a consumption time series and a predicted production time series for an electric system to a machine-learning predictor trained during a prior training phase using electric energy consumption training data and photovoltaic production training data. The consumption time series has a first data resolution, and the electric energy consumption training data and the photovoltaic production training data have a second data resolution greater than the first data resolution. The method includes determining, using an output of the machine-learning predictor, a predicted import time series of electric import values each specifying an amount of electric energy predicted to be imported by the electric system with a prospective photovoltaic solar system installed.
US11322938B2
A method and apparatus for estimating capacity of a system including an energy generation system, an energy storage system or both. The method and apparatus initially estimate the system capacity based on a facility location and size. The initial estimate may be adjusted through adjustment of at least one parameter. An updated capacity estimate is generated and displayed.
US11322929B2
An apparatus for detecting an open neutral condition in a split phase power system is described. The apparatus includes two powered lines providing output electricity to an electrical distribution system and a shared neutral line providing a grounded neutral to the first and second powered lines. The apparatus is configured for detecting when an open neutral condition is present in the split phase power system by determining when a power current is present on one or both of the first and second powered lines while a return current is not present on the neutral line; and in response to detecting that the open neutral condition is present, causing an interrupter to interrupt the power supplied by the first and second powered lines or to generate a signal indicating an open condition.
US11322924B2
Provided is a thunderbolt arrest-type lightning protection device that has a protected area formed to match a structure and a shape of a protected body being protected from thunderbolts, and is capable of effectively protecting the entire protected body from thunderbolts.
The device is configured by: a charged body 2 formed of a conductive material provided to cover a protected body B installed on a ground G; an electrical insulation layer 3 that holds the charged body 2 in an electrically-insulated state with respect to the ground G and the protected body B; a capacitor 4 installed on the ground G, and stores an electrical charge by an electrostatic capacity with the ground; and a conductor 5 that electrically connects the charged body 2 and a second electrode body 4b.
US11322923B2
An overhead power distribution line (10) comprises a tension resistant pole (101), two composite crossbeams (102) and tension resistant fixing members (103). A middle portion of the composite crossbeam (102) is horizontally secured on the tension resistant pole (101), and end portions of the composite crossbeam (102) are connected to the tension resistant fixing members (103). The tension resistant fixing members (103) enable the two composite crossbeams (102) to integrally connect and are for fixing conducting lines. With the above configuration, two composite crossbeams (102) are secured on the same horizontal plane of the tension resistant pole (101), thus satisfying vertical tension of a tension resistant requirement. Further, by using composited crossbeam bodies (102), a dry arc distance is significantly increased, and electrical lightning resistance performance is enhanced, preventing incidents such as line disconnection and flashover caused by lightning strike. The composite crossbeams (102) are maintenance-free and do not require periodical inspection and maintenance, significantly reducing labor costs. The use of crossbeams (102) can further eliminate the use of tension insulators and simplify the structure of lines.
US11322918B2
The present invention relates in general to the field of high voltage power line insulators, and more specifically, to a tool for installing high voltage power line insulators and a method of use. The installation tool includes a feature that allows a lineworker to safely install high voltage power line insulators of different shapes and sizes using the same installation tool. In particular, the installation tool comprises differently sized sockets that correspond to the distinct head size dimensions of different types of high voltage power line insulators. A purpose of the invention is to provide a tool for installing high voltage power line insulators and a method of use that minimizes risk of injury to the lineworker during installation, is easy to use, and cost-effective to manufacture.
US11322893B2
An electrical connector includes an insulating body having a mating surface. An insertion slot is concavely provided on the mating surface. Two side walls are located at two sides of the insertion slot. A slot bottom surface is formed on a concave direction of the insertion slot. One of the side walls is provided with aground accommodating slot and a signal accommodating slot. A signal terminal and a ground terminal are provided on the one of the side walls. The signal terminal is accommodated in the signal accommodating slot. The ground terminal is accommodated in the ground accommodating slot. A side of the insulating plug member has a first portion corresponding to the signal accommodating slot and a second portion corresponding to the ground accommodating slot. The first portion is accommodated in the signal accommodating slot and is provided closer to the mating surface than the slot bottom surface.
US11322881B2
A connection device may include a releasable electrical connection between a first current conducting element of a power electronics system and a second current conducting element of a transmission. The connection device may be configured such that it is removably locatable in a first opening in at least one of a power electronics housing and a second opening in a transmission housing. A transmission for a motor vehicle may include the connection device.
US11322876B2
A connector is provided with a housing, a plurality of first terminal fittings, and a plurality of second terminal fittings. The terminal fittings are press-fitted from a rear side of press-fit holes of the housing and arranged to be parallel in a left-right direction. A first projecting part is formed on both left and right edge parts of each of the first terminal fittings, and a second projecting part is formed on both left and right edge parts of each of the second terminal fittings. Each of the projecting parts has a shape where only a portion of the terminal fitting in a length direction projects in the left-right direction, and a pressing surface that is pressed by a jig during press-fitting is formed. The projecting parts of adjacent terminal fittings are arranged such that formation positions thereof are not aligned in the front-rear direction.
US11322875B2
A connector (10) according to the present disclosure includes an insulator to be fitted to a connection object (60), and contacts (50) attached to the insulator. Each of the contacts (50) includes a contact portion (59), a first elastic portion (54A), a first adjustment portion (54B1), and a second adjustment portion (54B2). The contact portion (59) electrically contacts the connection object (60) when the insulator and the connection object (60) are fitted together. The first elastic portion (54A) is elastically deformable and extends from a first base (51) supported by the insulator. The first adjustment portion (54B1) is formed continuously with the first elastic portion (54A) and has an electric conductivity higher than that of the first elastic portion (54A). The second adjustment portion (54B2) is formed continuously with the first adjustment portion (54B1) and has an electric conductivity lower than that of the first adjustment portion (54B1).
US11322874B2
A lock member has: a contact part that contacts one surface of an object to be connected; a locking part that has a shape allowing engagement with a part to be locked formed on the object to be connected; a connection part; and a pressure-receiving part that is pressed by a pressing member. The lock member includes at least one contact provided with a fixing function and used to enable electrification. The locking part projects in a direction that moves away from a board-mounting surface at a side near the board-mounting surface, at a position corresponding to the part to be locked of the object to be connected. The contact part is positioned on the side far from the board-mounting surface at the side facing the locking part, and at a position closer to an insertion side of the object to be connected than the locking part.
US11322870B2
A connector (10) according to the present disclosure is fitted with a connection object (60). The connector includes a first insulator (20), a second insulator (30) movable relative to the first insulator (20), and one or more contacts (50) mounted to the first insulator (20) and the second insulator (30), wherein the second insulator (30) has a receiving portion (33) that is superimposed on the first insulator (20) from a fitting side in a fitting direction between the connector (10) and the connection object (60).
US11322866B2
A system for transmitting power and current includes a power cable having stranded wires and an exposed end. The stranded wires are ultrasonically welded together. Ultrasonically welding the wires creates a bundle of wires at the exposed end that may be free from air pockets, reducing oxidation and improving the current path through the cable.
US11322863B2
A tool-less terminal block includes an insulated base, a turning part, a conductive terminal and a spring clamp. The insulated base has a cavity and a slot communicating to the cavity; the turning part is pivotally coupled to the insulated base; the conductive terminal is fixed to the bottom of the slot; the spring clamp is accommodated in the cavity and disposed at the top of the conductive terminal, and the spring clamp has a movable elastic arm pressing the conductive terminal to seal the slot, and the movable elastic arm has a link rod fixed to the turning part and operable together with the turning part. When the turning part is turned to a released position, the link rod is pulled by the turning part to drive the movable elastic arm away from the conductive terminal to open the slot, so as to provide a convenient use.
US11322862B2
A conductor connection terminal having at least one first spring-loaded clamping connection with a first operating lever for opening and closing a first clamping point formed between a first clamping leg and a first busbar section and at least one second spring-loaded clamping connection with a second operating lever for opening and closing a second first clamping point formed between a second clamping leg and a second busbar section and wherein the at least first spring-loaded clamping connection and the at least second spring-loaded clamping connection are arranged directly side by side in a direction of arrangement in a housing in the direction transverse to a conductor insertion direction. At least two operating levers arranged directly side by side in the direction of arrangement are designed differently.
US11322858B2
An antenna unit and an antenna array. The antenna unit includes M layers of cross metal patches, M layers of dielectric substrates, and a metal ground layer, where M is an integer greater than 1. In addition, an ith-layer dielectric substrate is disposed between an ith-layer cross metal patch and an (i+1)th-layer cross metal patch. The ith-layer cross metal patch, the ith-layer dielectric substrate, and the (i+1)th-layer cross metal patch are sequentially stacked, and i is an integer ranging from 1 to M−1. An Mth-layer cross metal patch, an Mth-layer dielectric substrate, and the metal ground layer are sequentially stacked. The antenna unit and the antenna array formed by units may have a good polarization feature, a relatively wide operating bandwidth, and a relatively good phase shift feature.
US11322851B2
Described are several embodiments of parabolic reflective antenna systems where rigid parabolic dishes based on shape memory materials are deployed to full size and shape from compact pre-folded preforms by application of heat. Several shape memory feeds working with the dishes are presented. Feed preforms include corrugated, telescopic and flattened ribbon types which extend or unfurl into final shapes upon application of heat. Several dish and feed embodiments also contain supports for secondary reflectors and patch antennas.
US11322846B2
An antenna device according to an embodiment of the present invention includes a dielectric layer, a first radiation pattern disposed on the dielectric layer, a second radiation pattern disposed in the first radiation pattern and partially separated from the first radiation pattern, and a transmission line commonly connected to the first radiation pattern and the second radiation pattern.
US11322842B2
A composite right/left-handed transmission line antenna includes a first radiator, a second radiator, and a capacitive matching circuit, where the first radiator is connected to the second radiator, the connected first radiator and second radiator are of a ring shape, and the matching circuit is connected to a feed-in point of the first radiator or the second radiator.
US11322831B1
The radar cross section (RCS) of a vehicle/antenna combination is reduced by using an antenna and ground plane which are of substantially the same area, and using a frequency selective surface (FSS) in the regions on the periphery of the ground plain where the FSS is designed to be transparent and thereby pass out-of-band frequencies, while reflecting one or more operating frequencies of the antenna. A multilayer absorber below the FSS absorbs the out-of-band frequencies that a larger ground plane may have otherwise reflected to the body of the vehicle to which the antenna is mounted.
US11322829B2
An antenna assembly and an electronic device are provided according to the present disclosure. The antenna assembly includes an antenna module and a bandwidth matching layer. The antenna module is configured to transmit and receive, within a preset direction range, a millimeter wave signal in a target frequency band. The bandwidth matching layer is spaced apart from the antenna module, and at least part of the bandwidth matching layer is disposed within the preset direction range. The bandwidth matching layer is configured to match an impedance of the antenna module to an impedance of free space to enable an impedance bandwidth of the antenna module in the target frequency band when the bandwidth matching layer is provided to be greater than an impedance bandwidth of the antenna module in the free space.
US11322828B2
A method of manufacturing a relay includes a molded resin element step configured to produce a molded resin element with an IC chip is embedded therein by injecting a resin around the IC chip; an assembly step configured to apply the molded resin element to a base material as an exterior jacket component of the relay, the base material serving as the main body of the relay; and an antenna wiring forming step configured to print an antenna wiring on a surface of the molded resin element, the antenna wiring configured to allow the IC chip to perform wireless communication.
US11322821B2
Disclosed are an antenna reflective net and an antenna reflective net mounting structure. Sliding slots are provided on side walls of the antenna reflective net mounting structure respectively. Protrusions of a base of the antenna reflective net slide into the sliding slots, and the size of the sliding slot is adapted to that of the protrusion. The protrusion is fixed in the sliding slot along a direction vertical to the sliding slot. A baffle block is provided at a distal end of the sliding slot. The baffle block restricts the protrusion from sliding along the direction of the distal end. Moreover, a limit part of an elastic pressing member of the antenna reflective net mounting structure restricts the protrusion from sliding along the direction of the entrance end of the sliding slot after the protrusion enters the sliding slot. Therefore, the antenna reflective net is easily mounted in the antenna reflective net mounting structure with high stability.
US11322808B2
A secondary battery module showing excellent packing efficiency which makes it possible to connect a secondary battery and a charge/discharge device with a stably low resistance without any unnecessary deformation of the secondary battery or an electrode terminal is disclosed. The secondary battery module includes a plurality of stack units, each of the stack units including: at least one non-conductive plate member; at least one conductive member fixed to the plate member; a secondary battery stacked on the plate member; and at least one electrode terminal sticking out of a side face of the secondary battery, and held by the conductive member.
US11322798B2
This disclosure relates to a rechargeable battery cell having a positive electrode, a negative electrode, an electrolyte, which comprises a conducting salt, and a separator, which is arranged between the positive electrode and the negative electrode. The negative electrode and the positive electrode are each an insertion electrode. The electrolyte is based on SO2. The separator comprises a separator layer which is an organic polymer separator layer. The thickness of the organic polymer separator layer, relative to the loading of the positive insertion electrode with active material per unit area, is less than 0.25 mm3/mg.
US11322796B2
A resin composition for fabricating a separator which is easy to control viscosity, a method of preparing the same, and a battery including the same, are disclosed.
US11322772B2
Battery assembly techniques and a corresponding system are disclosed. In various embodiments, the battery assembly techniques include compressing battery cells and inserting the battery cells in a can. Battery cells are stacked and then compressed using pneumatic cylinders that exert pressure on a first external layer of the stacked battery cells. A first portion of the stacked battery cells is released from the pneumatic cylinders while a second portion of the battery cells remains compressed. The first portion of the stacked battery cells is inserted in a can. In various embodiments, friction decreasing materials are added to the stacked battery cells to compress the stacked battery cells or ease insertion.
US11322770B2
A fuel cell includes a fuel cell stack, a casing, an application part, and a facilitating mechanism. The facilitating mechanism has a space that is provided between the casing and an upper current collector. The upper current collector and the casing are connected at inclined surfaces.
US11322765B2
Methods for optimizing, designing, making, and assembling various component parts and layers to produce optimized MEAs. Optimization is generally achieved by producing multi-layered MEAs wherein characteristics such as catalyst composition and morphology, ionomer concentration, and hydrophobicity/hydophilicity are specifically tuned in each layer. The MEAs are optimized for use with a variety of catalysts including catalysts with specifically designed and controlled morphology, chemical speciation on the bulk, chemical speciation on the surface, and/or specific hydrophobic or hydrophilic or other characteristics. The catalyst can incorporate non-platinum group metal (non-PGM) and/or platinum group metal (PGM) materials.
US11322751B2
A battery includes an electrode group including an air electrode and a negative electrode stacked with a separator therebetween, and an accommodating bag accommodating the electrode group along with an alkali electrolyte solution. The air electrode includes a catalyst for an air secondary battery. This catalyst for an air secondary battery is produced by a method for producing a catalyst for an air secondary battery, the method including a precursor preparation step of preparing a bismuth-ruthenium oxide precursor, a calcination step of calcining the bismuth-ruthenium oxide precursor obtained in this precursor preparation step to form a bismuth-ruthenium oxide, and a nitric acid treatment step of immersing the bismuth-ruthenium oxide obtained by this calcination step in a nitric acid aqueous solution.
US11322749B2
A battery using porous polymer materials with tapered or cone-shaped metalized pores. The types of batteries include, but are not limited to, Li—CoO2, Li—Mn2O4, Li—FePO4, Li—S, Li—O2, and other lithium cathode chemistries. The tapered metalized pores contain lithium metal in small reaction zones in the anode and cathode in a flexible structure. The form factor of such assembly would be very thin. Because of the thin form factor these electrodes would be suitable for batteries that require high power density, such certain electrical vehicles, power tools, and wearable devices.
US11322748B2
A method of forming a metal oxy-fluoride surface on lithium metal oxide cathode material particles is disclosed. Such a metal oxy-fluoride surface may help to prevent lithium metal oxide cathode active materials from reacting with water, thus enabling aqueous processing of cathodes made from such materials in the manufacture of lithium batteries. Such a method may also reduce lithium battery manufacturing costs and time by substituting water for currently-used organic solvents that are expensive and require special handling and disposal. Such a method may also reduce the cost of lithium metal oxide cathode active materials as the requirements for moisture-free manufacture, storage, and processing will be reduced or eliminated.
US11322747B2
A solid-state battery cell includes a cathode comprising a cathode glass fiber scaffold impregnated with cathode active material, an anode comprising an anode glass fiber scaffold impregnated with lithium metal or a lithium metal alloy, and a first electrolyte layer comprising an electrolyte glass fiber scaffold impregnated with a first solid-state electrolyte, the electrolyte layer positioned between the cathode and the anode and the electrolyte glass fiber scaffold extending throughout the first electrolyte layer.
US11322739B2
The present application relates to a secondary battery, a method for manufacturing the same and an apparatus containing the same. Specifically, in the secondary battery, the first negative electrode film comprises a first negative electrode active material, the second negative electrode film comprises a second negative electrode active material. The first negative electrode active material comprises natural graphite and satisfies: 12%≤A≤18%; the second negative electrode active material comprises artificial graphite and satisfies: 20%≤B≤30%; A is a resilience rate of the first negative electrode active material measured under an action force of 15,000 N, and B is a resilience rate of the second negative electrode active material measured under an action force of 15,000 N. The secondary battery of the present application can have better kinetic performance and better high-temperature storage performance while maintaining higher energy density.
US11322729B1
A method for manufacturing zinc negative electrodes includes mixing a powder including zinc with polytetrafluoroethylene to form a homogenous blend, injecting a lubricant into the homogenous blend to form a dough, kneading the dough to form a fibrillated dough, and extruding the fibrillated dough through a die to form a ribbon. The method also includes calendering the ribbon to a target thickness to form a plaque, drying the plaque to form an active material sheet, laminating portions of the active material sheet to a current collector substrate to form an electrode blank, and sectioning the electrode blank into zinc negative electrodes.
US11322724B2
The present disclosure relates to the field of display, and specifically provides a display substrate, a fabricating method thereof, and a corresponding display device. The display substrate includes a first transparent electrode and a second reflective electrode opposite to each other, a light emitting layer between the first transparent electrode and the second reflective electrode, an organic material layer on a side of the first transparent electrode away from the light emitting layer, and a transflective layer on a side of the organic material layer away from the light emitting layer.
US11322723B2
A packaging structure, a display component and a display device are provided by the present disclosure. The packaging structure includes: a substrate; a light-emitting unit arranged on the substrate; a packaging layer, by which the light-emitting unit is packaged on the substrate; and a water-absorbing layer which is arranged in the packaging layer and completely wrapped by the packaging layer.
US11322721B2
An encapsulation structure of an organic light emitting diode (OLED) display panel and a manufacturing method thereof are provided. By changing an edge design of a panel encapsulation structure and adding an encapsulation reduction layer to the encapsulation structure, the encapsulation reduction layer can be restored by subsequent processing after the encapsulation reduction layer is eroded by water and oxygen. This prevents an OLED display device from being oxidized, thereby extending a life of a device.
US11322707B2
A light-emitting device is configured to emit light in improved accordance with the Rec. 2020 specification. The light emitting device includes a substrate; a first electrode disposed on the substrate between an outer surface of the light emitting device and the substrate; a second electrode disposed between the first electrode and the outer surface; a first emissive layer in electrical contact with the first electrode and the second electrode, wherein the first emissive layer includes quantum dots that emit light when electrically excited, and wherein the first emissive layer is associated with a first peak wavelength, λ1; and a second emissive layer disposed between the first emissive layer and a viewing side of the light emitting device, wherein the second emissive layer is a photoluminescent layer that includes quantum dots that emit light when optically excited, and the second emissive layer is associated with a second peak wavelength, λ2, different from the first peak wavelength. The second emissive layer operates to convert a portion of light emitted by the first emissive layer from the first peak wavelength to the second peak wavelength, such that the resultant overall emission is in accordance with the Rec. 2020 specification.
US11322703B2
A photoelectric conversion element according to an embodiment of the present disclosure includes: a first electrode; a second electrode opposed to the first electrode; and an organic photoelectric conversion layer provided between the first electrode and the second electrode and formed using a plurality of materials having average particle diameters different from each other, the plurality of materials including at least fullerene or a derivative thereof.
US11322697B2
A flexible organic light emitting diode (OLED) panel is provided. The flexible OLED panel includes a flexible substrate including a light emitting region, a thinned region, and a wiring region, wherein the light emitting region is adjacent to the wiring region, the thinned region is disposed between the light emitting region and the wiring region, and the thinned region includes: a substrate groove; and a first ductile material disposed in the substrate; a plurality of metal wires disposed on the light emitting region and the wiring region of the flexible substrate; a light emitting layer disposed on one of the metal wires, and the light emitting layer located in the light emitting region; and an encapsulation layer disposed on the light emitting layer, and the encapsulation layer including an encapsulation-layer groove located in the thinned region, wherein the encapsulation-layer groove is opposite to the substrate groove.
US11322696B2
The present invention relates to binuclear metal complexes and electronic devices, in particular organic electroluminescent devices containing said metal complexes of the formula (1):
US11322694B2
The present application provides an electroluminescent material, a method for manufacturing an electroluminescent material, and a light emitting device, by employing the strong electron-withdrawing group such as cyano, pyridine, pyrimidine, or s-triazine to enhance the electron-withdrawing property of the fluorenone receptor unit, a captodative electron effect between the electron donor unit and the electron acceptor unit in the molecule is enhanced, so that the intermolecular charge transfer property is enhanced while the red light shifts, thereby further reducing the energy level difference between the single-line energy level and the triplet energy level of the target molecule, to realize a long life span, red light emitted electroluminescent material, a method for manufacturing the electroluminescent material and a light emitting device.
US11322691B2
The present invention includes novel compounds containing heterocycles or azaheterocycles and fused phenylene or aza and cyano substituted variants thereof. These compounds may be useful as host materials for phosphorescent electroluminescent devices. In some embodiments, the invention includes compounds of Formula I:
US11322688B2
Disclosed are an N-type semiconductor composition including fullerene or a fullerene derivative; and fullerene subunit derivative represented by Chemical Formula 1, and a thin film, an organic photoelectric device, an image sensor and an electronic device including the same. In Chemical Formula 1, X, Cy and R1 to R8 are the same as defined in the detailed description.
US11322681B2
A storage element including a storage layer configured to hold information by use of a magnetization state of a magnetic material, with a pinned magnetization layer being provided on one side of the storage layer, with a tunnel insulation layer, and with the direction of magnetization of the storage layer being changed through injection of spin polarized electrons by passing a current in the lamination direction, so as to record information in the storage layer, wherein a spin barrier layer configured to restrain diffusion of the spin polarized electrons is provided on the side, opposite to the pinned magnetization layer, of the storage layer; and the spin barrier layer includes at least one material selected from the group composing of oxides, nitrides, and fluorides.
US11322678B1
A mounting pad system and method for an HVAC outdoor unit that includes providing a lightweight fillable pad shell containing a gelling material and having securing slots extending from an underside surface to an upperside surface of the shell. The shell is filled with water through a port at its upper surface. Prior to leveling the filled pad on the soil at the site and installation of the outdoor unit, securing straps are inserted into the slots from the underside surface of the shell so as to extend through an upper surface thereof. The filling port is covered when the HVAC unit is placed on top of the pad. One or more securing anchors can be used to anchor the pad to the ground, which are also covered when the HVAC unit is place on top of the pad and an anti-theft cable can be employed to further prevent theft.
US11322677B2
The invention involves providing a reset signal before and or after one or more actuation signals to an electroactive polymer structure of an actuator. The reset signal can cause relaxation of defects such as e.g. trapped charge, dipoles and/or others in the EAP or EAP structure so that upon a subsequent activation using a drive signal, the initial actuation state is defined to be more constant than without use of the reset signal. Hence the actuation 5 output of a device employing the invention is more reproducible. The invention is applicable to actuator devices that have an electroactive polymer structure including an EAP material, where the structure is capable of providing a mechanical actuation upon subjection of at least part of the EAP material to an electrical drive signal.
US11322676B2
A multilayer ultrasonic transducer of an embodiment includes: a plurality of stacked oscillators; external electrodes disposed on outer exposed surfaces of two oscillators disposed in the outermost layers out of the plurality of oscillators; and a plurality of internal electrodes each disposed between two of the plurality of oscillators. There are provided electrode regions in which the plurality of internal electrodes are arranged such that the number of layers of the internal electrodes in a direction in which the oscillators are stacked gradiently increases from an inner region toward an outer peripheral region of the plurality of oscillators, and ultrasonic waves emitted from the plurality of oscillators are focused toward at least the inner region.
US11322675B2
A device comprises a plurality of electroactive material actuator units arranged as a linear set. Data for controlling the driving of the individual units is provided on a data line, and data line connections are made between each adjacent pair of electroactive material actuator units. The electroactive material actuator units are controlled in dependence on received data from the data line. This provides a reduced complexity of the wiring when multiple actuators need to be addressed and controlled in small application environments.
US11322670B2
A pixel array substrate has a plurality of sub-pixel regions, wherein a pixel structure of an individual sub-pixel region includes a first signal line, a second signal line, a first contact pad, a second contact pad, a light-emitting diode, a first conductive structure, and a flux structure layer. The first contact pad and the second contact pad are respectively electrically connected with the first signal line and the second signal line. The light-emitting diode is disposed on the first contact pad. A portion of the first conductive structure is disposed between the first contact pad and a first electrode of the light-emitting diode. The flux structure layer partially surrounds the first conductive structure and the light-emitting diode. A top portion of the flux structure layer is higher than a top surface of the first electrode and is lower than a bottom surface of a light-emitting layer of the light-emitting diode.
US11322662B2
The optoelectronic device including a radiation emitting semiconductor chip emitting electromagnetic radiation of a first wavelength range from a radiation exit surface, and a conversion element converting electromagnetic radiation of the first wavelength range into electromagnetic radiation of a second wavelength range at least partially and emitting electromagnetic radiation from a light coupling-out surface, wherein the light coupling-out surface of the conversion element is smaller than the radiation exit surface of the semiconductor chip.
US11322657B2
A flip-chip light emitting device includes a transparent substrate, an epitaxial light-emitting structure, a transparent bonding layer interposed between the transparent substrate and the light-emitting structure, and a protective insulating layer disposed over the light-emitting structure and the bonding layer. The transparent bonding layer has a smaller-thickness section that has a first contact surface for the protective insulating layer to be disposed thereover, and a larger-thickness section that has a second contact surface meshing with and bonded to a roughened bottom surface of the light-emitting structure. The first contact surface is smaller in roughness than the second contact surface. A method for producing the device is also disclosed.
US11322654B2
A nitride semiconductor light-emitting element includes an active layer that emits ultraviolet light, a p-type AlGaN-based electron blocking stack body that is located on the active layer and has a structure formed by sequentially stacking a first electron blocking layer, a second electron blocking layer and a third electron blocking layer from the active layer side, and a p-type contact layer located on the electron blocking stack body. An Al composition ratio in the second electron blocking layer is lower than an Al composition ratio in the first electron blocking layer, and an Al composition ratio in the third electron blocking layer decreases from the second electron blocking layer side toward the p-type contact layer side.
US11322649B2
Exemplary devices may include a substrate, a dielectric layer formed on the substrate, a first light source configured to emit first light characterized by a first wavelength, a second light source configured to emit second light characterized by a second wavelength different from the first wavelength, and a third light source configured to emit third light characterized by a third wavelength different from the first wavelength and the second wavelength. The first light source may be natively formed on a first region of the substrate and arranged within a first opening of the dielectric layer. The second light source may be natively formed on a second region of the substrate and arranged within a second opening of the dielectric layer. The third light source may be natively formed on a third region of the substrate and arranged within a third opening of the dielectric layer.
US11322648B2
A method for using a photon source, which includes a semiconductor structure having a first light emitting diode region, a second region including a quantum dot, a first voltage source, and a second voltage source, is provided. The method includes steps of applying an electric field across said first light emitting diode region to cause light emission by spontaneous emission, wherein the light emitted from said first light emitting diode region is absorbed in said second region and produces carriers to populate said quantum dot; and applying a tuneable electric field across said second region to control the emission energy of said quantum dot, wherein the light emitted from the second region exits said photon source.
US11322647B2
In some embodiments, a light emitting structure comprises a layered semiconductor stack comprising a first set of doped layers, a second layer, a light emitting layer positioned between the first set of doped layers and the second layer, and an electrical contact to the first set of doped layers. The first set of doped layers can comprise a first sub-layer, a second sub-layer, and a third sub-layer, where the third sub-layer is adjacent to the light emitting layer. The electrical contact to the first set of doped layers can be made to the second sub-layer. The first, second and third sub-layers can be doped n-type, and an electrical conductivity of the second sub-layer can be higher than an electrical conductivity of the first and third sub-layers. In some cases, the second sub-layer can absorb more light emitted from the light emitting layer than the first or third sub-layers.
US11322635B2
A photodetecting device includes a semiconductor substrate including a one-dimensionally distributed plurality of pixels. The photodetecting device includes, for each pixel, a plurality of avalanche photodiodes arranged to operate in Geiger mode, a plurality of quenching resistors electrically connected in series with the respective avalanche photodiodes, and a signal processing unit arranged to process output signals from the plurality of avalanche photodiodes. Light receiving regions of the plurality of avalanche photodiodes are two-dimensionally distributed for each pixel. Each signal processing unit includes a gate grounded circuit and a current mirror circuit electrically connected to the gate grounded circuit. The gate grounded circuit is electrically connected to the plurality of avalanche photodiodes of the corresponding pixel via the plurality of quenching resistors. The current minor circuit is arranged to output a signal corresponding to output signals from the plurality of avalanche photodiodes.
US11322633B2
An optomechanical system for absorbing light or emitting light, comprising as static frame element, an optical arrangement, a light absorbing/emitting substrate and a shifting mechanism. The shifting mechanism moves at least one layer of the optical arrangement relative to the light absorbing/emitting substrate or vice versa, wherein the movement is through one or more translation element relative to the static frame element in such a way that the transmitted light can be optimally absorbed by the light absorbing/emitting substrate, or that the incident light emitted by the light absorbing/emitting substrate can be optimally transmitted by the optical arrangement. Furthermore, the present invention also relates to a corresponding method for absorbing light or emitting light with the aforementioned optomechanical system.
US11322624B2
The present disclosure is related to a detection apparatus. The detection apparatus may include a gate insulating layer. The gate insulating layer may include at least a first layer and a second layer opposite the first layer. A plurality of protruding structures may be provided on a surface of the first layer facing the second layer and/or a surface of the second layer facing the first layer. The first layer and the second layer of the gate insulating layer may be connected through the protruding structures.
US11322622B2
Embodiments are directed to a flexible high voltage thin film transistor (f-HVTFT) with a center-symmetric circular configuration. The f-HVTFT includes a ring-shaped oxide semiconductor channel, a ring-shaped gate, a ring-shaped source, and a circular drain. The source and gate each have multiple connections to respective electrode pads, enabling stable and identical electrical characteristics and blocking voltage while the f-HVTFT is subject to bending from random directions. The f-HVTFT enables a high blocking voltage over 100 V, on-current over 100 μA, and low off-current of 0.1 pA, which makes it suitable for power management of self-powered wearable electronic systems.
US11322621B2
A thin film transistor includes a gate electrode, an active layer formed of oxide semiconductor material on a substrate, and a gate insulation layer therebetween. The active layer includes a channel region corresponding to the gate electrode, a source region at one side of the channel region, and a drain region at the other side of the channel region. The source region includes a first upper portion and the drain region includes a second upper portion that includes the oxide semiconductor material and Si.
US11322615B2
A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.
US11322610B2
A device includes a laterally diffused MOSFET, which in turn includes n-type source and drain regions in a p-type semiconductor substrate. A gate electrode is located over the semiconductor substrate between the source region and the drain region. An isolation region is laterally spaced apart from the source region, and is bounded by an n-type buried layer and an n-type well region that reaches from a surface of the substrate to the buried layer. A p-type doped region and an n-type doped region are disposed within the isolation region, the p-type doped region and the n-type doped region forming a diode. A first conductive path connects the n-type doped region to the source region, and a second conductive path connects the p-type doped region to the gate electrode.
US11322606B2
A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.
US11322604B2
An object is to provide a technique capable of improving both recovery loss and recovery capability. The semiconductor device includes a base layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the IGBT region and an anode layer of a second conductive type disposed on a front surface side of the semiconductor substrate in the diode region. The anode layer includes a first portion having a lower end located at a same position as a lower end of the base layer or having a lower end located above the lower end of the base layer and a second portion adjacent to the first portion in plan view, and whose lower end is located above the lower end of the first portion.
US11322601B2
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.
US11322598B2
A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region.
US11322593B2
A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide semiconductor layer of the first conductivity type, a second silicon carbide semiconductor layer of a second conductivity type, a first silicon carbide semiconductor region of the first conductivity type, a trench, and a gate electrode on a gate insulating film. Between the gate insulating film and any one among the first silicon carbide semiconductor layer, the second silicon carbide semiconductor layer, and the first silicon carbide semiconductor region is an interface section where a concentration of oxygen varies, the interface section having closer to the gate insulating film than to the any one among the first silicon carbide semiconductor layer, the second silicon carbide semiconductor layer, and the first silicon carbide semiconductor region, a region where a rate of increase of the oxygen included in the interface section is greatest.
US11322590B2
A semiconductor device includes a substrate, a first active fin on the substrate, the first active fin including a first side surface and a second side surface opposing the first side surface, a second active fin on the substrate, the second active fin including a third side surface facing the second side surface and a fourth side surface opposing the third side surface of the second active fin, a first isolation layer on the first side surface of the first active fin, a second isolation layer between the second side surface of the first active fin and the third side surface of the second active fin, a third isolation layer on the fourth side surface of the second active fin and a merged source/drain on the first and second active fins.
US11322586B2
A semiconductor device capable of suppressing the calorific value at the central portion of a wire bonding area is provided. A semiconductor device includes a plurality of IGBT cells in a cell area. An emitter electrode serves as a current path when a plurality of IGBT cells are in conductive state, and is formed to cover a plurality of IGBT cells. A wire is bonded to the emitter electrode. A dummy cell which does not perform a bipolar operation, is formed at least below a central portion of a wire bonding area which is an area at which the wire and the emitter electrode are bonded.
US11322584B2
A semiconductor device includes a semiconductor substrate, an upper diffusion region and a lower diffusion region. The semiconductor substrate has a main surface. The upper diffusion region of a first conductivity type is disposed close to the main surface of the semiconductor device. The lower diffusion region of a second conductivity type is disposed up to a position deeper than the upper diffusion region in a depth direction of the semiconductor substrate from the main surface as a reference, and has a higher impurity concentration than the semiconductor substrate. A diode device is provided by having a PN junction surface at an interface between the upper diffusion region and the lower diffusion region, and the PN junction surface has a curved surface disposed at a portion opposite to the main surface.
US11322578B2
There is provided a semiconductor device capable of improving the performance and/or reliability of the element, by increasing the capacitance of the capacitor, using a capacitor dielectric film including a ferroelectric material and a paraelectric material. The semiconductor device includes first and second electrodes disposed to be spaced apart from each other, and a capacitor dielectric film disposed between the first electrode and the second electrode and including a first dielectric film and a second dielectric film. The first dielectric film includes one of a first monometal oxide film and a first bimetal oxide film, the first dielectric film has an orthorhombic crystal system, the second dielectric film includes a paraelectric material, and a dielectric constant of the capacitor dielectric film is greater than a dielectric constant of the second dielectric film.
US11322576B2
An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.
US11322575B2
A display device includes a substrate including a display area having a first display area and a second display area, and a non-display area extending from the display area; a plurality of first sub-data lines disposed in the first display area; a plurality of second sub-data lines disposed in the second display area to correspond to the plurality of first sub-data lines; a control line including a line portion extending in a direction different from a direction in which the plurality of first sub-data lines and the plurality of second sub-data lines extend; and a plurality of transistors disposed between the plurality of first sub-data lines and the plurality of second sub-data lines and controlled by the control line to connect or disconnect the plurality of first sub-data lines and the plurality of second sub-data lines, thereby reducing power consumption by supplying a data signal only to a driving area during divisional driving.
US11322572B2
An organic light emitting diode display is described which includes a substrate having a display area and a non-display area; a metal layer disposed on the non-display area of the substrate, an insulating layer, a voltage line disposed on the gate insulating layer and receiving a driving voltage, a second voltage line disposed on the gate insulating layer and receiving a low driving voltage, an organic insulating layer, and a cathode electrode disposed on the organic insulating layer. The second voltage line and the cathode electrode are electrically connected to each other through an opening formed in the organic insulating layer, and the first voltage line or the second voltage line is electrically connected to the metal layer through an opening formed in the gate insulating layer.
US11322571B2
A multi-piece substrate integrally having a plurality of product regions each provided with a light-emitting element driven by a current and a blank region adjacent to each of the plurality of product regions is prepared. The current is passed through a cathode pad and an anode pad to inspect the light-emitting element. A plurality of display panels are cut out from the multi-piece substrate so as to respectively correspond to the plurality of product regions. The multi-piece substrate includes a plurality of first test pads disposed in each of the plurality of product regions for inspecting the light-emitting element, and a plurality of second test pads disposed in the blank region for inspecting the light-emitting element. The cathode pad and the anode pad are included in the plurality of first test pads and are not included in the plurality of second test pads.
US11322568B2
Provided are a display panel and a display device having a micro-cavity structure with transflective layers. The display panel includes a first display region, a second display region, a base substrate, a thin film transistor array layer and a pixel definition layer. A pixel density of the first display region is greater than a pixel density of the second display region. The thin film transistor array layer is disposed on a side of the base substrate. The pixel definition layer is disposed on a side of the thin film transistor array layer facing away from the base substrate and includes multiple openings. The second display region includes multiple light emitting regions and multiple light transparent regions. A part of the openings of the pixel definition layer form the light emitting regions. At least one micro-cavity structure is arranged in each of the multiple light transparent regions.
US11322567B2
A display panel, a manufacture method thereof and a display apparatus are provided. The display panel includes a display area, which includes a plurality of pixel units, wherein the pixel units include electroluminescent display devices and pixel drive circuits for driving the electroluminescent display devices to emit light; the electroluminescent display devices include light-emitting devices and virtual light-emitting devices; the light-emitting devices are electrically connected with the pixel drive circuits, while the virtual light-emitting devices are not connected with the corresponding pixel drive circuits; the display area includes a first display area and a second display area; and in the first display area and the second display area, the distribution density of the electroluminescent display devices is the same, and the density of the pixel drive circuits in the second display area is less than that of the pixel drive circuits in the first display area.
US11322558B2
A display panel and an electronic device. The display panel includes a substrate; a thin film transistor layer, the thin film transistor layer is located on the substrate; a light emitting layer, the light emitting layer is located on the thin film transistor layer, the light emitting layer includes a plurality of pixel points; the light emitting layer further includes a plurality of concentrating units, each of the concentrating units being located between two adjacent pixel points, and spaced apart from the pixel points.
US11322556B2
The disclosure is related to creating different functional micro devices by integrating functional tuning materials and creating an encapsulation capsule to protect these materials. Various embodiments of the present disclosure also related to improve light extraction efficiencies of micro devices by mounting micro devices at a proximity of a corner of a pixel active area and arranging QD films with optical layers in a micro device structure.
US11322554B2
A display apparatus includes a lower substrate, first to third light-emitting devices arranged on the lower substrate, where the first to third light-emitting devices each includes a color emission layer, an upper substrate arranged above the lower substrate with the first to third light-emitting devices therebetween, a first insulating layer arranged on a lower surface of the upper substrate in a direction to the lower substrate, the first insulating layer defining a (1-1)st opening corresponding to the first light-emitting device, a (1-2)nd opening corresponding to the second light-emitting device, and a (1-1)st groove connecting the (1-1)st opening to the (1-2)nd opening, a first color quantum dot layer arranged in the (1-1)st opening, and a second color quantum dot layer arranged in the (1-2)nd opening.
US11322551B2
The present disclosure discloses a display panel and a display device. The display device includes a first display area and a second display area, where the first display area includes a plurality of first sub-pixel units, and each of the first sub-pixel units includes a first light emitting device and a driving circuit for driving the first light emitting device to emit light; where the second display area includes a plurality of second sub-pixel units and a plurality of first voltage signal lines, each of the second sub-pixel units includes a second light emitting device, and the first voltage signal lines are directly and electrically connected to anodes of the second light emitting devices.
US11322550B2
An array substrate and a detection method thereof, and a display panel are disclosed. The array substrate includes a plurality of subpixels and a plurality of detection line structures. The plurality of subpixels are arranged in an array of a plurality of rows and a plurality of columns along a first direction and a second direction. Each of the plurality of detection line structures includes at least one first detection line extending along the first direction; adjacent (n)th row and (n+1)th row of subpixels in the array form a subpixel row group, one detection line structure is provided between the (n)th row and (n+1)th row of subpixels in each subpixel row group, and the detection line structure is configured to be connected to the (n)th row and (n+1)th row of subpixels and detect electrical characteristics of first transistors or light-emitting elements in the subpixels.
US11322543B2
Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer.
US11322539B2
There is provided a semiconductor device including: a plurality of bumps on a first semiconductor substrate; and a lens material in a region other than the plurality of bumps on the first semiconductor substrate, wherein a distance between a side of a bump closest to the lens material and a side of the lens material closest to the bump is greater than twice a diameter of the bump closest to the lens material, and wherein the distance between the side of the bump closest to the lens material and the side of the lens material closest to the bump is greater a minimum pitch of the bumps.
US11322527B2
The present invention teaches a pixel unit including thin film transistors (TFTs) and pixel electrodes corresponding to the TFTs. The pixel electrodes are connected to the source electrodes of the TFTs. Each pixel electrode includes multiple arc-shaped electrode units arranged at intervals along an axial direction around a periphery of a corresponding TFT. The electrode units are electrically connected together. The present invention adopts arc-shaped pixels (similar to concentric circles) so that liquid crystal molecules are closer to being isotropic. Then, by having different vertical alignment (VA) TFT designs in the primary pixel region and secondary pixel region and utilizing the differences in W/L and capacitance, different voltage levels for primary pixel electrode and secondary pixel electrode are achieved. The color shift problem is improved and the viewing angle is enhanced.
US11322524B2
A display panel is disclosed, which includes: a substrate including a display region and a border region adjacent to the display region; a first transistor disposed on the border region and including an active layer and a first conducting electrode on the substrate, wherein the first conducting electrode electrically connects to the active layer, and the first conducting electrode extends along a first direction; and a conductive layer disposed on the border region and including an opening, wherein the conductive layer partially overlaps the first conducting electrode in a top view of the border region, wherein a minimum distance from an edge of the opening to the active layer along the first direction is different from a minimum distance from another edge of the opening to the active layer along a second direction, and the first direction is different from the second direction.
US11322521B2
Disclosed is an array substrate, including a substrate, and a first data line, a first insulating layer and a second data line, which are disposed on the substrate in sequence. The first insulating layer is provided with a first via hole. The second data line is connected to the first data line through the first via hole. By configuring double-layer data lines, an area of the data lines is increased, thereby reducing the impedance of the data lines, thereby improving the charging capability of the remote pixels and the display quality of the panel.
US11322520B2
A flexible display device includes: a bendable display panel; a protective layer on a surface of the display panel; and an elastic layer on the first surface of the protective layer. The protective layer has a groove in a first surface thereof, and the elastic layer is in the groove in the protective layer.
US11322512B2
A semiconductor device including a stacked body that includes insulating layers and conductive layers that are alternately stacked, a first film provided inside a recess portion that penetrates through the stacked body, a second film provided on a surface of the first film, a third film provided on a surface of the second film, and a fourth film provided on a surface of the third film. An average concentration of a halogen element per unit area in the third film and the fourth film is lower than an average concentration of the halogen element per unit area at an interface between the third film and the fourth film.
US11322511B2
A semiconductor memory device includes a memory cell array disposed on a source plate; a discharge plate disposed on a bottom surface of the source plate; a source line discharge circuit disposed on a substrate below the discharge plate, and electrically coupling the discharge plate to a ground node in response to a source line discharge control signal; and a discharge path provided between the discharge plate and the source line discharge circuit.
US11322509B2
A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.
US11322506B2
The present invention provides a semiconductor structure for a split gate flash memory cell and a method of manufacturing the same. The split gate flash memory cell provided by the present invention at least includes a select gate and a floating gate formed on the substrate, one side of the select gate is formed with an isolation wall, and the floating gate is on the other side of the isolation wall. An ion implantation region is formed in an upper portion of the substrate below the isolation wall, wherein the ion implantation type of the ion implantation region is different from the ion implantation type of the substrate. The invention also provides a manufacturing method for manufacturing the above-mentioned split gate flash memory cell, and the manufacturing method provided by the invention can be compatible with the existing manufacturing process of the split gate flash memory cell without increasing the process cost and the process complexity. The manufactured split gate flash memory cell can reduce the influence of the channel inversion region on the channel current, thereby improving the characteristics of the channel current of the flash cell and optimizing the device performance.
US11322498B2
An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.
US11322497B1
The present disclosure relates to semiconductor structures and, more particularly, to electronic fuse (e-fuse) cells integrated with a bipolar device and methods of manufacture. The structure includes: a bipolar device comprising a collector region, a base region and an emitter region; and an e-fuse integrated with and extending from the emitter region of the bipolar device.
US11322484B2
The present invention provides a light emitting device comprising a first light emitting portion that emits white light at a color temperature of 6000K or more and a second light emitting portion that emits white light at a color temperature of 3000K or less, which include light emitting diode chips and phosphors and are independently driven. The present invention has an advantage in that a light emitting device can be diversely applied in a desired atmosphere and use by realizing white light with different light spectrums and color temperatures. Particularly, the present invention has the effect on health by adjusting the wavelength of light or the color temperature according to the circadian rhythm of humans.
US11322483B1
A semiconductor structure includes a peripheral circuit, a first three-dimensional memory array overlying the peripheral circuit and including a first alternating stack of first insulating layers and first electrically conductive layers containing first word lines and first select lines, and first memory stack structures vertically extending through the first alternating stack, and a second three-dimensional memory array overlying the first three-dimensional memory array and including a second alternating stack of second insulating layers and second electrically conductive layers containing second word lines and second select lines, and second memory stack structures vertically extending through the second alternating stack. The peripheral circuit includes a first word line driver circuit having first word line driver output nodes electrically connected to at least some of the first word lines and at least some of the second word lines, and each first word line is electrically connected to a respective second word line.
US11322480B2
A semiconductor memory device includes a substrate that has a first main surface and a second main surface opposite to the first main surface, a first semiconductor chip which is mounted on the first main surface and includes a first register, a plurality of first input/output (IO) terminals, and a first circuit connected between the first IO terminals and the first register, and a second semiconductor chip which is mounted on the second main surface and includes a second register, a plurality of second input/output (IO) terminals, and a second circuit connected between the second IO terminals and the second register. The second circuit is connected to the second IO terminals through input lines and to the second register through output lines, and is configured to change a connection path between the input lines and the output lines in response to a connection change command.
US11322478B2
A semiconductor device includes a wiring substrate and multiple semiconductor chips mounted on the wiring substrate by flip chip bonding with a resin being interposed between the wiring substrate and the semiconductor chips. The wiring substrate includes a chip mounting region in which the semiconductor chips are arranged in a matrix, and a resin injection region protruding from an end of the chip mounting region. The outer edge of the wiring substrate in the chip mounting region is positioned inward of the outer edge of the semiconductor chips arranged in the matrix. The outer edge of the wiring substrate in the resin injection region protrudes outward of the outer edge of the semiconductor chips arranged in the matrix.
US11322470B2
A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, an insulating layer contacting the second surface of the interconnect structure wherein the insulating layer has a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface, at least one optical chip over the fourth surface of the insulating layer and electrically coupled to the interconnect structure, and a molding compound over the first surface of the interconnect structure.
US11322464B2
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of bond pad structures over an interconnect structure on a front-side of a semiconductor body. The plurality of bond pad structures respectively have a titanium contact layer. The interconnect structure and the semiconductor body are patterned to define trenches extending into the semiconductor body. A dielectric fill material is formed within the trenches. The dielectric fill material is etched to expose the titanium contact layer prior to bonding the semiconductor body to a carrier substrate. The semiconductor body is thinned to expose the dielectric fill material along a back-side of the semiconductor body and to form a plurality of integrated chip die. The dielectric fill material is removed to separate the plurality of integrated chip die.
US11322463B2
A packaged antenna circuit structure suitable for 5G use includes a shielding layer, an electronic component, conductive pillars, a first insulation layer, a first stacked structure, an antenna structure, and a second stacked structure. The shielding layer defines a groove to receive the electronic component. The conductive pillars on the shielding layer surround the groove. The first insulation layer covers the shielding layer, the electronic component, and the conductive pillars. The first stacked structure is stacked on a side of the first insulation layer and includes a ground line connecting to the conductive pillars. The antenna structure is stacked on a side of the first stacked structure away from the first insulation layer and connected to the electronic component by the first stacked structure. The second stacked structure is stacked on a side of the first insulation layer away from the first stacked structure.
US11322451B2
A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.
US11322449B2
Structures and formation methods of chip packages are provided. The method includes disposing a semiconductor die over a carrier substrate. The method also includes disposing an interposer substrate over the carrier substrate. The interposer substrate has a recess that penetrates through opposite surfaces of the interposer substrate. The interposer substrate has interior sidewalls surrounding the semiconductor die, and the semiconductor die is as high as or higher than the interposer substrate. The method further includes forming a protective layer in the recess of the interposer substrate to surround the semiconductor die. In addition, the method includes removing the carrier substrate and stacking a package structure over the interposer substrate.
US11322435B2
A package substrate according to an aspect of the disclosure includes a substrate body, and a first power trace pattern and a first ground trace pattern disposed on a first surface of the substrate body. The first power trace pattern has a parent power line portion and at least one child power line portion branched from the parent power line portion, and the first ground trace pattern has a parent ground line portion and at least one child ground line portion branched from the parent ground line portion. At least a portion of the first power trace pattern is disposed to surround at least a portion of the first ground trace pattern, and at least a portion of the first ground trace pattern is disposed to surround at least a portion of the first power trace pattern.
US11322432B2
A semiconductor module includes: an insulating heat dissipation sheet; a semiconductor device provided on the heat dissipation sheet; a lead frame including a lead terminal and a die pad which are formed integrally; a wire connecting the lead frame to the semiconductor device and constituting a main current path; and a mold resin scaling the heat dissipation sheet, the semiconductor device, the lead frame and the wire, wherein the lead terminal is led out from the mold resin, the heat dissipation sheet is in direct contact with an undersurface of the die pad, and the wire is bonded to the die pad directly above a contact part provided between the die pad and the heat dissipation sheet.
US11322428B2
A semiconductor device package includes a substrate, a first semiconductor die, a conductive via, a first contact pad and a second contact pad. The substrate includes a first surface, and a second surface opposite to the first surface, the substrate defines a cavity through the substrate. The first semiconductor die is disposed in the cavity, wherein the first semiconductor die includes an active surface adjacent to the first surface, and an inactive surface. The conductive via penetrates through the substrate. The first contact pad is exposed from the active surface of the first semiconductor die and adjacent to the first surface of the substrate. The second contact pad is disposed on the first surface of the substrate, wherein the second contact pad is connected to a first end of the conductive via.
US11322427B2
A chip on film package including a chip and a flexible film. The chip includes bumps disposed on the chip and is mounted on the flexible film. The flexible film includes first vias, second vias, upper leads and lower leads. The first vias and the second vias penetrate the flexible film and are arranged on two opposite sides of a reference line respectively. A distance between one of the first vias and one of the second vias, which are closer to a first side of the chip, is longer than that between another one of the first vias and another one of the second, which are further from the first side. The upper leads are disposed on the upper surface connected between the vias and the bumps. The lower leads are disposed on the lower surface and connected to the vias.
US11322423B2
An electronic control device includes: a board; a heat generating component mounted on the board; a heat conductive sheet thermally coupled to one surface of the heat generating component located on a side opposite to the board side; and a cooling mechanism thermally coupled to the heat conductive sheet. The heat conductive sheet includes a folded structure having a plurality of folded-back portions and a plurality of connection portions provided between the folded-back portions, and the plurality of folded-back portions of the heat conductive sheet is thermally coupled to each of the heat generating component and the cooling mechanism.
US11322421B2
Provided is a package structure including a composite wafer, a plurality of dies, an underfill, and a plurality of dam structures. The composite wafer has a first surface and a second surface opposite to each other. The composite wafer includes a plurality of seal rings dividing the composite wafer into a plurality of packages; and a plurality of through holes respectively disposed between the seal rings and penetrating through the first and second surfaces. The dies are respectively bonded onto the packages at the first surface by a plurality of connectors. The underfill laterally encapsulates the connectors. The dam structures are disposed on the first surface of the composite wafer to separate the underfill from the through holes.
US11322420B2
The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
US11322416B2
A pattern of core material is formed on a wafer to include core features that have a critical dimension. A trim amount indicates an average amount of thickness to be removed from vertically oriented surfaces of the core features. A trim profile indicates how much variation in removal of thickness from vertically oriented surfaces of the core features is to be applied as a function of radial location on the wafer. A first set of data correlates the trim amount to one or more plasma trim process parameters. A second set of data correlates the trim profile to one or more plasma trim process parameters. Based on the trim amount, trim profile, and first and second sets of data, a set of plasma trim process parameters to achieve the trim amount and trim profile on the wafer is determined and a corresponding plasma trim process is performed on the wafer.
US11322409B2
Provided is a method of manufacturing a semiconductor device including providing a semiconductor substrate, and forming an epitaxial stack on the semiconductor substrate. The epitaxial stack comprises a plurality of first epitaxial layers interposed by a plurality of second epitaxial layers. The method further includes patterning the epitaxial stack and the semiconductor substrate to form a semiconductor fin, recessing a portion of the semiconductor fin to form source/drain spaces; and laterally removing portions of the plurality of first epitaxial layers exposed by the source/drain spaces to form a plurality of cavities. The method further includes forming inner spacers in the plurality of cavities, performing a treatment process to remove an inner spacer residue in the source/drain spaces, forming S/D features in the source/drain spaces, and forming a gate structure engaging the semiconductor fin.
US11322408B2
A method of forming a semiconductor structure includes forming a semiconductor layer stack including a substrate and a nanosheet channel stack including alternating layers of a sacrificial material and a semiconducting material providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the semiconductor layer stack, forming a liner on sidewalls of the vertical fins, and forming a sacrificial epitaxial layer over the substrate surrounding the vertical fins. The method further includes replacing the sacrificial epitaxial layer with a first dielectric layer, removing the liner to form air gaps between the first dielectric layer and sidewalls of the vertical fins, and forming a second dielectric layer in the air gaps between the first dielectric layer and sidewalls of the vertical fins. The first and second dielectric layers provide shallow trench isolation regions surrounding sidewalls of the vertical fins below the nanosheet channel stack.
US11322402B2
A semiconductor device includes a base structure including a lower level via and a lower level dielectric layer, a conductive pillar including an upper level line and an upper level via disposed on the lower level via, and a protective structure disposed between the lower level via and the upper level line. The protective structure includes a material having an etch rate less than or equal to that of the lower level via.
US11322399B2
Semiconductor structure and method for forming the semiconductor structure are provided. An exemplary method includes: providing a substrate, including a first region and a second region; forming a gate structure over the substrate; forming a first interlayer dielectric layer over the substrate; forming a plurality of metal plugs in the first interlayer dielectric layer; forming a second interlayer dielectric layer over the first interlayer dielectric layer; forming a first via in the first region exposing a metal plug, and a second via in the second region exposing the first interlayer dielectric layer by etching the second interlayer dielectric layer; fully filling the first via with a first tungsten layer; forming an adhesion layer over the first tungsten layer, the second interlayer dielectric layer, and a sidewall and bottom of the second via; and fully filling the second via with a second tungsten layer.
US11322397B2
In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.
US11322396B2
A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.
US11322394B2
A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.
US11322382B2
A wafer supporting structure according to an aspect of the present disclosure includes a supporting body, a first strained layer disposed on an upper portion of the supporting body and having a first thermal expansion rate, and a second strained layer disposed on a lower portion of the supporting body and having a second thermal expansion rate different from the first thermal expansion rate. One of the first strained layer and the second strained layer is configured to receive a working wafer thereon.
US11322379B2
A wafer storage box, wafer transfer device and wafer storage box and transfer assembly. The wafer storage and transfer assembly includes a chassis which is capable of translating or rotating, a sliding shaft, connecting levers, arms and at least two positioning sidewall. The chassis includes a groove. The sliding shaft can translate along the groove. The connecting levers are connected to the sliding shaft. Each arm extends from a connecting lever. The two positioning sidewall are respectively arranged on opposite sides of the chassis. Each positioning sidewall includes tracks accommodating the pins of connecting levers. The width of each of the tracks reduces from the front end of the positioning sidewall to the back end of the positioning sidewall. The wafer storage and transfer assembly can vacuum adsorb several wafers to achieve high efficiency of wafer storing and transferring.
US11322377B2
A stacking structure is applicable to manufacturing a circuit board. The stacking structure includes a transferring layer and a dielectric layer disposed on the transferring layer. The transferring layer includes a substrate and a thin film disposed on the substrate and having a plurality of recess structures thereon. The recess structures are connected as a single piece and bottom portions and top portions of the recess structures are configured to arrange in a staggered manner to form a multi-dimensional arrangement. At least a portion of the dielectric layer being is located in the recess structures, such that the dielectric layer is at least embedded with the recess structures.
US11322373B2
A liquid processing apparatus according to an embodiment includes a holding unit, a driving unit, a shaft, and a nozzle. The driving unit rotates the substrate and the holding unit that horizontally holds the substrate. The shaft is extended along an axial direction of a rotation axis. The nozzle includes a base that is attached to an upper end of the shaft, and a liquid supply unit that is extended from the base to a radial-direction outer side of the substrate and includes discharge ports formed to discharge the liquid toward a lower surface of the substrate. The shaft and the base are configured to include a discharge passage that is formed along the axial direction to discharge the liquid discharged toward the lower surface of the substrate. The base includes a concave portion that is concave downward to cause the liquid to flow toward the discharge passage.
US11322372B2
A fluid supply device includes a condenser, a tank that stores the fluid, a pump that pressure-feeds the fluid toward a processing chamber, a main pipe connecting the tank and the pump and transferring the liquid stored in the tank to the pump using a weight of the liquid, and a discharging pipe that is connected to the main pipe at a lowest position of the main pipe at one end, is opened to the atmosphere at the other end, and vaporizes and discharges the liquid in the tank and the main pipe to the outside. The discharging pipe is formed so that, after the liquid in the tank and the main pipe is fully discharged, a liquid pool that separates a space on the atmosphere side and a space on the main pipe side of the discharging pipe is temporarily produced in the discharging pipe.
US11322365B2
There is provided a substrate processing method including: reducing an oxide of a ruthenium film by supplying a hydrogen-containing gas to a substrate including the ruthenium film; etching the ruthenium film by supplying an oxygen-containing gas to the substrate so as to oxidize the ruthenium film; and repeating, multiple times, a cycle including reducing the oxide of the ruthenium film and etching the ruthenium film.
US11322360B2
A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing the die on a substrate; disposing a molding surrounding the die; removing a portion of the molding to expose a sidewall of the sacrificial layer, wherein a top surface of the molding is at a level substantially same as the top surface of the die; and removing the sacrificial layer from the die.
US11322349B2
A TTV of the silicon carbide substrate is less than or equal to 3 μm. The first main surface includes a first central region surrounded by a square having each side of 90 mm. An intersection of diagonal lines of the first central region coincides with a center of the first main surface. The first central region is constituted of nine square regions each having each side of 30 mm. A maximum LTV among the nine square regions is less than or equal to 1 μm. An arithmetic mean roughness Sa in a second central region is less than or equal to 0.1 nm, the second central region being surrounded by a square centering on the intersection and having each side of 250 μm.
US11322348B2
A multi-function equipment implements a method of fabricating a thin film. The multi-function equipment according to the invention includes a reaction chamber, a plasma source, a plasma source power generating unit, a bias electrode, an AC (Alternating Current) voltage generating unit, a DC (Direct current) bias generating unit, a metal chuck, a first precursor supply source, a second precursor supply source, a carrier gas supply source, an oxygen supply source, a nitrogen supply source, an inert gas supply source, an automatic pressure controller, and a vacuum pump.
US11322344B2
The subject of the invention is a method and device for reducing contamination in a plasma reactor, especially contamination by lubricants, particularly for plasma processing of materials. The method is based on the fact that the contaminated gas pumped out of at least one reduced pressure vacuum chamber in the form of a plasma lamp (LA1, LA2, LA3) is purified in at least one purifying plasma lamp (LA01, LA02, LAH, LAE), in which a glow discharge is initiated between the anodes of the purifying plasma lamp (A01, A02) and the cathodes of the purifying plasma lamp (K01, K02), favorably particles of lubricants are cracked and partially polymerized, while processed heavy particles of lubricants are collected in a buffer tank (ZB) and then discharged outside the pumping system. The device contains at least one reduced pressure vacuum chamber in the form of a plasma lamp (LA1, LA2, LA3), it is connected to at least one purifying plasma lamp (LA01, LA02, LAH, LAE) with a buffer tank (ZB) connected to a vacuum pump (PP). The vacuum tube connecting the plasma lamps (LA1, LA2, LA3) with the purifying plasma lamp (LA01, LA02, LAH, LAE)) is equipped with a dosing valve (V) for the gaseous admixture medium (MD) to plasma lamps (LA1, LA2, LA3), from which radiation (R1, R2, R3) is directed to the processed material (OM).
US11322338B2
A method for modifying magnetic field distribution in a deposition chamber is disclosed. The method includes the steps of providing a target magnetic field distribution, removing a first plurality of fixed magnets in the deposition chamber, replacing each of the first plurality of fixed magnets with respective ones of a second plurality of magnets, performing at least one of adjusting a position of at least one of the second plurality of the magnets, and adjusting a size of at least one of the second plurality of magnets, adjusting a magnetic flux of at least one of the second plurality of magnets, measuring the magnetic field distribution in the deposition chamber, and comparing the measured magnetic field distribution in the deposition chamber with the target magnetic field distribution.
US11322333B2
A scintillator assembly including an entrance surface for receiving charged particles into the scintillator assembly, the charged particles including first charged particles at a first energy level and second charged particles at a second energy level. A first scintillator structure configured for receiving the first charged particles and generating a corresponding first signal formed of first photons with a first wavelength of λ1, a second scintillator structure configured for receiving the second charged particles and generating a corresponding second signal of second photons with a second wavelength of λ2, and an emitting surface for egress of a combined signal from the scintillator assembly, the combined signal including the first and second photons, and at least one beam splitter for receiving the combined signal and separating the combined signal to first and second photons.
US11322332B2
The present invention relates to an apparatus and method for analyzing the energy of backscattered electrons generated from a specimen. The apparatus includes: an electron beam source (101) for generating a primary electron beam; an electron optical system (102, 105, 112) configured to direct the primary electron beam to a specimen while focusing and deflecting the primary electron beam; and an energy analyzing system configured to detect an energy spectrum of backscattered electrons emitted from the specimen. The energy analyzing system includes: a Wien filter (108) configured to disperse the backscattered electrons; a detector (107) configured to measure the energy spectrum of the backscattered electrons dispersed by the Wien filter (108); and an operation controller (150) configured to change an intensity of a quadrupole field of the Wien filter (108), while moving a detecting position of the detector (107) for the backscattered electrons in synchronization with the change in the intensity of the quadrupole field.
US11322330B2
The apparatus is for use with an electron microscope, a sample, a source of high pressure gas and a vacuum pump system. The apparatus includes a holder part a body part and a Joule-Thomson refrigerator. The holder part is adapted to receive the sample and adapted to present the sample to the microscope for inspection in use. The body part defines a cavity, the cavity being evacuated by the vacuum pump system for use. The refrigerator is disposed within the cavity and thermally-coupled to the holder part, the refrigerator being coupled in use to the source of high pressure gas to maintain the sample at about a predetermined temperature.
US11322328B2
Arc Fault Circuit Interrupter (AFCI), Ground Fault Circuit Interrupter (GFCI) or AF/GF circuit breakers which may optionally have relatively small or compact bodies that have shaped neutral busbars and/or load terminals with an arm that extends through a window of a current transformer in a circuit breaker housing. The neutral busbar and/or load terminal can have a rigid or semi-rigid shaped body with a first segment that extends through the window of the current transformer and a second segment that extends behind the first segment about a printed circuit board. A plug-on, pigtail or bolt-on neutral can engage an electrical pad of the neutral busbar.
US11322326B1
An elastic contact plate structure of an electromagnetic relay includes at least one elastic plate assembly and at least one contact structure. The elastic plate assembly includes first, second, third and fourth plates sequentially stacked on one another, and first plate has a first convex arc bent portion with first mounting hole formed at an end; second plate has second convex arc bent portion with second mounting hole formed at an end. Third plate has third mounting hole formed at an end; fourth plate has fixed section, which has fourth mounting hole, and elastic section. Contact structure is passed and fixed into first, second, third, and fourth mounting hole. Therefore, the force receiving strength of elastic contact plate structure shows a positive linear change with the deformation, and the stability of connecting or disconnecting elastic contact plate structure is improved significantly, so as to achieve a better electrical performance.
US11322317B2
A housing for accommodating an electrical device is provided. A bolt for holding a bus bar electrically connected to the electrical device includes a threaded shaft and a base. The housing includes a first housing configured to hold the electrical device and a bolt housing. The bolt housing includes an upper wall having a U-shaped slot. A resilient tab is disposed on a bottom wall and beneath the U-shaped slot. A pair of slits are disposed on each side of the resilient tab, wherein the threaded shaft is dimensioned to be seated within the U-shaped slot, and wherein the resilient tab presses the base against an undersurface of the upper wall so as to hold the bolt in an upright position relative to the upper wall.
US11322310B2
A photochemical electrode includes: an electrically conductive layer; and a photoexcitation material layer provided over the electrically conductive layer and including a photoexcitation material, wherein the photoexcitation material layer is one of a first photoexcitation material layer in which a potential of the conduction band minimum decreases from a second surface opposite to a first surface on the side of the electrically conductive layer toward the first surface and a second photoexcitation material layer in which a potential of the valence band maximum decreases from the second surface toward the first surface.
US11322308B2
According to an embodiment, a capacitor includes a conductive substrate, a conductive layer and a dielectric layer. The conductive substrate has a first main surface and a second main surface. The first main surface includes sub-regions. Each sub-region is provided with recesses or projections each having a shape extending in one direction and arranged in a width direction thereof. One or more of the sub-regions and another one or more of the sub-regions are different from each other in a length direction of the recesses or protrusions. The conductive layer covers sidewalls and bottom surfaces of the recesses or sidewalls and top surfaces of the projections. The dielectric layer is interposed between the conductive substrate and the conductive layer.
US11322307B2
A multilayer ceramic capacitor includes a third segregation by each of metal elements of a first segregation and a second segregation is provided at each of a first corner region in which an end in a length direction in which the first segregation is provided overlaps an end in a width direction in which the second segregation is provided in a first internal electrode layer, and a second corner region in which an end in the length direction in which the second segregation is provided overlaps an end in the width direction in which the second segregation is provided in a second internal electrode layer.
US11322295B2
A coil component includes a magnetic body portion that includes metallic particles and a resin material, a coil conductor that is embedded in the magnetic body portion, and a first outer electrode and a second outer electrode each of which is electrically connected to the coil conductor. At least a portion of an outer layer of the magnetic body portion forms an electrically conductive layer that includes a second metallic material having a specific resistance lower than a specific resistance of a first metallic material forming the metallic particles. The electrically conductive layer includes a first electrically conductive layer that is electrically connected to the first outer electrode and a second electrically conductive layer that is electrically connected to the second outer electrode. The first electrically conductive layer and the second electrically conductive layer are electrically isolated from each other.
US11322286B2
The invention describes a split transformer assembly (1) comprising a first partial assembly (10) comprising a primary winding arrangement (10W) shaped to accommodate a first core half (10C); a second partial assembly (20) comprising a secondary winding arrangement (20W) shaped to accommodate a second core half (20C); and wherein the first partial assembly (10) is realized for mounting on one side of a circuit board (3) and the second partial assembly (20) is realized for mounting on the opposite side of the circuit board (3) such that the core halves (10C, 20C) of the partial assemblies (10, 20) are completely isolated by the material of the circuit board (3). The invention further describes a switching converter circuit arrangement (2), and a method of assembling a split transformer (1).
US11322282B2
An electromagnetic actuator includes an essentially cylindrical pole tube, an armature situated radially within the pole tube, and an electromagnetic coil situated radially outside of the pole tube, the pole tube including a first axial end area, a second axial end area, and an outer recess, which extends in the circumferential direction, in proximity to the first axial end area on an outer side of the pole tube. On an inner side, the pole tube includes an inner recess that extends in the circumferential direction and whose axial extension is smaller than an axial extension of the outer recess and that is situated approximately at the height of an edge area of the outer recess pointing away from the second axial end area viewed in the axial direction.
US11322276B2
A wire harness including: a wire; a cover that covers the wire; and a braid made of resin that covers the wire, wherein: the wire protrudes from a first end of the cover to an outside of the cover, and a space is formed between the wire and the first end, and the braid is provided at a position that overlaps the first end of the cover in a longitudinal direction of the wire and is exposed to the outside of the cover.
US11322272B2
The present disclosure provides a coiled cord capable of increasing the length of a cable while preventing a winding diameter of the coiled cord in a plane orthogonal to the direction in which the coiled cord is extended and contracted in a natural state from increasing. A first exemplary aspect is a coiled cord around which a cable is wound, the cable being capable of being freely extended and contracted, the coiled cord including: a first layer in which the cable is wound from an inner side of the coiled cord to an outer side thereof in a radial direction, and a second layer in which the cable is wound from the outer side of the coiled cord to the inner side thereof in the radial direction, in which the first and the second layers are continuously connected to each other.
US11322265B2
According to some embodiments, a system for widening and densifying a scrape-off layer (SOL) in a field reversed configuration (FRC) fusion reactor is disclosed. The system includes a gas box at one end of the reactor including a gas inlet system and walls of suitable heat bearing materials. The system further includes an exit orifice adjoining the gas box, wherein the exit orifice has a controllable radius and length to allow plasma to flow out from the gas box to populate the SOL with the plasma. The system may also include fusion products, which decrease in speed in the plasma in the SOL, allowing energy to be extracted and converted into thrust or electrical power and further allowing ash to be extracted to reduce neutron emissions and maintain high, steady-state fusion power.
US11322261B2
A telehealth device includes a memory, a processor, one or more cameras, and a communication interface for relaying a data communication between a remote mobile device of a medical practitioner and the telehealth device used by a user over a communication network in a single communication channel. The processor may be configured to receive measurements of the user from one or more medical sensors, to collect medical information about the user, to overlay multiple layers of the collected medical in about the user including the received measurements over the data communication, to send the data communication over the communication network with the overlaid multiple layers for display on the remote mobile device of the medical practitioner, to execute commands sent from the remote mobile device in the single communication channel, so as to allow, based on the commands, the medical practitioner to remotely control the telehealth device.
US11322257B2
An intelligent diagnosis system for diagnosing one or more health conditions is provided. The system comprises a plurality of preceptors configured to receive an initial set of parameters from a user, wherein the initial set of parameters represent at least one symptoms related to a health condition presented in a patient. The intelligent system further includes a cognition module coupled to the plurality of preceptors and configured to identify a first set of probable conditions based on the initial set of parameters and generate a set of reactions in response to the first set of probable conditions. The intelligent diagnosis system further includes a reaction module coupled to the cognition module and configured to select one or more reactions from the set of reactions and present the one or more reactions to the user. The cognition module is further configured to iteratively narrow down the initial set of probable conditions to a final set of probable conditions based on a final set of input parameters; wherein the final set of probable conditions is used to identify and diagnose the one or more health condition presented in the patient.
US11322255B2
A system for self-fulfillment of an alimentary instruction set based on vibrant constitutional guidance using artificial intelligence. The system includes a computing device designed and configured to receive training data. The computing device is further configured to record at least a biological extraction from a user and generate a diagnostic output. The computing device is further configured to generate a self-fulfillment instruction set utilizing the diagnostic output. The computing device is further configured to receive a user entry containing a completed alimentary self-fulfillment action. The computing device is further configured to update the self-fulfillment instruction set as a function of an alimentary self-fulfillment action.
US11322244B2
The present invention is an Deep Neural Network based technology relating to diagnosis of Anisomelia, also referred to as Leg Length Discrepancy (LLD). This invention is a system and method, which comprises of a diagnosis device referred to as the “LEG-Minder” device that is typically installed in a diagnosis center setting, and diagnoses for LLD on the basis of a neural network model with patient's leg photos or x-rays thereof; and a neural network learning server referred to as the “LEGislator” which is connected to the Internet and performs Deep Neural Network (DNN) learning, on the individual LLD databases generated by a plurality of the “LEG-Minder” device(s). In particular, the present invention relates to a technology in which patient's leg photos (or x-rays) and the corresponding diagnostic result data are acquired in each diagnosis center and then individually uploaded to the LEGislator; and then, on the basis of the uploaded information the LEGislator performs DNN learning to generate an upgraded neural network model, which is then disseminated to the “LEG-Minder” device(s), providing them the latest learnings, which subsequently helps in improving the diagnosis accuracy. This invention optimizes the diagnosis environment of the diagnosis center for Anisomelia.
US11322243B2
An improved method and system for identifying and displaying related images obtained during an examination is disclosed. Each image includes both pixel data, corresponding to the image to be displayed, and location information, defining a relationship between the pixel data and a reference point. During a review of the images, a physician may identify an abnormality or particular region of interest in one image. The location information corresponding to the position identified by the physician within the image is obtained from the image file. Having identified location information for a particular location on the first image, the system analyzes the location information corresponding to the pixel data for each of the other stored images to identify any other image that intersects the identified location. All images that intersect the identified location may then be displayed adjacent to the first image for inspection by the physician.
US11322237B1
A healthcare provider user interface for treatment option and authorization is disclosed herein. In embodiments, a healthcare provider device includes a display coupled to one or more processors. The display includes a graphical user interface comprising one or more input interface display pages and one or more output interface display pages. The one or more input interface display pages may include one or more input boxes configured to receive information including patient demographic and physiological information, insurance information, past treatments, and one or more medical diagnoses. The one or more output interface display pages may include a treatment list generated based on the received information and a prior authorization form configured to receive one or more prior authorization input fields.
US11322230B2
A system and method for receiving and processing patient medical information for integration into third party applications, including patient medical records, billing systems, and reporting systems. The method may be implemented as a software as a service application separate from the middle tier application server or other computer system implementing the third party application. In addition, the system may operate in a stateless environment in which the computer system running the SaaS application may not retain the patient medical information or data relating to a patient history interview state.
US11322225B2
The present disclosure provides systems and methods for determining effects of genetic variants on selection of polyadenylation sites (PAS) during polyadenylation processes. In an aspect, the present disclosure provides a polyadenylation code, a computational model that can predict alternative polyadenylation patterns from transcript sequences. A score can be calculated that describes or corresponds to the strength of a PAS, or the efficiency in which it is recognized by the 3′-end processing machinery. The polyadenylation model may be used, for example, to assess the effects of anti-sense oligonucleotides to alter transcript abundance. As another example, the polyadenylation model may be used to scan the 3′-UTR of a human genome to find potential PAS.
US11322224B2
The present disclosure provides methods for determining the ploidy status of a chromosome in a gestating fetus from genotypic data measured from a mixed sample of DNA comprising DNA from both the mother of the fetus and from the fetus, and optionally from genotypic data from the mother and father. The ploidy state is determined by using a joint distribution model to create a plurality of expected allele distributions for different possible fetal ploidy states given the parental genotypic data, and comparing the expected allelic distributions to the pattern of measured allelic distributions measured in the mixed sample, and choosing the ploidy state whose expected allelic distribution pattern most closely matches the observed allelic distribution pattern. The mixed sample of DNA may be preferentially enriched at a plurality of polymorphic loci in a way that minimizes the allelic bias, for example using massively multiplexed targeted PCR.
US11322223B2
The present disclosure includes methods and apparatuses comprising a memory component having an independent structure and including an array of memory cells with associated decoding and sensing circuitry of a read interface, a host device coupled to the memory component through a communication channel, a JTAG interface in the array of memory cells, and an additional register in the JTAG interface. The additional register is configured to store a page address associated with the array of memory cells, the memory component is configured to load the page address at the power-on of the apparatus, and the host device is configured to perform a read sequence at the page address.
US11322220B2
A memory system is provided. In the memory system, a memory controller transmits a write enable signal and a data strobe signal to a flash memory device, a command or an address is transmitted at a rising edge or a falling edge of the write enable signal through a data line in a single data rate (SDR) scheme, and input data is transmitted at each of a rising edge and a falling edge of the data strobe signal through the data line in a double data rate (DDR) scheme. The memory controller includes a parity signal generation unit configured to receive the write enable signal transmitted in the DDR scheme and output a parity signal by generating a first parity bit for the input data. The flash memory device includes a bit error detection unit configured to receive the parity signal output from the memory controller, generate a second parity bit for the input data received by the flash memory device, and determine whether a bit error has occurred to the input data by performing a parity check.
US11322218B2
Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.
US11322217B2
A track and hold circuit includes a signal input terminal, a clock input terminal, an output terminal, a transistor, and a bootstrapping circuit with a transformer. The transistor includes a source, a drain, and a gate, where the source is coupled to the signal input terminal, and the drain is coupled to the output terminal. The transformer includes a primary winding coupled to the clock input terminal, and a secondary winding. The secondary winding is coupled between the source and the gate to control a gate-source voltage of the transistor.
US11322215B1
A one-time programmable (OTP) memory device includes a first memory cell, which further includes a first source line extending along a first direction on a substrate, a first word line extending along the first direction on one side of the first source line, a second word line extending along the first direction on another side of the first source line, a first diffusion region extending along a second direction adjacent to two sides of the first word line and the second word line, and a first metal interconnection connecting the first word line and the second word line.