US09246172B2
A cathode material for a lithium ion secondary battery includes an oxide represented by a composition formula Li2-xMIIyM(Si,MB)O4, wherein MII represents a divalent element; M represents at least one element selected from the group consisting of Fe, Mn, Co and Ni; and MB represents, as an optional component, an element substituted for Si to compensate for a difference between an electric charge of [Li2]2+ and an electric change of [Li2-xMIIy]n+ as needed. In the composition formula representing the oxide, x and y are −0.25
US09246163B2
Provided is a metal oxygen battery 1 including a positive electrode 2 having oxygen as an active material, a negative electrode 3 having metallic lithium as an active material, and an electrolyte layer 4 interposed between the positive electrode 2 and negative electrode 3. The positive electrode 2 contains oxygen storage material including mixed crystal of hexagonal composite metal oxide expressed by the general formula AxByOz (in which, A is one type of metal selected from a group of Y, Sc, La, Sr, Ba, Zr, Au, Ag, Pt, Pd, B is one type of metal selected from a group of Mn, Ti, Ru, Zr, Ni, Cr, and x=1, 1≦y≦2, 1≦z≦7, provided that a case where both A and B are Zr is excluded) and one or more non-hexagonal composite metal oxide expressed by the general formula AxByOz.
US09246156B2
A battery pack for an electric bicycle is disclosed. In one embodiment, the battery pack includes i) a lower case having a top, a bottom and an interior space formed between the top and bottom and ii) a battery cell placed in the interior space of the lower case, wherein the battery cell has first and second surfaces opposing each other, and wherein the first surface of the battery cell is closer to the bottom of the lower case than the second surface of the battery cell. The battery pack may further include i) a protection circuit board mounted on the second surface of the battery cell and placed in the interior space of the lower case, ii) an upper case formed over the top of the lower case and iii) a separator case formed between the protection circuit board and the upper case.
US09246155B2
Disclosed is a secondary battery having improved safety against puncture and collapse. The secondary battery includes an electrode assembly including a first electrode, a second electrode, and a separator between the first electrode and the second electrode, a case receiving the electrode assembly, a cap plate coupled to the case, and a support plate electrically coupled to the first and second electrodes of the electrode assembly, the support plate being disposed between the electrode assembly and the case.
US09246153B2
A secondary battery is disclosed. In one aspect, the battery includes a bare cell having a substantially prismatic shape, a first terminal located in a first region of a first surface of the bare cell and a second terminal located in a second region of the first surface of the bare cell. The battery also includes a first insulation tape located between the bare cell and the first terminal, wherein the first insulation tape covers the first surface of the bare cell, and second and third surfaces of the bare cell extending in a direction that crosses the first surface of the bare cell. The battery also includes a second insulation tape located between the first insulation tape and the first terminal.
US09246152B2
Disclosed herein is a middle or large-sized battery pack having a plurality of electrically connected battery modules, the middle or large-sized battery pack including an electrode terminal connecting device, wherein the electrode terminal connecting device includes a conductive connecting member coupled to electrode terminals of the battery modules to electrically connect the electrode terminals of the battery modules to each other and a shut-off cutter mounted to the conductive connecting member to shut off the circuit of the conductive connecting member when impact is applied to the battery pack in the longitudinal direction of the battery pack.
US09246151B2
An electrical connection assembly is provided to electrically connect with at least one electrical contact of an electronic apparatus. The electrical connection assembly includes an insulating casing, a circuit board and a resilient conductive element. An inner space is defined in the insulating casing, and at least one opening is defined on the insulating casing for communicating the inner space and the exterior of the insulating casing. The circuit board is disposed in the inner space of the insulating casing. The resilient conductive element includes a connecting side for fixing on and electrically connecting with the circuit board. The resilient conductive element further includes a compressible side for facing the opening and being exposed therethrough. The thickness of the resilient conductive element is reduced when an external force is applied thereon and recovers when the external force is removed.
US09246144B2
A battery pack and a method for manufacturing the same are provided, which can protect a plurality battery cells from external shock or vibration by preventing the plurality battery cells from moving within a case. The battery pack includes a plurality of battery cells, a case accommodating the battery cells and including a plurality of injection holes, and a shock absorbing member integrally formed at the outside and inside of the case so as to penetrate the injection holes and supporting the battery cells.
US09246138B2
A light-emitting panel includes: a substrate and a light-emitting functional multilayer formed on the substrate, wherein the light-emitting functional multilayer including a first functional layer and a second functional layer, a thickness of part of the first functional layer positioned in a first light-emitting region is smaller than a thickness of part of the first functional layer positioned in a second light-emitting region, a thickness of part of the second functional layer positioned in the first light-emitting region is greater than a thickness of part of the second functional layer positioned in the second light-emitting region, and when the light-emitting functional multilayer is viewed in a layering direction, the first light-emitting region and the second light-emitting region are adjacent or distant from each other in a direction perpendicular to the layering direction, and each include a plurality of pixels that are each composed of a plurality of adjacent sub-pixels.
US09246130B2
An organic electroluminescence display device includes a thin film transistor substrate and a counter substrate, in which the thin film transistor substrate includes: a moisture blocking area that surrounds an outside of the display area and is made of only an inorganic material between the first substrate and the sealing film, and an auxiliary area between the display area and the moisture blocking area, and a thickness of areas of the counter substrate opposite to the auxiliary area and the moisture blocking area is thinner than a thickness of an area of the counter substrate opposite to the display area.
US09246127B2
An organic light emitting diode display includes a first substrate, an organic light emitting element, a sealant, and a second substrate. The first substrate includes a first groove disposed in a display area of the organic light emitting diode display and a second groove disposed outside the display area. The organic light emitting element is at least partially disposed in the first groove. The sealant is at least partially disposed in the second groove. The second substrate is disposed on the first substrate. The organic light emitting element is sealed between the first substrate and the second substrate via at least the sealant.
US09246126B2
An OLED display is disclosed. The display includes a rear substrate, a front substrate facing the rear substrate, a cell seal provided between the rear and front substrates to adhere the two substrates to each other, and a reinforcement member provided between the rear and front substrates adjacent to the cell seal to adhere the two substrates to each other.
US09246117B2
Described is an (organic) light-emitting diode ((O)LED) wherein the light-emitting layer comprises a blend of an electroluminescent semiconducting material with a ferro-electric material. Either of the electrodes forms a modulatable injection barrier with the ferro-electric material, the modulation requiring a voltage Vm serving to polarize or repolarize the ferro-electric material. With Vm being larger than the voltage Ve required for light emission, the (O)LED can be turned “on” or “off” by applying a pulse voltage to (re)polarize the ferro-electric material.
US09246115B2
An organic solar cell and a method of manufacturing the same.
US09246113B2
A dense binary memory switch device combines the function of a pass transistor and a memory cell and has low programming and operation voltages. The device includes a charge storage region coupled to a gate electrode through a gate dielectric layer and directly contacting a channel region. The charge storage region contains quantum structures, deep traps or combinations thereof and is charged by carriers injected from injection regions that are in direct contact with the charge storage region. Fabrication of the device at low temperatures compatible with back-end-of-line processing is further disclosed.
US09246095B2
An electronic device includes a semiconductor memory unit that includes a vertical electrode formed over a substrate and receiving a voltage through one end of the vertical electrode, a resistance variable layer formed along a side of the vertical electrode to be thinner going from one end to the other end, and a plurality of horizontal electrodes formed adjacent to the vertical electrode with the resistance variable layer disposed between the horizontal electrodes and the vertical electrode, and stacked over the substrate with a space from each other.
US09246094B2
Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The resistive switching nonvolatile memory cells may include a first layer disposed. The first layer may be operable as a bottom electrode. The resistive switching nonvolatile memory cells may also include a second layer disposed over the first layer. The second layer may be operable as a resistive switching layer that is configured to switch between a first resistive state and a second resistive state. The resistive switching nonvolatile memory cells may include a third layer disposed over the second layer. The third layer may be operable as a resistive layer that is configured to determine, at least in part, an electrical resistivity of the resistive switching nonvolatile memory element. The third layer may include a semi-metallic material. The resistive switching nonvolatile memory cells may include a fourth layer that may be operable as a top electrode.
US09246091B1
A metal silicon oxide barrier layer between a nitride electrode containing the same metal and an oxide variable-resistance layer in a ReRAM cell prevents the metal from diffusing into the variable-resistance layer and prevents oxygen from diffusing into and oxidizing the electrode. Compound oxides of the same metal and silicon with varying stoichiometries and metal/silicon ratios may optionally replace part or all of the variable-resistance layer, a defect-reservoir layer, or both. The metal nitride electrode may include a metal silicon nitride current-limiting portion. Optionally, all the layers sharing the common metal may be formed in-situ as part of a single unit process, such as atomic layer deposition.
US09246080B2
In order to obtain a ferroelectric thin film having good crystallinity and realizing high piezoelectric properties, and a production method therefor, provided is a ferroelectric thin film constituting a dielectric material having a perovskite structure that comprises Zr and Ti formed on a substrate, wherein a layer having a Zr ratio that is smaller than a predetermined ratio and having good crystallinity and a layer that realizes good piezoelectric properties and has a Zr ratio that is about as great as the predetermined ratio are combined. A production method is also provided.
US09246078B2
Various aspects as described herein are directed to piezoelectric materials. As consistent with one or more embodiments, an apparatus includes a nanomaterial and structures coupled to the nanomaterial. This nanomaterial-structure combination manifests piezoelectric characteristics, via the combination. In certain implementations, neither the nanomaterial nor the coupled structures independently exhibit piezoelectric characteristics, yet do so in combination.
US09246076B2
A production method for a thermoelectric conversion module having a thermoelectric conversion element and an electrode, which are metallurgically bonded together via a porous metal layer. The porous metal layer is made of nickel or silver and has a density ratio of 50 to 90%.
US09246070B2
In accordance with certain embodiments, a phosphor element at least partially surrounding a light-emitting die is shaped to influence color-temperature divergence.
US09246067B2
A semiconductor light emitting device which produces mixed light of a desired emission color by a combination of a semiconductor light emitting element and a wavelength converting layer containing a fluorescent substance, and a vehicle lamp including the semiconductor light emitting device. The wavelength converting layer has different wavelength conversion characteristics respectively at its portion covering an area of relatively high current density at light emission operation of the semiconductor light emitting element and at its portion covering an area of relatively low current density so as to reduce chromaticity difference over the light extraction surface of the mixed light due to non-uniformity of current density in the light emitting layer at light emission operation.
US09246066B1
A fluorescent composite resin substrate white light LED includes a fluorescent composite resin substrate, two conductive brackets, a light emitting unit, two conductive lines and a package material. The fluorescent composite resin substrate is formed from a mixture through a curing reaction. Each of the conductive brackets is partially connected to the substrate. The light emitting unit is disposed on the substrate. The conductive lines are connected to the light emitting unit and respectively connected to the conductive brackets. The package material is formed from a mixture through a curing reaction. By fixing the light emitting unit at the fluorescent composite resin substrate, when applied to white light LED operations, the present invention achieves effects of emitting light through six planes, having high light flux and good heat dissipation, and significantly increasing production yield rate and speed without incurring different color temperatures at front and reverse sides.
US09246062B2
Transparent ohmic contacts to p-GaN and other high-work-function (≧4.2 eV) semiconductors are fabricated from zinc stannate (e.g., ZnSnO3). ZnO and SnO2 may be sputtered from separate targets and annealed to form the zinc stannate. The Zn:Sn ratio may be tuned over the range between 1:2 and 2:1 to optimize bandgap, work function, conductivity, and transparency for the particular semiconductor and wavelength of interest. Conductivity may be improved by crystallizing the zinc stannate, by doping with up to 5 wt % Al or In, or both.
US09246057B2
Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
US09246048B2
Example embodiments are directed to light-emitting devices (LEDs) and methods of manufacturing the same. The LED includes a first semiconductor layer; a second semiconductor layer; an active layer formed between the first and second semiconductor layers; and an emission pattern layer including a plurality of layers on the first semiconductor layer, the emission pattern including an emission pattern for externally emitting light generated from the active layer.
US09246040B2
A thin film solar cell module according to an embodiment of the invention includes a substrate, a plurality of solar cells each including a first electrode on the substrate, a second electrode on the first electrode, and a photoelectric conversion unit between the first electrode and the second electrode, a ribbon positioned on each of first and second outermost solar cells among the solar cells, and a conductive adhesive part positioned between the first outermost solar cell and the ribbon and between the second outermost solar cell and the ribbon. The conductive adhesive part positioned between the second electrode of the first outermost solar cell and the ribbon includes a first connector, which is electrically connected to the first electrode, the photoelectric conversion unit, and the second electrode of the first outermost solar cell.
US09246035B2
An apparatus and method for portable solar panel assemblies configured to enable the unit to be transported by multiple means in order to provide both grid tied and off grid power as needed. Solar panel assemblies are configured to have a range of rotation of approximately 0 to 25 degrees in two directions to allow efficient sunlight capture. The solar panel assembly in the closed position will allow for more compact and aerodynamic profile when being transported.
US09246028B2
A silicon solar cell is manufactured by providing a carrier plate, and by applying a first contact pattern to the carrier plate. The first contact pattern includes a set of first laminar contacts. The silicon solar cell is further manufactured by applying a multitude of silicon slices to the first contact pattern, and by applying a second contact pattern to the multitude of silicon slices. Each first laminar contact of the set of first laminar contacts is in spatial laminar contact with maximally two silicon slices. The second contact pattern includes a set of second laminar contacts. Each second laminar contact of the set of second laminar contacts is in spatial laminar contact with maximally two silicon slices.
US09246017B2
An integrated MEMS inertial sensor device includes one or more three-axis MEMS inertial sensor devices, such as accelerometers, with dual or single proof mass configurations. These designs can be compact and can decouple the motion of each axis to minimize the measurement errors due to cross-axis sensitivity. Some embodiments include a frame to decouple the motion of two axes and to provide geometric symmetry. Some embodiments also include double-folded springs. In a specific embodiment, the three axes of an integrated MEMS accelerometer device are entirely decoupled. Thus, the actuation of each axis, through a force due to acceleration, has little or substantially no effect on the other axes.
US09246000B2
In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
US09245995B2
A semiconductor device includes a power metal-oxide-semiconductor (MOS) transistor including a semiconductor substrate, an impurity region on the semiconductor substrate, the impurity region having a first conductivity, a drift region in the impurity region, the drift region having the first conductivity, a body region in the impurity region adjacent to the drift region, the body region having a second conductivity different from the first conductivity, a drain extension insulating layer on the drift region, a gate insulating layer and a gate electrode sequentially stacked across a portion of the body region and a portion of the drift region, a drain extension electrode on the drain extension insulating layer, a drain region contacting a side of the drift region opposite to the body region, the drain region having the first conductivity, and a source region in the body region, the source region having the second conductivity.
US09245990B2
The present invention provides a silicon-compatible germanium-based high-hole-mobility transistor with high-hole-mobility germanium channel comprising a semiconductor material having a valence band offset instead of the conventional gate insulating film, a germanium channel region, and a quantum well formed by heterojunctions of the upper and lower portions of the germanium channel on a silicon substrate. Thus, the present invention enables to gain maximum hole mobility of the germanium channel by using the two-dimensional hole gas gathered into the quantum well for high-speed and low-power operations and device reliability improvement.
US09245989B2
Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, and drain and source contacts similarly coaxially wrap completely around the drain and source regions.
US09245988B2
An electrostatic discharge protection device has a substrate, a P-well, a N-well, and an isolation portion. The P-well and N-well formed in the substrate are neighboring to each other. Along a specific direction, the P-well has a first N-type, a first P-type, a second N-type, a second P-type, and a third N-type high doping regions sequentially located thereon, and the N-well has a third P-type, a fourth N-type, a fourth P-type, a fifth N-type, and a fifth P-type high doping regions sequentially located thereon. The first N-type, the third N-type, the first P-type, and the second P-type high doping regions are coupled to a ground end, the third P-type, the fifth P-type, the fourth N-type, and the fifth N-type high doping regions are coupled to a voltage supply end, and the second N-type and the fourth P type high doping regions are coupled to an input/output end.
US09245983B2
An embodiment of the disclosed invention is a method for manufacturing a semiconductor device, which includes the steps of: forming a first insulating film; performing oxygen doping treatment on the first insulating film to supply oxygen to the first insulating film; forming a source electrode, a drain electrode, and an oxide semiconductor film electrically connected to the source electrode and the drain electrode, over the first insulating film; performing heat treatment on the oxide semiconductor film to remove a hydrogen atom in the oxide semiconductor film; forming a second insulating film over the oxide semiconductor film; and forming a gate electrode in a region overlapping with the oxide semiconductor film, over the second insulating film. The manufacturing method allows the formation of a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability.
US09245978B2
Disclosed are a self-aligned thin film transistor controlling a diffusion length of a doping material using a doping barrier in a thin film transistor having a self-aligned structure and a method of manufacturing the same. The self-aligned thin film transistor with a doping barrier includes: an active layer formed on a substrate and having a first doping region, a second doping region, and a channel region; a gate insulating film formed on the channel region; a gate electrode formed on the gate insulating film; a doping source film formed on the first doping region and the second doping region; and a doping barrier formed between the doping source film and the first doping region and between the doping source film and the second doping region.
US09245975B2
A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.
US09245973B2
A method for manufacturing a semiconductor device having a field-effect transistor, including forming a trench in a semiconductor substrate, forming a first insulating film in the trench, forming an intrinsic polycrystalline silicon film over the first insulating film, and introducing first conductive type impurities into the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. Next, a second insulating film is formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film, upper part of the trench ton form a second gate electrode.
US09245970B2
A semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an interfacial layer over the semiconductor substrate, the interfacial layer having a capacitive effective thickness of less than 1.37 nanometers (nm). The semiconductor structure further includes a high-k dielectric layer over the interfacial layer.
US09245964B2
An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.
US09245955B2
An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress to the channel region of the NMOS transistors and compressive stress to the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.
US09245951B1
Device structures and fabrication methods for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.
US09245933B2
An electroluminescent (EL) device and a display device are disclosed. The OLED device comprises a base substrate; a plurality of pixel units arranged in an array are disposed on the base substrate; each pixel unit comprises sub-pixel units provided with EL structures; the EL structures each comprise a transparent anode, an emission layer (EML) and a transparent cathode disposed on the base substrate in sequence; the EL structure of each sub-pixel unit is divided into a transmissive area and a reflective area; and the reflective area of the EL structure is provided with a reflective layer. The EL device can achieve transparent display with the transmissive area of each sub-pixel unit, and meanwhile, the transmissive area for achieving transparent display can also realize normal display.
US09245931B2
An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a plurality of pixels and each pixel includes a first area configured to emit light and a second area configured to transmit external light therethrough. Each pixel also includes a first electrode formed in the first area and an organic layer formed in the first area and the second area, wherein the organic layer covers the first electrode. Each pixel further includes a second electrode covering at least the organic layer formed in the first area and having a first opening exposing at least a portion of the organic layer formed in the second area. A reflection prevention layer is formed substantially covering the organic layer formed in the second area. The reflection prevention layer has a refractive index lower than that of the organic layer.
US09245930B2
A method of manufacturing a display panel includes: a first step of forming a partition wall layer above a substrate; a second step of exposing the partition wall layer using a first photomask that has a mask pattern corresponding to a blue opening; a third step of exposing the partition wall layer using a second photomask that has a mask pattern corresponding to a red opening and a green opening; a fourth step of forming a partition wall by removing the partition wall layer to form the red opening, the green opening , and the blue opening in the partition wall layer; and a fifth step of forming a light emitting layer in each opening.
US09245917B2
A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.
US09245911B2
A semiconductor device used for a semiconductor relay includes: a first diode; a second diode; an electric field shield film for covering the second semiconductor island region, where the second diode is formed; and a wiring for electrically connecting the first diode to the second diode. The wiring is arranged so as to cross above a silicon oxide film surrounding the second semiconductor island region. The electric field shield film is positioned below the wiring, and has a cutout portion in an overlapping region which overlaps the wiring. By forming the cutout portion, end portions of the electric field shield film is arranged to be shifted. Therefore, formation of a deep concave portion which is based on a concave portion on the silicon oxide film and a step of the electric field shield film over the entire width of the wiring can be prevented, and the disconnection of the wiring can be prevented.
US09245907B2
A novel display device capable of excellent reflective display is provided. The display device includes a transistor including a gate electrode layer, a gate insulating layer over the gate electrode layer, a semiconductor layer over the gate insulating layer, and a source electrode layer and a drain electrode layer over the gate insulating layer and the semiconductor layer; a reflective electrode layer on the same plane as the source electrode layer and the drain electrode layer; a coloring layer overlapping with the reflective electrode layer; a pixel electrode layer overlapping with the coloring layer; and an anti-oxidation conductive layer connected to one of the source electrode layer and the drain electrode layer. The pixel electrode layer is connected to the transistor through the anti-oxidation conductive layer.
US09245897B2
A method for manufacturing a memory device may include obtaining a substrate structure that includes a substrate, an oxide material layer positioned on the substrate, a polysilicon material layer positioned on the oxide material layer, a first control gate and a second control gate positioned on the polysilicon material layer, and an offset oxide layer positioned between the first control gate and the second control gate. The method may further include the following steps: removing, using the offset oxide layer as a first mask, a portion of the polysilicon material layer for forming a polysilicon structure that includes a first step structure; forming a masking oxide layer on the offset oxide layer; removing, using the masking oxide layer as a second mask, a portion of the polysilicon structure for forming a floating gate polysilicon member that includes the first step structure and a second step structure.
US09245894B2
An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.
US09245863B2
According to example embodiments of inventive concepts, a semiconductor package apparatus includes a first semiconductor package including a first substrate, a first solder resist layer on the first substrate, and a first sealing member that covers and protects the first solder resist layer, and a plurality of solder balls on the first substrate. The plurality of solder balls includes a first solder ball having a first height and a second solder ball having a second height that is different from the first height. The first sealing member includes holes that expose the solder balls.
US09245862B1
An electronic component structure includes a primary redistribution structure having a primary redistribution structure terminal. A secondary redistribution structure is formed on the primary redistribution structure terminal. A buildup dielectric layer encloses the primary redistribution structure, where a cushion pad of the secondary redistribution structure is supported by the buildup dielectric layer. An interconnection ball is mounted to the secondary redistribution structure. Stress imparted upon the interconnection ball is transferred through the secondary redistribution structure and dissipated to the buildup dielectric layer through the cushion pad. The buildup dielectric layer is readily able to absorb this stress thus minimizing the probability of failure of the secondary redistribution structure including the interconnection ball formed thereon.
US09245861B2
A wafer process for MCSP comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer covering metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer and a thick metal layer at bottom surface of wafer in recessed space in a sequence; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and the metal seed and metal layers along the scribe line.
US09245856B2
A semiconductor device includes a wiring substrate. The wiring substrate includes a first surface, a second surface located at an opposite side of the first surface, a cavity formed in the first surface, an electrode pad formed on the first surface surrounding the cavity, and a high frequency wire exposed on the first surface. A semiconductor element is accommodated in the cavity. A bonding wire connects the semiconductor element and the electrode pad. A first protection film is arranged on the first surface of the wiring substrate to cover the first surface, the semiconductor element, the electrode pad, the bonding wire, and the high frequency wire.
US09245822B2
A semiconductor layout pattern includes a device layout pattern, a plurality of rectangular first dummy patterns having a first size, a plurality of rectangular second dummy patterns having varied second sizes, and a plurality of first via dummy patterns smaller than the second dummy patterns and arranged in a spatial range within the second dummy patterns.
US09245819B2
An electrical component package is disclosed comprising: an electrical component having an embedded surface, a structure attached to the electrical component opposite the embedded surface, a conductive adhesive directly attached to the embedded surface, where the conductive adhesive is shaped to taper away from the embedded surface, and an encapsulation material covering the conductive adhesive and the electrical component. In various embodiments, the tapered conductive adhesive facilitates the securing of the conductive adhesive to the electrical component by the encapsulation material. Also disclosed are various methods of forming an electrical component package having a single interface conductive interconnection on the embedded surface. The conductive interconnection is configured to maintain an interconnection while under stress forces. Further disclosed in a method of applied a conductive adhesive that enables design flexibility regarding the shape and depth of the conductive interconnection.
US09245812B2
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.
US09245803B1
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a Bessel beam shaper laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
US09245798B2
A method for at least partially filling a feature on a workpiece includes obtaining a workpiece including a feature having a high aspect ratio in the range of about 10 to about 80, depositing a first conformal conductive layer in the feature, and thermally treating the workpiece to reflow the first conformal conductive layer in the feature.
US09245796B1
A method of fabricating an interconnection structure according to an embodiment of the present invention, includes patterning a dielectric layer to form a first recession region, including a first nest-shaped recession region having a first width and a first line-shaped recession region having a second width, which is less than the first width. A guide spacer layer is formed on sidewalls of the first recession region to provide a second recession region including a second nest-shaped recession region in the first nest-shaped recession region. A self-assembling block copolymer material is formed to fill the second nest-shaped recession region. The self-assembling block copolymer material is annealed to form a polymer block domain and a polymer block matrix, surrounding the polymer block domain. The polymer block domain is removed to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is etched to form a via cavity.
US09245794B2
An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.
US09245789B2
The present invention addresses the problem of inhibiting the evolution of a poisoning gas to eliminate wiring-pattern resolution failures and thereby forming a desired wiring layer structure to provide functional elements having an improved property yield. This method for forming multi-layered copper interconnect on a semiconductor substrate comprises: forming a multilayer resist structure to form a given resist pattern on a substrate including an interlayer dielectric film that has via holes which have been formed in part thereof and filled with an SOC layer, the multilayer resist structure comprising an SOC layer, an SOG layer, an SiO2 layer, and a chemical amplification type resist superposed in this order from the substrate side; conducting etching using the resist pattern as a mask to form a pattern for a wiring layer and via plugs; and forming the wiring layer and the via plugs in the pattern.
US09245774B2
The present invention provides a semiconductor device with an improved yield ratio and reduced height and manufacturing cost; and a method of manufacturing the semiconductor device. According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a semiconductor element that is flip-chip connected to the substrate, and a molding portion that seals the semiconductor element. The side surfaces of the semiconductor element are enclosed by the molding portion. An upper surface of the semiconductor element is not enclosed by the molding portion. Damage to the side surfaces of the semiconductor element caused by an external impact when the semiconductor device is stored is minimized, because the molding portion protects the side surfaces of the semiconductor element. Accordingly, the yield ratio of the semiconductor device is improved. The height of the semiconductor device can also be reduced since the upper surface of the semiconductor element is not enclosed with the molding portion.
US09245771B2
Semiconductor packages having through electrodes and methods for fabricating the same are provided. The method may comprise providing a first substrate including a first circuit layer, forming a front mold layer on a front surface of the first substrate, grinding a back surface of the first substrate, forming a first through electrode that penetrates the first substrate to be electrically connected to the first circuit layer, providing a second substrate on the back surface of the first substrate, the second substrate including a second circuit layer that is electrically connected to the first through electrode, forming a back mold layer on the back surface of the first substrate, the back mold layer encapsulating the second substrate, and removing the front mold layer.
US09245769B2
Methods for processing a substrate are described herein. Methods can include positioning a substrate with an exposed surface comprising a silicon oxide layer in a processing chamber, biasing the substrate, treating the substrate to roughen a portion of the silicon oxide layer, heating the substrate to a first temperature, exposing the exposed surface of the substrate to ammonium fluoride to form one or more volatile products while maintaining the first temperature, and heating the substrate to a second temperature, which is higher than the first temperature, to sublimate the volatile products.
US09245768B2
Methods for controlling substrate uniformity in a thermal processing chamber include a measuring process to provide temperature-related quantities across a radius of a substrate, correlating substrate properties with processing parameters to simulate deformation of the substrate at various radial distances over a temperature range, a thermal process so that temperature of at least one reference region within the substrate matches a target set point temperature, measuring a temperature of at least one reference region as the substrate rotates, measuring deformation of the substrate as the substrate rotates, correlating measured temperatures of at least one reference region with simulated deformation of the substrate and measured temperature-related quantities of the substrate to calculate a simulated shape change of the substrate over a temperature range, tuning substrate flatness by adjusting lamp temperature profile across the substrate based on simulated shape change of the substrate and actual shape of the substrate.
US09245765B2
Implementations and techniques for applying a film to a semiconductor wafer and for processing a semiconductor wafer are generally disclosed.
US09245755B2
An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.
US09245749B2
A method of forming a Ga2O3-based crystal film includes epitaxially growing a Ga2O3-based crystal film on a (001)-oriented principal surface of a Ga2O3-based substrate at a growth temperature of not less than 750° C. A crystal multilayer structure includes a Ga2O3-based substrate with a (001)-oriented principal surface, and a Ga2O3-based crystal film formed on the principal surface of the Ga2O3-based substrate by epitaxial growth. The principal surface has a flatness of not more than 1 nm in an RMS value.
US09245746B2
The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.
US09245735B2
An upper electrode device applied to the film coating process has a splitter chamber and at least three gas diversion plates; a gas inlet is set on the splitter chamber; the at least three gas diversion plates were fixed on the inside walls of the splitter chamber and used for diverting and outputting the gas introduced into the splitter chamber through the gas inlet. By using the upper electrode device provided by the present disclosure can uniformize the gas used for coating in the film coating process, especially uniformize the gas in the perimeter area and the center area. Consequently, the uniformity of the thickness of the whole film coated is improved.
US09245733B2
A plasma lighting system includes a magnetron configured to generate microwaves, and a bulb filled with a main dose and an additive dose. The main dose and the additive dose generate light under the influence of microwaves and have maximum intensities of respective intrinsic wavelengths at different wavelengths. A motor is configured to rotate the bulb. A controller is connected to the motor. The controller adjusts the Revolutions Per Minute (RPM) of the bulb to thereby adjust a color temperature of light emitted from the bulb.
US09245732B2
A lighting apparatus is provided that includes a magnetron configured to generate microwaves having a predetermined frequency, a waveguide including a first wave guide space configured to introduce and guide the microwaves and a second wave guide space expanded from the first wave guide space, a resonator to which the microwaves are transmitted from the waveguide and a bulb located in the resonator, the bulb encapsulating a light emitting material and being configured to emit light in response to the transmitted microwaves. The second wave guide space is located in a transmission path of the microwaves transmitted from the magnetron to the resonator.
US09245728B2
A mass spectrometer is disclosed comprising a RF confinement device, a beam expander and a Time of Flight mass analyzer. The beam expander is arranged to expand an ion beam emerging from the RF confinement device so that the ion beam is expanded to a diameter of at least 3 mm in the orthogonal acceleration extraction region of the Time of Flight mass analyzer.
US09245727B2
The invention relates to the voltage supply of mass spectrometers, particularly electrostatic Kingdon ion analyzers, requiring extremely noise-free operating voltages. The invention proposes the use of passive charge storage devices, which operate without any feedback control and display no measurable noise or ripple if they are well shielded, instead of the usual actively operating high-voltage generators. Chemical charge storage devices or capacitors with good insulation can be used for this purpose. These may display slight voltage decreases due to continuous discharge, depending on their quality, but these decreases can be mathematically compensated.
US09245725B2
An ion trap device is disclosed. The device includes a series of electrodes that define an ion flow path. A radio frequency (RF) field is applied to the series of electrodes such that each electrode is phase shifted approximately 180 degrees from an adjacent electrode. A DC voltage is superimposed with the RF field to create a DC gradient to drive ions in the direction of the gradient. A second RF field or DC voltage is applied to selectively trap and release the ions from the device. Further, the device may be gridless and utilized at high pressure.
US09245724B2
An ion guide system includes an ion guide with pole rods, a device for laterally introducing an ion species, and a mass spectrometer for analyzing product ions of reactions between different ion species. The device is configured and positioned such that an RF field with at least two-fold rotational symmetry with respect to the axis is generated. The device includes shortened pole rods and/or further electrodes. The pole rods and the further electrodes have at least two-fold rotational symmetry. The symmetry of the RF field allows ions to travel straight ahead through the ion guide with no hindrance. Such arrangements are particularly suitable for bringing together largely loss-free positive and negative ion species for reacting them. The reactions may be used to fragment multiply charged biopolymer ions by electron transfer or to remove excess charges of multiply charged biopolymer ions.
US09245723B2
A method of operating a gas-filled collision cell in a mass spectrometer is provided. The collision cell has a longitudinal axis. Ions are caused to enter the collision cell. A trapping field is generated within the collision cell so as to trap the ions within a trapping volume of the collision cell, the trapping volume being defined by the trapping field and extending along the longitudinal axis. Trapped ions are processed in the collision cell and a DC potential gradient is provided, using an electrode arrangement, resulting in a non-zero electric field at all points along the axial length of the trapping volume so as to cause processed ions to exit the collision cell. The electric field along the axial length of the trapping volume has a standard deviation that is no greater than its mean value.
US09245721B2
The invention relates to the characterization of samples which are located in their many hundreds up to tens or hundreds of thousands on a sample support plate in a regular pattern, a so-called array, by ionization with matrix-assisted laser desorption and mass spectrometric measurement, for example. The invention proposes that the position of the sample pattern, and thus the position of each sample in the measuring instrument, for example a mass spectrometer, should be determined by measuring at least two finely structured internal position recognition patterns, such as fine crosses. The position recognition patterns are preferably applied as the samples are generated, with the same apparatus which also generates the sample pattern. A mass spectrometer in which laser spots with diameters of only four to five micrometers can be generated, which can preferably be positioned with an accuracy of one micrometer or better, is particularly suitable for the characterization.
US09245715B2
The present invention provides a drawing apparatus for performing drawing on a substrate with a plurality of charged particle beams, comprising a blanker array including first and second groups, each of which includes at least one blanker, a deflector configured to deflect the plurality of charged particle beams to scan the plurality of charged particle beams on the substrate, and a controller configured to respectively supply first and second control signals to the first and second groups at first and second timings, wherein the first and second groups are respectively arranged at such relative positions that a positional difference between respective drawing regions thereof, due to a difference between the first and second timings, in a scanning direction of the deflector is compensated for.
US09245714B2
Compression, transmission and decompression of gray-tone imagery data includes receiving a gray-tone image suitable for printing at least a portion of a pattern onto a substrate by operation of an electron beam lithography system, aggregating sets of lines of the gray-tone image into trilines, sequentially encoding each of the trilines of the gray-tone image by operation of one or more encoders, the one or more encoders equipped with a codebook configured to store a plurality of triline fragments and a write location and transmitting the encoded trilines of the gray-tone image to a set of decoders of the digital pattern generator via a set of data pathways established between the one or more encoders and each of the decoders.
US09245709B1
A charged particle beam specimen inspection system is described. The system includes an emitter for emitting at least one charged particle beam, a specimen support table configured for supporting the specimen, an objective lens for focusing the at least one charged particle beam, a charge control electrode provided between the objective lens and the specimen support table, wherein the charge control electrode has at least one aperture opening for the at least one charged particle beam, and a flood gun configured to emit further charged particles for charging of the specimen, wherein the charge control electrode has a flood gun aperture opening at which a conductive membrane is provided which is positioned between the flood gun and the specimen support table.
US09245700B2
A circuit breaker including a first and a second contact movable relative each other between an open position, in which the contacts are at a distance from each other, and a closed position, in which the contacts are in electrical contact with each other. The first contact includes one or more contact elements adapted to be in electrical contact with the second contact when the contacts are in the closed position, and a mesh made of metal arranged in thermal contact with the contact elements. The mesh is arranged to at least partly surround the contact elements to allow heat to conduct from the contact elements to the mesh.
US09245675B2
An apparatus for generating a pulsed magnetic field includes an insulating body, an electrical conductor positioned on the insulating body, and a ferromagnetic body having a hollow portion, wherein the insulating body and the electrical conductor are positioned in the hollow portion. In some embodiments of the present disclosure, the electrical conductor has at least one gap separating the electrical conductor into at least two parts, thereby allowing a current to flow through the at least two parts in parallel to generate a magnetic field in the insulating body.
US09245674B2
A rare-earth permanent magnetic powder, a bonded magnet, and a device comprising the bonded magnet are provided. The rare-earth permanent magnetic powder is mainly composed of 7-12 at % of Sm, 0.1-1.5 at % of M, 10-15 at % of N, 0.1-1.5 at % of Si, and Fe as the balance, wherein M is at least one element selected from the group of Be, Cr, Al, Ti, Ga, Nb, Zr, Ta, Mo, and V, and the main phase of the rare-earth permanent magnetic powder is of TbCu7 structure. Element Si is added into the rare-earth permanent magnetic powder for increasing the ability of SmFe alloy to from amorphous structure, and for increasing the wettability of the alloy liquid together with the addition of element M in a certain content, which enables the alloy liquid prone to be injected out of a melting device. The average diameter of the rare-earth permanent magnetic powder is in the range of 10-100 μm, and the rare-earth permanent magnetic powder is composed of nanometer crystals with average grain size of 10-120 nm or amorphous structure.
US09245672B2
An object of the disclosure is to provide a chip resistor without causing the disconnection in atmosphere of sulfidizing gas and without precipitating silver sulfide on its surface. The chip resistor of the present disclosure includes a resistor layer disposed on a top surface of a substrate; a first upper electrode layer disposed at both sides of the resistor layer and being electrically connected to the resistor layer; and a second upper electrode layer disposed on the first upper electrode layer and including between 75% by weight and 85% by weight (inclusive) of silver particles with an average particle diameter ranging from 0.3 um to 2 um, between 1% by weight and 10% by weight (inclusive) of carbon, and a resin.
US09245670B2
A wire structure, which may be configured for a semiconductor device, is disclosed. The wire may include an elongate flexible core formed of a conductor material and a cladding layer covering an outer surface of the core. The cladding layer may be a conductor. In various aspects the cladding layer and core have different grain sizes. An average grain size of the core material may be several orders of magnitude greater than an average grain size of the cladding layer material. The cladding layer may be an alloy having a varying concentration of a minor component across its thickness. Methods of forming a wire structure are also disclosed.
US09245664B2
A conductive metal composition comprising 50 to 94 wt % of silver particles having an average particle size in the range of 40 to 450 nm and having an aspect ratio of 3 to 1:1, 1 to 4 wt % of a thermoplastic polyester resin having a weight-average molar mass of 10000 to 150000, and 4 to 49 wt % of a diluent for the thermoplastic polyester resin.
US09245656B2
A system and method for reducing energetic proton flux trapped in the inner radiation belt by injecting Ultra Low Frequency (ULF) electromagnetic waves is disclosed. The ULF electromagnetic waves is generated by space or ground based transmitters and the frequency range is selected such that the injected waves are in gyrofrequency resonance with trapped 10 to 100 Mev protons. Pitch angle scattering of the trapped protons in gyro-resonance with the injected waves increases their precipitation rate by forcing their orbits into pitch angles inside the atmospheric loss-cone where they are lost by intaracting with the dense neutral atmosphere at altitudes below 100 km. The reduction of energetic proton flux trapped in the inner radiation belt allows use of commercial electronics with submicron feature size on Low Earth Orbit satellites and microsatellites without the operational constraints imposed by the presence of energetic proton fluxes trapped at the inner radiation belts.
US09245653B2
Apparatuses, systems, methods, and computer program products are disclosed for reduced level cell solid-state storage. A method includes determining that an erase block of a non-volatile storage device is to operate in a reduced level cell (RLC) mode. The non-volatile storage device may be configured to store at least three bits of data per storage cell. A method includes instructing the non-volatile storage device to program first and second pages of the erase block with data. A method includes instructing the non-volatile storage device to program a third page of the erase block with a predefined data pattern. Programming of a predefined data pattern may be configured to adjust which abodes of the erase block are available to represent stored user data values.
US09245647B2
An OTP memory cell and an OTP memory circuit. The OTP memory cell having a memory module, a write module, a read module, and a load module. Data may be written into the memory module once the write module is active; and data may be read out of the memory module once the read module is active. The OTP memory cell may also have a first latch module and a second latch module.
US09245628B2
A non-volatile semiconductor memory device includes a semiconductor layer of a first conductivity type, and a plurality of wells of a second conductivity type formed on the first semiconductor layer, the wells being arranged in a first direction. A memory block is arranged in each well. A plurality of word lines are provided, each word line being commonly connected to a plurality of NAND cell units in one memory block. A plurality of bit lines extend in a first direction, the bit lines being connected to first ends of the NAND cell units present in the memory blocks. A source line is connected to second ends of the NAND cell units. A well driver performs a control of selectively providing a first voltage or a second voltage higher than the first voltage to each well.
US09245627B2
A memory device includes a memory cell with an elementary SRAM-type cell and an elementary module coupled between a supply terminal and the elementary SRAM-type cell. The elementary module has a single nonvolatile EEPROM elementary memory cell that includes a floating gate transistor. The elementary module also has a controllable interconnection stage that can be controlled by a control signal external to the memory cell. The nonvolatile elementary memory cell and the controllable interconnection stage are connected to one another. The floating gate transistor of the nonvolatile memory cell is controllable to be turned off when a data item stored in the elementary SRAM-type cell is programmed into the nonvolatile elementary cell.
US09245618B2
A method for read measurement of resistive memory cells having s≧2 programmable cell-states includes applying to each cell at least one initial voltage and making a measurement indicative of cell current due to the initial voltage; determining a read voltage for the cell in dependence on the measurement; applying the read voltage to the cell; making a read measurement indicative of cell current due to the read voltage; and outputting a cell-state metric dependent on the read measurement; wherein the read voltages for cells are determined in such a manner that the cell-state metric exhibits a desired property.
US09245617B2
A nonvolatile memory comprising at least one ferromagnetic region having permittivity which changes from a first state to a second state of lower permittivity upon heating; at least one heater operatively associated with the at least one ferromagnetic region which selectively provides heat to the ferromagnetic region to change its permittivity; and a plurality of connectors operatively connected to the at least one heater and adapted to be connected to a current source that provides a current which causes the heater to change the at least one ferromagnetic region from a first state to a second state. Optionally, the memory is arranged as an array of memory cells. Optionally, each cell has a magnetic field sensor operatively associated therewith. Optionally, the nonvolatile memory is radiation hard. Also, a method of recording data by heating at least one ferromagnetic region to change its permittivity.
US09245615B2
A boost system for dual-port SRAM includes a comparator and a boost circuit. The comparator is configured to compare a first row address of a first port and a second row address of a second port, and output a first enable signal. The boost circuit is configured to boost a voltage difference between a first voltage source and a second voltage source according to the first enable signal.
US09245608B2
Perpendicular magnetic anisotropy (PMA) type magnetic random access memory cells are constructed with a composite PMA layer to provide a magnetic tunnel junction (MTJ) with an acceptable thermal barrier. A PMA coupling layer is deposited between a first PMA layer and a second PMA layer to form the composite PMA layer. The composite PMA layer may be incorporated in PMA type MRAM cells or in-plane type MRAM cells.
US09245605B2
A clock synchronization circuit includes a delay-locked loop (DLL) and a delay-locked control unit. The DLL is configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal. The delay-locked control unit configured to detect the locked state of the DLL, and to control the DLL based on the determined locked state.
US09245599B1
Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.
US09245587B2
A server device has a case, a backplane board mounted inside the case, a plurality of data storage device replacement mechanisms inserted inside the case, a plurality of first data storage devices and a plurality of second data storage devices. The data storage device replacement mechanism includes a tray, a connector assembly and a circuit board. The connector assembly is disposed inside an accommodation space of the tray and includes a first connector and a second connector. The circuit board is installed inside a second arrangement area of the tray and electrically connected to the first connector, the second connector and the backplane board. The first data storage device is arranged inside a first arrangement area of the tray and electrically connected to the first connector. The second data storage device is arranged inside the second arrangement area of the tray and electrically connected to the second connector.
US09245584B2
In an information processing apparatus, a cue playback decision unit 610 determines, based on recording information acquired from a recording information storage unit in which a recorded content having a program recorded and the recording information of the recorded content are associated with each other, whether or not a recorded content of a playback target is a recorded content whose recording is started prior to starting time of the program and which is to be played back by cue playback. A time confirmation unit 612 acquires, when it is determined that the recorded content is a recorded content to be played back by cue playback, recording starting time included in the recording information of the recorded content of the playback target from the recording information storage unit. A skip time acquisition unit 614 determines, based on the number of seconds of the recording starting time acquired by the time confirmation unit 612, a period of time to be skipped upon cue playback of the recorded content of the playback target.
US09245583B2
Group management of video device playback provides a mechanism for shared playback of recorded video content. Digital video playback devices are linked to a central management system through network connections which manages the shared playback, or a peer-to-peer network connection is used without the central management system. One user may be responsible for all actions affecting content playback, or all users may be permitted to affect content playback, with certain actions of those users limited in type or quantity. Group membership and group member permissions can be accomplished using the digital playback device through interactive interfaces implemented by the digital video playback device, or can be accomplished using a personal computer coupled to the device or central management system. Users may comment on shared playback using interactive video-based commentary functionality that may provide a text channel or graphical images that may be selected from a set of pre-configured commentary items.
US09245573B2
A method including depositing a plasmonic material at a temperature of at least 150° C.; and forming at least a peg of a near field transducer (NFT) from the deposited plasmonic material.
US09245570B2
Provided is a reproducing apparatus including: an optical system that obtains a signal light by radiating light emitted from a light source and generates a reference light from the light emitted from the light source, with respect to a recording medium, and that generates first to fourth groups of the signal light beams and the reference light beams, with respect to the superposed light in which the signal light and the reference light are superposed onto each other; a light receiving unit that receives light beams of the first to fourth groups of the signal light beams and the reference light beams respectively through first to fourth light receiving elements; and a reproduction signal generation circuit that calculates a first differential signal and a second differential signal, and that generates a reproduction signal by performing an arithmetic operation using the first and second differential signals.
US09245560B1
A data storage device is disclosed comprising a disk comprising a spiral track, and a head actuated over the disk, wherein the head comprises a read element offset radially from a write element by a reader/writer offset. The spiral track is first read to write a plurality of concentric servo sectors on the disk that define at least one concentric servo track on the disk. The spiral track is second read and the concentric servo sectors are read to measure the reader/writer offset.
US09245555B2
Stable, low resistance conductive adhesive ground connections between motor contacts and a gold-plated contact area on a stainless steel component of a dual stage actuated suspension. The stainless steel component can be a baseplate, load beam, hinge, motor plate, add-on feature or flexure.
US09245547B1
Method and apparatus for a magnetic sensor device having a magnetic field sensing element to generate an output signal and a signal processing module coupled to the magnetic field sensing element, the signal processing module including a linearization module to apply a third order Taylor expansion term to the output signal generated by the magnetic field sensing element. An output module can receive the linearized signal from the linearization module and provide a device output signal.
US09245545B1
A method of forming a single layer inductive coil structure includes forming a first conductive coil on a substrate, forming an insulating layer by atomic layer deposition (ALD) over the first coil and the substrate, and forming one or more additional conductive coils on each of adjacent sides of the first coil insulated from the first coil and the substrate by the insulating layer. A method of forming a stacked layer inductive coil includes forming a cavity in a substrate, forming a first coil in the cavity wherein the cavity has an atomic layer deposition (ALD) layer, forming a second coil in the cavity adjacent to the first coil and separated by the ALD layer from the first coil, forming an insulating layer over the first and second coil, and forming a third coil on the insulating layer.
US09245540B1
An electrical circuit includes: a controlled switch; one or more temperature sensors in thermal contact with the controlled switch; and a control unit configured to: receive a temperature signal from the one or more temperature sensors; compare the received temperature signal to a predetermined threshold; and in response to the received temperature signal exceeding the predetermined threshold, render the controlled switch inoperative.
US09245538B1
The present technology provides robust, high quality expansion of the speech within a narrow bandwidth acoustic signal which can overcome or substantially alleviate problems associated with expanding the bandwidth of the noise within the acoustic signal. The present technology carries out a multi-faceted analysis to accurately identify noise within the narrow bandwidth acoustic signal. Noise classification information regarding the noise within the narrow bandwidth acoustic signal is used to determine whether to expand the bandwidth of the narrow bandwidth acoustic signal. By expanding the bandwidth based on the noise classification information, the present technology can expand the speech bandwidth of the narrow bandwidth acoustic signal and prevent or limit the bandwidth expansion of the noise.
US09245533B2
The present proposes new methods and an apparatus for enhancement of source coding systems utilizing high frequency reconstruction (HFR). It addresses the problem of insufficient noise contents in a reconstructed highband, by Adaptive Noise-floor Addition. It also introduces new methods for enhanced performance by means of limiting unwanted noise, interpolation and smoothing of envelope adjustment amplification factors. The present invention is applicable to both speech coding and natural audio coding systems.
US09245524B2
The present invention can increase the types of noises that can be dealt with enough to enable speech recognition with a speech recognition rate of high accuracy.A speech recognition device of the present invention performs processes of: storing, in a manner to relate them to each other, a suppression coefficient representing a noise suppression amount and an adaptation coefficient representing an adaptation amount of a noise model, where the noise model is generated on the basis of a predetermined noise and is to be compounded (synthesized) to a clean acoustic model generated on the basis of a voice including no noise; estimating noise from an input signal; suppressing from the input signal a portion of the estimated noise of an amount specified by a suppression amount specified on the basis of the suppression coefficient; generating an adapted acoustic model which is noise-adapted, by compounding (synthesizing) the clean acoustic model with a noise model generated on the basis of the estimated noise in accordance with an adaptation amount specified on the basis of the adaptation coefficient; and recognizing voice on the basis of the noise-suppressed input signal and the generated adapted acoustic model.
US09245523B2
The subject matter discloses a method for expansion of search queries on large vocabulary continuous speech recognition transcripts comprising: obtaining a textual transcript of audio interaction generated by the large vocabulary continuous speech recognition; generating a topic model from the textual transcripts; said topic model comprises a plurality of topics wherein each topic of the plurality of topics comprises a list of keywords; obtaining a search term; associating a topic from the topic model with the search term; and generating a list of candidate term expansion words by selecting keywords from the list of keywords of the associated topic; said candidate term expansion words are of high probability to be substitution errors of the search term that are generated by the large vocabulary continuous speech recognition.
US09245514B2
The various embodiments relate generally to systems, devices, apparatuses, and methods for providing audio streams to multiple listeners, and more specifically, to a system, a device, and a method for providing independent listener-specific audio streams to multiple listeners using a common audio source, such as a set of loudspeakers, and, optionally, a shared audio stream. In some embodiments, a method includes identifying a first audio stream for reception at a first region to be canceled at a second region, and generating a cancellation signal that is projected in another audio stream destined for the second region. The cancellation signal and the first audio steam are combined at the second region. Further, a compensation signal to reduce the cancellation signal at the first region can be generated.
US09245512B2
An acoustic antenna element for receiving and/or emitting low-frequency underwater waves comprises an acoustic panel formed by at least one acoustic pick-up enclosed in a flexible jacket, the acoustic panel being generally rectangular and being mounted against a curved support by a mounting device including a clamping device comprising at least two flanges the ends of which are mounted on the support, the respective flanges comprising at least one tie between the two ends thereof, and the clamping device capable of adjusting the tension in the ties between the two respective ends thereof, the flanges being arranged so that the support is bent between the two respective ends of the ties and so that the panel is clamped against the support by the ties when they are under tension.
US09245506B2
A resonance tone generation apparatus 20 is applied to an electronic musical instrument DM having a tone generator for generating, in accordance with a tone generation instruction signal having a key number n, a musical tone signal indicative of a piano sound having a key tone pitch specified by the key number. In the resonance tone generation apparatus 20, the key numbers n are assigned. The resonance tone generation apparatus 20 has a plurality of resonance tone generation circuits 30(n) each being configured to have a plurality of resonance frequencies and each retrieving a musical tone signal indicative of a musical sound of the piano and generating a musical tone signal indicative of a resonance tone which imitates a sound of strings of the piano, the sound being resonated by the piano sound indicated by the retrieved musical tone signal. The resonance tone generation apparatus 20 also has a resonance circuit setting portion 60 which allows respective resonance frequencies of the resonance tone generation circuit 30(n) to coincide with frequencies of a fundamental tone and overtones of a musical sound PS(n) generated by the tone generator in accordance with tone generation instruction information including the key number n.
US09245500B1
The present invention is directed to a non-transitory machine readable storage medium containing program instructions for displaying digital content while preventing image capture, the non-transitory machine readable storage medium configured to generating a mask to superimpose upon a display object with the mask including one or more transparent portions and one or more opaque portions that blocks the display object therebeneath from viewing; and moving the one or more transparent portions of the mask incrementally to expose various portions of the display object in sequence. The display object may be image, text, video, or any combination thereof. The one or more transparent portions of the mask may have a linear shape extending along a first direction and may move in a second direction substantially perpendicular to the first direction. Alternatively, the one or more transparent portions of the mask may have a sector-shaped opening that rotates to expose the display object.
US09245499B1
Processing a set of images is disclosed, including: receiving a set of images; and searching for a representation of a user's face associated with the set of images and a plurality of sets of extrinsic information corresponding to respective ones of at least a subset of the set of images. Rendering a glasses frame is disclosed, including: receiving a selection associated with the glasses frame; rendering the glasses frame using at least a representation of a user's face and a set of extrinsic information corresponding to an image in a recorded set of images; and overlaying the rendered glasses frame on the image.
US09245498B2
The general field of the invention is that of display systems comprising means for generating graphic symbols and an associated semitransparent display device. The display device according to the invention has two overlaid semitransparent flat display screens, one passive and the other active, each symbol displayed on the semitransparent display device comprising a first representation and a second representation. The first representation is displayed on the first display screen with a low transmission rate for the light and with a predetermined first size. The second representation is displayed on the second display screen in the same place as the first representation, with a luminance and a predetermined second size that is smaller than the first size so that the second representation is overlaid on the first representation and the displayed symbol appears bright with a dark border.
US09245494B2
A method and apparatus that are capable of identifying corresponding screen displays that convey color coded information and identifying whether color coded information found in corresponding screen displays is likely to be accessible or inaccessible to a colorblind individual. The method and apparatus are capable of receiving data corresponding to a plurality of screen displays including information encoded in color. The method and apparatus are capable of identifying corresponding screen displays from the plurality of screen displays. The method and apparatus are further capable of detecting text and color encoded information that are different in the first and second corresponding screen displays at first and second locations, respectively. The method and apparatus are further capable of determining a proximity of the first and the second locations when there is text that is different in the first and second corresponding screens at the first location, and generating a colorblindness accessibility indicator based on whether text that is different was detected/and or the determined proximity.
US09245485B1
Techniques for generating dithered images for display on electronic paper displays set to one-bit display modes are described herein. An electronic device having an electronic paper display sets a display mode parameter associated with the electronic paper display to a one-bit display mode. The electronic device or a remote service further generates a dithered image from a monochrome image based at least in part on a one-bit dithering algorithm. While the display mode parameter is set to the one-bit display mode, the electronic device then displays the dithered image on the electronic paper display.
US09245457B2
Golf performance and equipment characteristics may be determined by analyzing the impact between a golf ball and an impacting surface. In some examples, the impacting surface may be a golf club face. The impact between the golf ball and the surface may be measured based on sound and/or motion sensors (e.g., gyroscopes, accelerometers, etc.). Based on motion and/or sound data, various equipment-related information including golf ball compression, club head speed and impact location may be derived. Such information and/or other types of data may be conveyed to a user to help improve performance, aid in selecting golf equipment and/or to insure quality of golfing products.
US09245449B1
Methods and apparatus for providing trajectory planning for an aircraft based on constraint processing are disclosed. The method may take into consideration the dynamic or real-time operational and environmental factors, and utilizes constraint processing to provide trajectory optimizations between the end points of the flight. The trajectory planning method may be performed utilizing a computer or processor onboard the aircraft. The method may include receiving a starting location and an ending location for a phase of flight of the aircraft; receiving a set of constraints from multiple systems and sensors for the phase of flight of the aircraft, wherein operations of the aircraft during the phase of flight are subject to the set of constraints; and analyzing the set of constraints to determine an optimal trajectory between the starting location and the ending location, the optimal trajectory is determined based on compliance with the set of constraints.
US09245445B2
An optically-based target detection system includes a holographic detection filter designed to produce a concentrated spot when a target is present.
US09245439B2
A method, system, and apparatus for temporarily disarming a barrier alarm in a security system is described. In one embodiment, a method for temporarily disarming a barrier alarm is described, comprising receiving an indication to disarm the barrier alarm, the indication generated at the barrier alarm by a user, disarming the barrier alarm in response to receiving the indication, re-arming the barrier alarm upon the occurrence of a predetermined condition.
US09245438B2
A water leak detector including a housing defining a retention reservoir, and a coupler connected to the housing and configured to secure the housing to a water pipe. A switch is supported by the housing and is configured to detect water at a predetermined level within the reservoir. An indicator may be an electrical communication with the switch to provide an indication to a user when water has reached the predetermined level within the reservoir.
US09245430B1
A beverage koozie having a wireless locator that emits sounds under the control of a key fob. The koozie has an interior switch that causes a sound generator to emit sound when a beverage is placed in the koozie. The sound generator can also be activated by a key fob. In response to RF from the key fob the sound generator emits an audible signal to enable a user to find the koozie. The sound generator can also emit entertaining sounds when directed by the key fob.
US09245428B2
Systems and methods for haptic remote control gaming are disclosed. In one embodiment a portable multifunction device receives information from a remotely controllable device. The portable multifunction device can be operable as a remote control for the remotely controllable device. The portable multifunction device may be a smartphone, a tablet computer, or another suitable electronic device. The portable multifunction device can determine a haptic effect based at least in part on the information received from the remotely controllable device. The portable multifunction device may generate a signal configured to cause an actuator to output the determined haptic effect. The portable multifunction device can output the signal.
US09245427B2
A system and method for synchronizing a plurality of networked fire alarm panels is disclosed. A plurality of fire panels (i.e., nodes) are arranged on a peer-to-peer network, such as a token ring network. One node is designated as a SyncHost, and the remaining nodes are periodically reset to the clock time associated with the SyncHost to ensure all nodes remain substantially synchronized to a single time. As such, when an alarm condition is signaled, the visual notification devices (i.e., strobe lights) of all the fire panels (nodes) will flash at substantially the same time, in accordance with government guidelines. To accomplish the synchronization, the SyncHost sends periodic attendance polls around the network, noting the transit times of the polls. The individual nodes on the network also note times associated with the polls. The SyncHost sends a sync message to the nodes, and each of the individual nodes resets its internal clock according to the sync message and internal compensations calculated that are based on the attendance poll transit times. Other embodiments are disclosed and claimed.
US09245418B2
A gaming machine comprises a display and a game controller arranged to control images of symbols displayed on the display. The game controller is arranged to play a game wherein at least one random event is caused to be displayed on the display and, if a predefined winning event occurs, a prize is awarded. A plurality of sub-games constitute the game displayed on the display. As an initial display, fewer than a full set of images of each of the sub-games are displayed to show a partial outcome of the game, the fewer than the full set of images being representative of a determination of an expected value for each of the sub-games.
US09245416B2
A game token having a counter system including a denomination value, a housing, and a token identification element at least partially contained within the housing is disclosed. The token identification element includes an antenna configured to receive and transmit a signal, a memory configured to store a plurality of different types of token data, a counter configured to modify and maintain a read attempt value, and a processor or control logic. The processor or logic control configured to, upon a read attempt of the memory by a reader, compare a signature of the reader against the one or more authorized reader signatures, and generate an alert when the signature does not match any one of the one or more authorized reader signatures.
US09245415B2
When the player identifies herself to a gaming machine at a casino, for example by inserting a player tracking card into the card reader, she is, at generally the same time, logging onto a game provider's backend system (the game provider being different from the casino operator). This concurrent sign-on to the game provider's system is done in a non-intrusive, transparent, and passive manner. The player is not distracted from the normal steps leading to game play on the machine until she is ready to redeem points with the game provider or for some reason additional authentication is needed from the player. By virtue of this single sign-on to the game provider network, in addition to continuing game play across different casinos, the player can publish events to the Internet, such as on social networking sites, take advantage of offers targeted specifically for her, or facilitate responsible gaming programs.
US09245414B2
A gaming system and method of rewarding players of electronic gaming machines connected by a network to a host computer, including storing player-useable points at a network-accessible location, enabling a player to convert at least some of the points into monetary units at a conversion rate, wherein the monetary units are convertible into credits for wagering on at least one of the electronic gaming machines, awarding a personal points conversion rate multiplier to a player, and applying the points conversion rate multiplier to the conversion rate.
US09245405B2
A cabinet system for securely storing items includes a cabinet housing, a controller, and at least one drawer unit. The cabinet housing has a locking mechanism, and the controller is in communication with the cabinet housing and configured to operate the locking mechanism. The drawer unit is designed to be releasably locked at least partially within the cabinet housing by the locking mechanism, and slidable within a portion of the cabinet housing when released by the locking mechanism. The drawer unit includes at least one storage compartment, a cover, memory, and a power source. The storage compartment is configured to store at least one item therein. The cover is movable to an open configuration and a closed configuration. When the cover is in the closed configuration, the cover limits access to the item of the storage compartment. The memory is powered by the power source and is configured to store data associated with a movement of the cover.
US09245395B2
A rider characteristic determining apparatus capable of determining characteristics of a rider controlling a saddle riding type vehicle, and a saddle riding type vehicle including the same, are configured such that the rider's characteristics are determined from a turning movement of the saddle riding type vehicle which reflects results of the rider controlling the saddle riding type vehicle. This enables a stable characteristic determination regardless of individual operation or control by the rider. Further, a turning performance score of the vehicle is calculated based on at least one of vehicle state amounts of a roll direction, a pitch direction and a caster angle which influence the steering angle of the saddle riding type vehicle. This enables a proper evaluation of the turning characteristic of the saddle riding type vehicle.
US09245387B2
Methods for positioning virtual objects within an augmented reality environment using snap grid spaces associated with real-world environments, real-world objects, and/or virtual objects within the augmented reality environment are described. A snap grid space may comprise a two-dimensional or three-dimensional virtual space within an augmented reality environment in which one or more virtual objects may be positioned. In some embodiments, a head-mounted display device (HMD) may identify one or more grid spaces within an augmented reality environment, detect a positioning of a virtual object within the augmented reality environment, determine a target grid space of the one or more grid spaces in which to position the virtual object, determine a position of the virtual object within the target grid space, and display the virtual object within the augmented reality environment based on the position of the virtual object within the target grid space.
US09245374B2
Three-dimensional scanning is improved with the use of space carving to exclude certain scan results from processing and display. Using space carving techniques, a spatial matrix is maintained to store data on volumetric regions (or voxels) known to be empty. By excluding or modifying processing of outlier data from within these unoccupied voxels, a three-dimensional reconstruction process can achieve concurrent improvements in accuracy and speed. In addition, a real time display of scan results can be improved by modifying how such outliers are rendered.
US09245351B2
Provided are a color evaluation apparatus and the like capable of evaluating the appropriateness of a color scheme in an image to be evaluated. A color evaluation apparatus 101 includes a division unit 102 that identifies a partial region of an input image, an acquisition unit 103 that acquires color information for identifying a color contained in the partial region and a first character string contained in the partial region, an extraction unit 104 that extracts a second character string which is associated in advance with the color information, and an evaluation unit 105 that evaluates appropriateness of the color information according to a result of comparing the first character string and the second character string.
US09245346B2
A method for optically scanning and measuring a scene by a three-dimensional (3D) measurement device in which multiple scans are generated to then be registered in a joint coordinate system of the scene. At first at least one cluster is generated from at least one scan, further scans are registered for test purposes in the coordinate system of the cluster, and registering is then confirmed if specified quality criteria are fulfilled and the generated clusters are then joined, for which purpose pairs are formed of selected scans and/or clusters to form pairs, the pairs are registered for test purposes and registering is confirmed if appropriate.
US09245336B2
A method includes obtaining first volumetric image data, which is acquired at a first time, including a region of interest with a structural feature located at a first position. The method further includes obtaining second volumetric image data, which is acquired at a second different time, including the region of interest with the structural feature located at a second different position. The method further includes determining a registration transformation that registers the first and second volumetric image data such that the at least one structural feature in the first volumetric image data aligns with the at least one structural feature in the second volumetric image data. The registration transformation is based at least on a contour guided deformation registration. The method further includes generating a signal indicative of the registration transformation.
US09245333B1
An imaging system may include an image sensor and a transparent protective layer formed within the field-of-view of the image sensor. The imaging system may include a light source that emits light in a predetermined pattern. The imaging system may include circuitry that may detect a reflected version of the predetermined pattern of light in image data captured by image sensor. In response, the imaging system may determine an obstruction is present within the field-of-view of the image sensor. The obstruction may be located on the transparent protective layer and may be within 10 centimeters of the image sensor. The light source and image sensor may be located in the interior of a vehicle and oriented to face the exterior of the vehicle. The imaging system may use the image data captured by the image sensor to perform vehicle assist functions for the vehicle.
US09245321B2
A method for a parallel image reconstruction is disclosed. The method includes (a) acquiring image information by channel via parallel coils in a magnetic resonance imaging (MRI) scanner; (b) extracting low-frequency signals from the image information; (c) reconstructing low-frequency images from the low-frequency signals; (d) generating filter banks by using the low-frequency images; and (f) reconstructing a final image by using the filter banks. The generating of the filter banks includes separately generating low-frequency image information for reconstruction of magnitude information and low-frequency image information for reconstruction of phase information, and then separately generating a filter for reconstruction of the magnitude information and a filter for reconstruction of the phase information.
US09245318B2
Some embodiments are directed to a method of automatically modifying a scanned image of a page from an input document comprising a plurality of pages. First, scanned images of the plurality of pages are obtained. Next, a user selection for an output orientation of an output document and optionally value of N for an N-Up operation is received. Thereafter, input orientation of each scanned image is detected. Then, the scanned image is rotated, based on the detected input orientation, the output orientation and the value of ‘N’ if provided by the user. Next, the rotated scanned image content is resized so that it fits on a page. Finally, the output document is prepared that includes pages in the output orientation.
US09245315B2
In an example embodiment a method, apparatus and computer program product are provided. The method includes facilitating receipt of a light-field image, determining one or more depth levels in the light-field image and generating a plurality of images from the light-field image. The method includes determining one or more registration matrices corresponding to the one or more depth levels between an image and one or more remaining images of the plurality of images. The method includes performing a super-resolution of the image and the one or more remaining images based on the one or more registration matrices to generate a super-resolved image of the image.
US09245309B2
Providing feedback regarding potential detectability by a decoder of a watermark message produced by a watermarking encoder includes receiving a watermark detectability indication that does not directly correspond to detectability of the watermark message by the decoder but is only a proxy for detectability of the watermark message by the decoder, transforming the watermark detectability indication into an enhancement indication corresponding to a prescribed enhancement to a watermark signal in which the watermark message is embedded based on the watermark detectability indication, and transmitting the enhancement indication to enhance the watermark signal thereby enhancing detectability of the watermark message.
US09245307B2
Technologies are generally described for projecting structured light patterns onto an Augmented Reality (AR) scene in order to track AR camera motion in AR systems. In some examples, structured light patterns may be projected onto the AR scene from a light source in the same plane as the AR camera in order to preserve a consistent reference point for detecting the structured light pattern. The AR camera may detect the structured light patterns and determine the location of the AR camera based on a distance analysis of the detected structured light patterns. Based on the changing locations of the AR camera, the system may track the movement of the AR camera as its location relative to the AR scene changes.